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Linux/arch/arm/mm/alignment.c

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  1 /*
  2  *  linux/arch/arm/mm/alignment.c
  3  *
  4  *  Copyright (C) 1995  Linus Torvalds
  5  *  Modifications for ARM processor (c) 1995-2001 Russell King
  6  *  Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
  7  *  - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
  8  *    Copyright (C) 1996, Cygnus Software Technologies Ltd.
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License version 2 as
 12  * published by the Free Software Foundation.
 13  */
 14 #include <linux/moduleparam.h>
 15 #include <linux/compiler.h>
 16 #include <linux/kernel.h>
 17 #include <linux/errno.h>
 18 #include <linux/string.h>
 19 #include <linux/proc_fs.h>
 20 #include <linux/seq_file.h>
 21 #include <linux/init.h>
 22 #include <linux/sched.h>
 23 #include <linux/uaccess.h>
 24 
 25 #include <asm/cp15.h>
 26 #include <asm/system_info.h>
 27 #include <asm/unaligned.h>
 28 
 29 #include "fault.h"
 30 
 31 /*
 32  * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
 33  * /proc/sys/debug/alignment, modified and integrated into
 34  * Linux 2.1 by Russell King
 35  *
 36  * Speed optimisations and better fault handling by Russell King.
 37  *
 38  * *** NOTE ***
 39  * This code is not portable to processors with late data abort handling.
 40  */
 41 #define CODING_BITS(i)  (i & 0x0e000000)
 42 #define COND_BITS(i)    (i & 0xf0000000)
 43 
 44 #define LDST_I_BIT(i)   (i & (1 << 26))         /* Immediate constant   */
 45 #define LDST_P_BIT(i)   (i & (1 << 24))         /* Preindex             */
 46 #define LDST_U_BIT(i)   (i & (1 << 23))         /* Add offset           */
 47 #define LDST_W_BIT(i)   (i & (1 << 21))         /* Writeback            */
 48 #define LDST_L_BIT(i)   (i & (1 << 20))         /* Load                 */
 49 
 50 #define LDST_P_EQ_U(i)  ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
 51 
 52 #define LDSTHD_I_BIT(i) (i & (1 << 22))         /* double/half-word immed */
 53 #define LDM_S_BIT(i)    (i & (1 << 22))         /* write CPSR from SPSR */
 54 
 55 #define RN_BITS(i)      ((i >> 16) & 15)        /* Rn                   */
 56 #define RD_BITS(i)      ((i >> 12) & 15)        /* Rd                   */
 57 #define RM_BITS(i)      (i & 15)                /* Rm                   */
 58 
 59 #define REGMASK_BITS(i) (i & 0xffff)
 60 #define OFFSET_BITS(i)  (i & 0x0fff)
 61 
 62 #define IS_SHIFT(i)     (i & 0x0ff0)
 63 #define SHIFT_BITS(i)   ((i >> 7) & 0x1f)
 64 #define SHIFT_TYPE(i)   (i & 0x60)
 65 #define SHIFT_LSL       0x00
 66 #define SHIFT_LSR       0x20
 67 #define SHIFT_ASR       0x40
 68 #define SHIFT_RORRRX    0x60
 69 
 70 #define BAD_INSTR       0xdeadc0de
 71 
 72 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
 73 #define IS_T32(hi16) \
 74         (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
 75 
 76 static unsigned long ai_user;
 77 static unsigned long ai_sys;
 78 static unsigned long ai_skipped;
 79 static unsigned long ai_half;
 80 static unsigned long ai_word;
 81 static unsigned long ai_dword;
 82 static unsigned long ai_multi;
 83 static int ai_usermode;
 84 
 85 core_param(alignment, ai_usermode, int, 0600);
 86 
 87 #define UM_WARN         (1 << 0)
 88 #define UM_FIXUP        (1 << 1)
 89 #define UM_SIGNAL       (1 << 2)
 90 
 91 /* Return true if and only if the ARMv6 unaligned access model is in use. */
 92 static bool cpu_is_v6_unaligned(void)
 93 {
 94         return cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U);
 95 }
 96 
 97 static int safe_usermode(int new_usermode, bool warn)
 98 {
 99         /*
100          * ARMv6 and later CPUs can perform unaligned accesses for
101          * most single load and store instructions up to word size.
102          * LDM, STM, LDRD and STRD still need to be handled.
103          *
104          * Ignoring the alignment fault is not an option on these
105          * CPUs since we spin re-faulting the instruction without
106          * making any progress.
107          */
108         if (cpu_is_v6_unaligned() && !(new_usermode & (UM_FIXUP | UM_SIGNAL))) {
109                 new_usermode |= UM_FIXUP;
110 
111                 if (warn)
112                         printk(KERN_WARNING "alignment: ignoring faults is unsafe on this CPU.  Defaulting to fixup mode.\n");
113         }
114 
115         return new_usermode;
116 }
117 
118 #ifdef CONFIG_PROC_FS
119 static const char *usermode_action[] = {
120         "ignored",
121         "warn",
122         "fixup",
123         "fixup+warn",
124         "signal",
125         "signal+warn"
126 };
127 
128 static int alignment_proc_show(struct seq_file *m, void *v)
129 {
130         seq_printf(m, "User:\t\t%lu\n", ai_user);
131         seq_printf(m, "System:\t\t%lu\n", ai_sys);
132         seq_printf(m, "Skipped:\t%lu\n", ai_skipped);
133         seq_printf(m, "Half:\t\t%lu\n", ai_half);
134         seq_printf(m, "Word:\t\t%lu\n", ai_word);
135         if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
136                 seq_printf(m, "DWord:\t\t%lu\n", ai_dword);
137         seq_printf(m, "Multi:\t\t%lu\n", ai_multi);
138         seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode,
139                         usermode_action[ai_usermode]);
140 
141         return 0;
142 }
143 
144 static int alignment_proc_open(struct inode *inode, struct file *file)
145 {
146         return single_open(file, alignment_proc_show, NULL);
147 }
148 
149 static ssize_t alignment_proc_write(struct file *file, const char __user *buffer,
150                                     size_t count, loff_t *pos)
151 {
152         char mode;
153 
154         if (count > 0) {
155                 if (get_user(mode, buffer))
156                         return -EFAULT;
157                 if (mode >= '' && mode <= '5')
158                         ai_usermode = safe_usermode(mode - '', true);
159         }
160         return count;
161 }
162 
163 static const struct file_operations alignment_proc_fops = {
164         .open           = alignment_proc_open,
165         .read           = seq_read,
166         .llseek         = seq_lseek,
167         .release        = single_release,
168         .write          = alignment_proc_write,
169 };
170 #endif /* CONFIG_PROC_FS */
171 
172 union offset_union {
173         unsigned long un;
174           signed long sn;
175 };
176 
177 #define TYPE_ERROR      0
178 #define TYPE_FAULT      1
179 #define TYPE_LDST       2
180 #define TYPE_DONE       3
181 
182 #ifdef __ARMEB__
183 #define BE              1
184 #define FIRST_BYTE_16   "mov    %1, %1, ror #8\n"
185 #define FIRST_BYTE_32   "mov    %1, %1, ror #24\n"
186 #define NEXT_BYTE       "ror #24"
187 #else
188 #define BE              0
189 #define FIRST_BYTE_16
190 #define FIRST_BYTE_32
191 #define NEXT_BYTE       "lsr #8"
192 #endif
193 
194 #define __get8_unaligned_check(ins,val,addr,err)        \
195         __asm__(                                        \
196  ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
197  THUMB( "1:     "ins"   %1, [%2]\n"     )               \
198  THUMB( "       add     %2, %2, #1\n"   )               \
199         "2:\n"                                          \
200         "       .pushsection .fixup,\"ax\"\n"           \
201         "       .align  2\n"                            \
202         "3:     mov     %0, #1\n"                       \
203         "       b       2b\n"                           \
204         "       .popsection\n"                          \
205         "       .pushsection __ex_table,\"a\"\n"        \
206         "       .align  3\n"                            \
207         "       .long   1b, 3b\n"                       \
208         "       .popsection\n"                          \
209         : "=r" (err), "=&r" (val), "=r" (addr)          \
210         : "" (err), "2" (addr))
211 
212 #define __get16_unaligned_check(ins,val,addr)                   \
213         do {                                                    \
214                 unsigned int err = 0, v, a = addr;              \
215                 __get8_unaligned_check(ins,v,a,err);            \
216                 val =  v << ((BE) ? 8 : 0);                     \
217                 __get8_unaligned_check(ins,v,a,err);            \
218                 val |= v << ((BE) ? 0 : 8);                     \
219                 if (err)                                        \
220                         goto fault;                             \
221         } while (0)
222 
223 #define get16_unaligned_check(val,addr) \
224         __get16_unaligned_check("ldrb",val,addr)
225 
226 #define get16t_unaligned_check(val,addr) \
227         __get16_unaligned_check("ldrbt",val,addr)
228 
229 #define __get32_unaligned_check(ins,val,addr)                   \
230         do {                                                    \
231                 unsigned int err = 0, v, a = addr;              \
232                 __get8_unaligned_check(ins,v,a,err);            \
233                 val =  v << ((BE) ? 24 :  0);                   \
234                 __get8_unaligned_check(ins,v,a,err);            \
235                 val |= v << ((BE) ? 16 :  8);                   \
236                 __get8_unaligned_check(ins,v,a,err);            \
237                 val |= v << ((BE) ?  8 : 16);                   \
238                 __get8_unaligned_check(ins,v,a,err);            \
239                 val |= v << ((BE) ?  0 : 24);                   \
240                 if (err)                                        \
241                         goto fault;                             \
242         } while (0)
243 
244 #define get32_unaligned_check(val,addr) \
245         __get32_unaligned_check("ldrb",val,addr)
246 
247 #define get32t_unaligned_check(val,addr) \
248         __get32_unaligned_check("ldrbt",val,addr)
249 
250 #define __put16_unaligned_check(ins,val,addr)                   \
251         do {                                                    \
252                 unsigned int err = 0, v = val, a = addr;        \
253                 __asm__( FIRST_BYTE_16                          \
254          ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
255          THUMB( "1:     "ins"   %1, [%2]\n"     )               \
256          THUMB( "       add     %2, %2, #1\n"   )               \
257                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
258                 "2:     "ins"   %1, [%2]\n"                     \
259                 "3:\n"                                          \
260                 "       .pushsection .fixup,\"ax\"\n"           \
261                 "       .align  2\n"                            \
262                 "4:     mov     %0, #1\n"                       \
263                 "       b       3b\n"                           \
264                 "       .popsection\n"                          \
265                 "       .pushsection __ex_table,\"a\"\n"        \
266                 "       .align  3\n"                            \
267                 "       .long   1b, 4b\n"                       \
268                 "       .long   2b, 4b\n"                       \
269                 "       .popsection\n"                          \
270                 : "=r" (err), "=&r" (v), "=&r" (a)              \
271                 : "" (err), "1" (v), "2" (a));                 \
272                 if (err)                                        \
273                         goto fault;                             \
274         } while (0)
275 
276 #define put16_unaligned_check(val,addr)  \
277         __put16_unaligned_check("strb",val,addr)
278 
279 #define put16t_unaligned_check(val,addr) \
280         __put16_unaligned_check("strbt",val,addr)
281 
282 #define __put32_unaligned_check(ins,val,addr)                   \
283         do {                                                    \
284                 unsigned int err = 0, v = val, a = addr;        \
285                 __asm__( FIRST_BYTE_32                          \
286          ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
287          THUMB( "1:     "ins"   %1, [%2]\n"     )               \
288          THUMB( "       add     %2, %2, #1\n"   )               \
289                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
290          ARM(   "2:     "ins"   %1, [%2], #1\n" )               \
291          THUMB( "2:     "ins"   %1, [%2]\n"     )               \
292          THUMB( "       add     %2, %2, #1\n"   )               \
293                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
294          ARM(   "3:     "ins"   %1, [%2], #1\n" )               \
295          THUMB( "3:     "ins"   %1, [%2]\n"     )               \
296          THUMB( "       add     %2, %2, #1\n"   )               \
297                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
298                 "4:     "ins"   %1, [%2]\n"                     \
299                 "5:\n"                                          \
300                 "       .pushsection .fixup,\"ax\"\n"           \
301                 "       .align  2\n"                            \
302                 "6:     mov     %0, #1\n"                       \
303                 "       b       5b\n"                           \
304                 "       .popsection\n"                          \
305                 "       .pushsection __ex_table,\"a\"\n"        \
306                 "       .align  3\n"                            \
307                 "       .long   1b, 6b\n"                       \
308                 "       .long   2b, 6b\n"                       \
309                 "       .long   3b, 6b\n"                       \
310                 "       .long   4b, 6b\n"                       \
311                 "       .popsection\n"                          \
312                 : "=r" (err), "=&r" (v), "=&r" (a)              \
313                 : "" (err), "1" (v), "2" (a));                 \
314                 if (err)                                        \
315                         goto fault;                             \
316         } while (0)
317 
318 #define put32_unaligned_check(val,addr) \
319         __put32_unaligned_check("strb", val, addr)
320 
321 #define put32t_unaligned_check(val,addr) \
322         __put32_unaligned_check("strbt", val, addr)
323 
324 static void
325 do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
326 {
327         if (!LDST_U_BIT(instr))
328                 offset.un = -offset.un;
329 
330         if (!LDST_P_BIT(instr))
331                 addr += offset.un;
332 
333         if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
334                 regs->uregs[RN_BITS(instr)] = addr;
335 }
336 
337 static int
338 do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
339 {
340         unsigned int rd = RD_BITS(instr);
341 
342         ai_half += 1;
343 
344         if (user_mode(regs))
345                 goto user;
346 
347         if (LDST_L_BIT(instr)) {
348                 unsigned long val;
349                 get16_unaligned_check(val, addr);
350 
351                 /* signed half-word? */
352                 if (instr & 0x40)
353                         val = (signed long)((signed short) val);
354 
355                 regs->uregs[rd] = val;
356         } else
357                 put16_unaligned_check(regs->uregs[rd], addr);
358 
359         return TYPE_LDST;
360 
361  user:
362         if (LDST_L_BIT(instr)) {
363                 unsigned long val;
364                 get16t_unaligned_check(val, addr);
365 
366                 /* signed half-word? */
367                 if (instr & 0x40)
368                         val = (signed long)((signed short) val);
369 
370                 regs->uregs[rd] = val;
371         } else
372                 put16t_unaligned_check(regs->uregs[rd], addr);
373 
374         return TYPE_LDST;
375 
376  fault:
377         return TYPE_FAULT;
378 }
379 
380 static int
381 do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
382                       struct pt_regs *regs)
383 {
384         unsigned int rd = RD_BITS(instr);
385         unsigned int rd2;
386         int load;
387 
388         if ((instr & 0xfe000000) == 0xe8000000) {
389                 /* ARMv7 Thumb-2 32-bit LDRD/STRD */
390                 rd2 = (instr >> 8) & 0xf;
391                 load = !!(LDST_L_BIT(instr));
392         } else if (((rd & 1) == 1) || (rd == 14))
393                 goto bad;
394         else {
395                 load = ((instr & 0xf0) == 0xd0);
396                 rd2 = rd + 1;
397         }
398 
399         ai_dword += 1;
400 
401         if (user_mode(regs))
402                 goto user;
403 
404         if (load) {
405                 unsigned long val;
406                 get32_unaligned_check(val, addr);
407                 regs->uregs[rd] = val;
408                 get32_unaligned_check(val, addr + 4);
409                 regs->uregs[rd2] = val;
410         } else {
411                 put32_unaligned_check(regs->uregs[rd], addr);
412                 put32_unaligned_check(regs->uregs[rd2], addr + 4);
413         }
414 
415         return TYPE_LDST;
416 
417  user:
418         if (load) {
419                 unsigned long val;
420                 get32t_unaligned_check(val, addr);
421                 regs->uregs[rd] = val;
422                 get32t_unaligned_check(val, addr + 4);
423                 regs->uregs[rd2] = val;
424         } else {
425                 put32t_unaligned_check(regs->uregs[rd], addr);
426                 put32t_unaligned_check(regs->uregs[rd2], addr + 4);
427         }
428 
429         return TYPE_LDST;
430  bad:
431         return TYPE_ERROR;
432  fault:
433         return TYPE_FAULT;
434 }
435 
436 static int
437 do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
438 {
439         unsigned int rd = RD_BITS(instr);
440 
441         ai_word += 1;
442 
443         if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
444                 goto trans;
445 
446         if (LDST_L_BIT(instr)) {
447                 unsigned int val;
448                 get32_unaligned_check(val, addr);
449                 regs->uregs[rd] = val;
450         } else
451                 put32_unaligned_check(regs->uregs[rd], addr);
452         return TYPE_LDST;
453 
454  trans:
455         if (LDST_L_BIT(instr)) {
456                 unsigned int val;
457                 get32t_unaligned_check(val, addr);
458                 regs->uregs[rd] = val;
459         } else
460                 put32t_unaligned_check(regs->uregs[rd], addr);
461         return TYPE_LDST;
462 
463  fault:
464         return TYPE_FAULT;
465 }
466 
467 /*
468  * LDM/STM alignment handler.
469  *
470  * There are 4 variants of this instruction:
471  *
472  * B = rn pointer before instruction, A = rn pointer after instruction
473  *              ------ increasing address ----->
474  *              |    | r0 | r1 | ... | rx |    |
475  * PU = 01             B                    A
476  * PU = 11        B                    A
477  * PU = 00        A                    B
478  * PU = 10             A                    B
479  */
480 static int
481 do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
482 {
483         unsigned int rd, rn, correction, nr_regs, regbits;
484         unsigned long eaddr, newaddr;
485 
486         if (LDM_S_BIT(instr))
487                 goto bad;
488 
489         correction = 4; /* processor implementation defined */
490         regs->ARM_pc += correction;
491 
492         ai_multi += 1;
493 
494         /* count the number of registers in the mask to be transferred */
495         nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
496 
497         rn = RN_BITS(instr);
498         newaddr = eaddr = regs->uregs[rn];
499 
500         if (!LDST_U_BIT(instr))
501                 nr_regs = -nr_regs;
502         newaddr += nr_regs;
503         if (!LDST_U_BIT(instr))
504                 eaddr = newaddr;
505 
506         if (LDST_P_EQ_U(instr)) /* U = P */
507                 eaddr += 4;
508 
509         /*
510          * For alignment faults on the ARM922T/ARM920T the MMU  makes
511          * the FSR (and hence addr) equal to the updated base address
512          * of the multiple access rather than the restored value.
513          * Switch this message off if we've got a ARM92[02], otherwise
514          * [ls]dm alignment faults are noisy!
515          */
516 #if !(defined CONFIG_CPU_ARM922T)  && !(defined CONFIG_CPU_ARM920T)
517         /*
518          * This is a "hint" - we already have eaddr worked out by the
519          * processor for us.
520          */
521         if (addr != eaddr) {
522                 printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
523                         "addr = %08lx, eaddr = %08lx\n",
524                          instruction_pointer(regs), instr, addr, eaddr);
525                 show_regs(regs);
526         }
527 #endif
528 
529         if (user_mode(regs)) {
530                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
531                      regbits >>= 1, rd += 1)
532                         if (regbits & 1) {
533                                 if (LDST_L_BIT(instr)) {
534                                         unsigned int val;
535                                         get32t_unaligned_check(val, eaddr);
536                                         regs->uregs[rd] = val;
537                                 } else
538                                         put32t_unaligned_check(regs->uregs[rd], eaddr);
539                                 eaddr += 4;
540                         }
541         } else {
542                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
543                      regbits >>= 1, rd += 1)
544                         if (regbits & 1) {
545                                 if (LDST_L_BIT(instr)) {
546                                         unsigned int val;
547                                         get32_unaligned_check(val, eaddr);
548                                         regs->uregs[rd] = val;
549                                 } else
550                                         put32_unaligned_check(regs->uregs[rd], eaddr);
551                                 eaddr += 4;
552                         }
553         }
554 
555         if (LDST_W_BIT(instr))
556                 regs->uregs[rn] = newaddr;
557         if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
558                 regs->ARM_pc -= correction;
559         return TYPE_DONE;
560 
561 fault:
562         regs->ARM_pc -= correction;
563         return TYPE_FAULT;
564 
565 bad:
566         printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
567         return TYPE_ERROR;
568 }
569 
570 /*
571  * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
572  * we can reuse ARM userland alignment fault fixups for Thumb.
573  *
574  * This implementation was initially based on the algorithm found in
575  * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
576  * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
577  *
578  * NOTES:
579  * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
580  * 2. If for some reason we're passed an non-ld/st Thumb instruction to
581  *    decode, we return 0xdeadc0de. This should never happen under normal
582  *    circumstances but if it does, we've got other problems to deal with
583  *    elsewhere and we obviously can't fix those problems here.
584  */
585 
586 static unsigned long
587 thumb2arm(u16 tinstr)
588 {
589         u32 L = (tinstr & (1<<11)) >> 11;
590 
591         switch ((tinstr & 0xf800) >> 11) {
592         /* 6.5.1 Format 1: */
593         case 0x6000 >> 11:                              /* 7.1.52 STR(1) */
594         case 0x6800 >> 11:                              /* 7.1.26 LDR(1) */
595         case 0x7000 >> 11:                              /* 7.1.55 STRB(1) */
596         case 0x7800 >> 11:                              /* 7.1.30 LDRB(1) */
597                 return 0xe5800000 |
598                         ((tinstr & (1<<12)) << (22-12)) |       /* fixup */
599                         (L<<20) |                               /* L==1? */
600                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
601                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
602                         ((tinstr & (31<<6)) >>                  /* immed_5 */
603                                 (6 - ((tinstr & (1<<12)) ? 0 : 2)));
604         case 0x8000 >> 11:                              /* 7.1.57 STRH(1) */
605         case 0x8800 >> 11:                              /* 7.1.32 LDRH(1) */
606                 return 0xe1c000b0 |
607                         (L<<20) |                               /* L==1? */
608                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
609                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
610                         ((tinstr & (7<<6)) >> (6-1)) |   /* immed_5[2:0] */
611                         ((tinstr & (3<<9)) >> (9-8));    /* immed_5[4:3] */
612 
613         /* 6.5.1 Format 2: */
614         case 0x5000 >> 11:
615         case 0x5800 >> 11:
616                 {
617                         static const u32 subset[8] = {
618                                 0xe7800000,             /* 7.1.53 STR(2) */
619                                 0xe18000b0,             /* 7.1.58 STRH(2) */
620                                 0xe7c00000,             /* 7.1.56 STRB(2) */
621                                 0xe19000d0,             /* 7.1.34 LDRSB */
622                                 0xe7900000,             /* 7.1.27 LDR(2) */
623                                 0xe19000b0,             /* 7.1.33 LDRH(2) */
624                                 0xe7d00000,             /* 7.1.31 LDRB(2) */
625                                 0xe19000f0              /* 7.1.35 LDRSH */
626                         };
627                         return subset[(tinstr & (7<<9)) >> 9] |
628                             ((tinstr & (7<<0)) << (12-0)) |     /* Rd */
629                             ((tinstr & (7<<3)) << (16-3)) |     /* Rn */
630                             ((tinstr & (7<<6)) >> (6-0));       /* Rm */
631                 }
632 
633         /* 6.5.1 Format 3: */
634         case 0x4800 >> 11:                              /* 7.1.28 LDR(3) */
635                 /* NOTE: This case is not technically possible. We're
636                  *       loading 32-bit memory data via PC relative
637                  *       addressing mode. So we can and should eliminate
638                  *       this case. But I'll leave it here for now.
639                  */
640                 return 0xe59f0000 |
641                     ((tinstr & (7<<8)) << (12-8)) |             /* Rd */
642                     ((tinstr & 255) << (2-0));                  /* immed_8 */
643 
644         /* 6.5.1 Format 4: */
645         case 0x9000 >> 11:                              /* 7.1.54 STR(3) */
646         case 0x9800 >> 11:                              /* 7.1.29 LDR(4) */
647                 return 0xe58d0000 |
648                         (L<<20) |                               /* L==1? */
649                         ((tinstr & (7<<8)) << (12-8)) |         /* Rd */
650                         ((tinstr & 255) << 2);                  /* immed_8 */
651 
652         /* 6.6.1 Format 1: */
653         case 0xc000 >> 11:                              /* 7.1.51 STMIA */
654         case 0xc800 >> 11:                              /* 7.1.25 LDMIA */
655                 {
656                         u32 Rn = (tinstr & (7<<8)) >> 8;
657                         u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
658 
659                         return 0xe8800000 | W | (L<<20) | (Rn<<16) |
660                                 (tinstr&255);
661                 }
662 
663         /* 6.6.1 Format 2: */
664         case 0xb000 >> 11:                              /* 7.1.48 PUSH */
665         case 0xb800 >> 11:                              /* 7.1.47 POP */
666                 if ((tinstr & (3 << 9)) == 0x0400) {
667                         static const u32 subset[4] = {
668                                 0xe92d0000,     /* STMDB sp!,{registers} */
669                                 0xe92d4000,     /* STMDB sp!,{registers,lr} */
670                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
671                                 0xe8bd8000      /* LDMIA sp!,{registers,pc} */
672                         };
673                         return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
674                             (tinstr & 255);             /* register_list */
675                 }
676                 /* Else fall through for illegal instruction case */
677 
678         default:
679                 return BAD_INSTR;
680         }
681 }
682 
683 /*
684  * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
685  * handlable by ARM alignment handler, also find the corresponding handler,
686  * so that we can reuse ARM userland alignment fault fixups for Thumb.
687  *
688  * @pinstr: original Thumb-2 instruction; returns new handlable instruction
689  * @regs: register context.
690  * @poffset: return offset from faulted addr for later writeback
691  *
692  * NOTES:
693  * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
694  * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
695  */
696 static void *
697 do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
698                             union offset_union *poffset)
699 {
700         unsigned long instr = *pinstr;
701         u16 tinst1 = (instr >> 16) & 0xffff;
702         u16 tinst2 = instr & 0xffff;
703 
704         switch (tinst1 & 0xffe0) {
705         /* A6.3.5 Load/Store multiple */
706         case 0xe880:            /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
707         case 0xe8a0:            /* ...above writeback version */
708         case 0xe900:            /* STMDB/STMFD, LDMDB/LDMEA */
709         case 0xe920:            /* ...above writeback version */
710                 /* no need offset decision since handler calculates it */
711                 return do_alignment_ldmstm;
712 
713         case 0xf840:            /* POP/PUSH T3 (single register) */
714                 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
715                         u32 L = !!(LDST_L_BIT(instr));
716                         const u32 subset[2] = {
717                                 0xe92d0000,     /* STMDB sp!,{registers} */
718                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
719                         };
720                         *pinstr = subset[L] | (1<<RD_BITS(instr));
721                         return do_alignment_ldmstm;
722                 }
723                 /* Else fall through for illegal instruction case */
724                 break;
725 
726         /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
727         case 0xe860:
728         case 0xe960:
729         case 0xe8e0:
730         case 0xe9e0:
731                 poffset->un = (tinst2 & 0xff) << 2;
732         case 0xe940:
733         case 0xe9c0:
734                 return do_alignment_ldrdstrd;
735 
736         /*
737          * No need to handle load/store instructions up to word size
738          * since ARMv6 and later CPUs can perform unaligned accesses.
739          */
740         default:
741                 break;
742         }
743         return NULL;
744 }
745 
746 static int
747 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
748 {
749         union offset_union uninitialized_var(offset);
750         unsigned long instr = 0, instrptr;
751         int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
752         unsigned int type;
753         unsigned int fault;
754         u16 tinstr = 0;
755         int isize = 4;
756         int thumb2_32b = 0;
757 
758         if (interrupts_enabled(regs))
759                 local_irq_enable();
760 
761         instrptr = instruction_pointer(regs);
762 
763         if (thumb_mode(regs)) {
764                 u16 *ptr = (u16 *)(instrptr & ~1);
765                 fault = probe_kernel_address(ptr, tinstr);
766                 if (!fault) {
767                         if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
768                             IS_T32(tinstr)) {
769                                 /* Thumb-2 32-bit */
770                                 u16 tinst2 = 0;
771                                 fault = probe_kernel_address(ptr + 1, tinst2);
772                                 instr = (tinstr << 16) | tinst2;
773                                 thumb2_32b = 1;
774                         } else {
775                                 isize = 2;
776                                 instr = thumb2arm(tinstr);
777                         }
778                 }
779         } else
780                 fault = probe_kernel_address(instrptr, instr);
781 
782         if (fault) {
783                 type = TYPE_FAULT;
784                 goto bad_or_fault;
785         }
786 
787         if (user_mode(regs))
788                 goto user;
789 
790         ai_sys += 1;
791 
792  fixup:
793 
794         regs->ARM_pc += isize;
795 
796         switch (CODING_BITS(instr)) {
797         case 0x00000000:        /* 3.13.4 load/store instruction extensions */
798                 if (LDSTHD_I_BIT(instr))
799                         offset.un = (instr & 0xf00) >> 4 | (instr & 15);
800                 else
801                         offset.un = regs->uregs[RM_BITS(instr)];
802 
803                 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
804                     (instr & 0x001000f0) == 0x001000f0)   /* LDRSH */
805                         handler = do_alignment_ldrhstrh;
806                 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
807                          (instr & 0x001000f0) == 0x000000f0)   /* STRD */
808                         handler = do_alignment_ldrdstrd;
809                 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
810                         goto swp;
811                 else
812                         goto bad;
813                 break;
814 
815         case 0x04000000:        /* ldr or str immediate */
816                 if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */
817                         goto bad;
818                 offset.un = OFFSET_BITS(instr);
819                 handler = do_alignment_ldrstr;
820                 break;
821 
822         case 0x06000000:        /* ldr or str register */
823                 offset.un = regs->uregs[RM_BITS(instr)];
824 
825                 if (IS_SHIFT(instr)) {
826                         unsigned int shiftval = SHIFT_BITS(instr);
827 
828                         switch(SHIFT_TYPE(instr)) {
829                         case SHIFT_LSL:
830                                 offset.un <<= shiftval;
831                                 break;
832 
833                         case SHIFT_LSR:
834                                 offset.un >>= shiftval;
835                                 break;
836 
837                         case SHIFT_ASR:
838                                 offset.sn >>= shiftval;
839                                 break;
840 
841                         case SHIFT_RORRRX:
842                                 if (shiftval == 0) {
843                                         offset.un >>= 1;
844                                         if (regs->ARM_cpsr & PSR_C_BIT)
845                                                 offset.un |= 1 << 31;
846                                 } else
847                                         offset.un = offset.un >> shiftval |
848                                                           offset.un << (32 - shiftval);
849                                 break;
850                         }
851                 }
852                 handler = do_alignment_ldrstr;
853                 break;
854 
855         case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
856                 if (thumb2_32b) {
857                         offset.un = 0;
858                         handler = do_alignment_t32_to_handler(&instr, regs, &offset);
859                 } else {
860                         offset.un = 0;
861                         handler = do_alignment_ldmstm;
862                 }
863                 break;
864 
865         default:
866                 goto bad;
867         }
868 
869         if (!handler)
870                 goto bad;
871         type = handler(addr, instr, regs);
872 
873         if (type == TYPE_ERROR || type == TYPE_FAULT) {
874                 regs->ARM_pc -= isize;
875                 goto bad_or_fault;
876         }
877 
878         if (type == TYPE_LDST)
879                 do_alignment_finish_ldst(addr, instr, regs, offset);
880 
881         return 0;
882 
883  bad_or_fault:
884         if (type == TYPE_ERROR)
885                 goto bad;
886         /*
887          * We got a fault - fix it up, or die.
888          */
889         do_bad_area(addr, fsr, regs);
890         return 0;
891 
892  swp:
893         printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
894 
895  bad:
896         /*
897          * Oops, we didn't handle the instruction.
898          */
899         printk(KERN_ERR "Alignment trap: not handling instruction "
900                 "%0*lx at [<%08lx>]\n",
901                 isize << 1,
902                 isize == 2 ? tinstr : instr, instrptr);
903         ai_skipped += 1;
904         return 1;
905 
906  user:
907         ai_user += 1;
908 
909         if (ai_usermode & UM_WARN)
910                 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
911                        "Address=0x%08lx FSR 0x%03x\n", current->comm,
912                         task_pid_nr(current), instrptr,
913                         isize << 1,
914                         isize == 2 ? tinstr : instr,
915                         addr, fsr);
916 
917         if (ai_usermode & UM_FIXUP)
918                 goto fixup;
919 
920         if (ai_usermode & UM_SIGNAL) {
921                 siginfo_t si;
922 
923                 si.si_signo = SIGBUS;
924                 si.si_errno = 0;
925                 si.si_code = BUS_ADRALN;
926                 si.si_addr = (void __user *)addr;
927 
928                 force_sig_info(si.si_signo, &si, current);
929         } else {
930                 /*
931                  * We're about to disable the alignment trap and return to
932                  * user space.  But if an interrupt occurs before actually
933                  * reaching user space, then the IRQ vector entry code will
934                  * notice that we were still in kernel space and therefore
935                  * the alignment trap won't be re-enabled in that case as it
936                  * is presumed to be always on from kernel space.
937                  * Let's prevent that race by disabling interrupts here (they
938                  * are disabled on the way back to user space anyway in
939                  * entry-common.S) and disable the alignment trap only if
940                  * there is no work pending for this thread.
941                  */
942                 raw_local_irq_disable();
943                 if (!(current_thread_info()->flags & _TIF_WORK_MASK))
944                         set_cr(cr_no_alignment);
945         }
946 
947         return 0;
948 }
949 
950 /*
951  * This needs to be done after sysctl_init, otherwise sys/ will be
952  * overwritten.  Actually, this shouldn't be in sys/ at all since
953  * it isn't a sysctl, and it doesn't contain sysctl information.
954  * We now locate it in /proc/cpu/alignment instead.
955  */
956 static int __init alignment_init(void)
957 {
958 #ifdef CONFIG_PROC_FS
959         struct proc_dir_entry *res;
960 
961         res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL,
962                           &alignment_proc_fops);
963         if (!res)
964                 return -ENOMEM;
965 #endif
966 
967 #ifdef CONFIG_CPU_CP15
968         if (cpu_is_v6_unaligned()) {
969                 cr_alignment &= ~CR_A;
970                 cr_no_alignment &= ~CR_A;
971                 set_cr(cr_alignment);
972                 ai_usermode = safe_usermode(ai_usermode, false);
973         }
974 #endif
975 
976         hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
977                         "alignment exception");
978 
979         /*
980          * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
981          * fault, not as alignment error.
982          *
983          * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
984          * needed.
985          */
986         if (cpu_architecture() <= CPU_ARCH_ARMv6) {
987                 hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
988                                 "alignment exception");
989         }
990 
991         return 0;
992 }
993 
994 fs_initcall(alignment_init);
995 

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