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TOMOYO Linux Cross Reference
Linux/arch/arm/mm/alignment.c

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  1 /*
  2  *  linux/arch/arm/mm/alignment.c
  3  *
  4  *  Copyright (C) 1995  Linus Torvalds
  5  *  Modifications for ARM processor (c) 1995-2001 Russell King
  6  *  Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
  7  *  - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
  8  *    Copyright (C) 1996, Cygnus Software Technologies Ltd.
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License version 2 as
 12  * published by the Free Software Foundation.
 13  */
 14 #include <linux/moduleparam.h>
 15 #include <linux/compiler.h>
 16 #include <linux/kernel.h>
 17 #include <linux/errno.h>
 18 #include <linux/string.h>
 19 #include <linux/proc_fs.h>
 20 #include <linux/seq_file.h>
 21 #include <linux/init.h>
 22 #include <linux/sched.h>
 23 #include <linux/uaccess.h>
 24 
 25 #include <asm/cp15.h>
 26 #include <asm/system_info.h>
 27 #include <asm/unaligned.h>
 28 #include <asm/opcodes.h>
 29 
 30 #include "fault.h"
 31 #include "mm.h"
 32 
 33 /*
 34  * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
 35  * /proc/sys/debug/alignment, modified and integrated into
 36  * Linux 2.1 by Russell King
 37  *
 38  * Speed optimisations and better fault handling by Russell King.
 39  *
 40  * *** NOTE ***
 41  * This code is not portable to processors with late data abort handling.
 42  */
 43 #define CODING_BITS(i)  (i & 0x0e000000)
 44 #define COND_BITS(i)    (i & 0xf0000000)
 45 
 46 #define LDST_I_BIT(i)   (i & (1 << 26))         /* Immediate constant   */
 47 #define LDST_P_BIT(i)   (i & (1 << 24))         /* Preindex             */
 48 #define LDST_U_BIT(i)   (i & (1 << 23))         /* Add offset           */
 49 #define LDST_W_BIT(i)   (i & (1 << 21))         /* Writeback            */
 50 #define LDST_L_BIT(i)   (i & (1 << 20))         /* Load                 */
 51 
 52 #define LDST_P_EQ_U(i)  ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
 53 
 54 #define LDSTHD_I_BIT(i) (i & (1 << 22))         /* double/half-word immed */
 55 #define LDM_S_BIT(i)    (i & (1 << 22))         /* write CPSR from SPSR */
 56 
 57 #define RN_BITS(i)      ((i >> 16) & 15)        /* Rn                   */
 58 #define RD_BITS(i)      ((i >> 12) & 15)        /* Rd                   */
 59 #define RM_BITS(i)      (i & 15)                /* Rm                   */
 60 
 61 #define REGMASK_BITS(i) (i & 0xffff)
 62 #define OFFSET_BITS(i)  (i & 0x0fff)
 63 
 64 #define IS_SHIFT(i)     (i & 0x0ff0)
 65 #define SHIFT_BITS(i)   ((i >> 7) & 0x1f)
 66 #define SHIFT_TYPE(i)   (i & 0x60)
 67 #define SHIFT_LSL       0x00
 68 #define SHIFT_LSR       0x20
 69 #define SHIFT_ASR       0x40
 70 #define SHIFT_RORRRX    0x60
 71 
 72 #define BAD_INSTR       0xdeadc0de
 73 
 74 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
 75 #define IS_T32(hi16) \
 76         (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
 77 
 78 static unsigned long ai_user;
 79 static unsigned long ai_sys;
 80 static void *ai_sys_last_pc;
 81 static unsigned long ai_skipped;
 82 static unsigned long ai_half;
 83 static unsigned long ai_word;
 84 static unsigned long ai_dword;
 85 static unsigned long ai_multi;
 86 static int ai_usermode;
 87 static unsigned long cr_no_alignment;
 88 
 89 core_param(alignment, ai_usermode, int, 0600);
 90 
 91 #define UM_WARN         (1 << 0)
 92 #define UM_FIXUP        (1 << 1)
 93 #define UM_SIGNAL       (1 << 2)
 94 
 95 /* Return true if and only if the ARMv6 unaligned access model is in use. */
 96 static bool cpu_is_v6_unaligned(void)
 97 {
 98         return cpu_architecture() >= CPU_ARCH_ARMv6 && get_cr() & CR_U;
 99 }
100 
101 static int safe_usermode(int new_usermode, bool warn)
102 {
103         /*
104          * ARMv6 and later CPUs can perform unaligned accesses for
105          * most single load and store instructions up to word size.
106          * LDM, STM, LDRD and STRD still need to be handled.
107          *
108          * Ignoring the alignment fault is not an option on these
109          * CPUs since we spin re-faulting the instruction without
110          * making any progress.
111          */
112         if (cpu_is_v6_unaligned() && !(new_usermode & (UM_FIXUP | UM_SIGNAL))) {
113                 new_usermode |= UM_FIXUP;
114 
115                 if (warn)
116                         pr_warn("alignment: ignoring faults is unsafe on this CPU.  Defaulting to fixup mode.\n");
117         }
118 
119         return new_usermode;
120 }
121 
122 #ifdef CONFIG_PROC_FS
123 static const char *usermode_action[] = {
124         "ignored",
125         "warn",
126         "fixup",
127         "fixup+warn",
128         "signal",
129         "signal+warn"
130 };
131 
132 static int alignment_proc_show(struct seq_file *m, void *v)
133 {
134         seq_printf(m, "User:\t\t%lu\n", ai_user);
135         seq_printf(m, "System:\t\t%lu (%pF)\n", ai_sys, ai_sys_last_pc);
136         seq_printf(m, "Skipped:\t%lu\n", ai_skipped);
137         seq_printf(m, "Half:\t\t%lu\n", ai_half);
138         seq_printf(m, "Word:\t\t%lu\n", ai_word);
139         if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
140                 seq_printf(m, "DWord:\t\t%lu\n", ai_dword);
141         seq_printf(m, "Multi:\t\t%lu\n", ai_multi);
142         seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode,
143                         usermode_action[ai_usermode]);
144 
145         return 0;
146 }
147 
148 static int alignment_proc_open(struct inode *inode, struct file *file)
149 {
150         return single_open(file, alignment_proc_show, NULL);
151 }
152 
153 static ssize_t alignment_proc_write(struct file *file, const char __user *buffer,
154                                     size_t count, loff_t *pos)
155 {
156         char mode;
157 
158         if (count > 0) {
159                 if (get_user(mode, buffer))
160                         return -EFAULT;
161                 if (mode >= '' && mode <= '5')
162                         ai_usermode = safe_usermode(mode - '', true);
163         }
164         return count;
165 }
166 
167 static const struct file_operations alignment_proc_fops = {
168         .open           = alignment_proc_open,
169         .read           = seq_read,
170         .llseek         = seq_lseek,
171         .release        = single_release,
172         .write          = alignment_proc_write,
173 };
174 #endif /* CONFIG_PROC_FS */
175 
176 union offset_union {
177         unsigned long un;
178           signed long sn;
179 };
180 
181 #define TYPE_ERROR      0
182 #define TYPE_FAULT      1
183 #define TYPE_LDST       2
184 #define TYPE_DONE       3
185 
186 #ifdef __ARMEB__
187 #define BE              1
188 #define FIRST_BYTE_16   "mov    %1, %1, ror #8\n"
189 #define FIRST_BYTE_32   "mov    %1, %1, ror #24\n"
190 #define NEXT_BYTE       "ror #24"
191 #else
192 #define BE              0
193 #define FIRST_BYTE_16
194 #define FIRST_BYTE_32
195 #define NEXT_BYTE       "lsr #8"
196 #endif
197 
198 #define __get8_unaligned_check(ins,val,addr,err)        \
199         __asm__(                                        \
200  ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
201  THUMB( "1:     "ins"   %1, [%2]\n"     )               \
202  THUMB( "       add     %2, %2, #1\n"   )               \
203         "2:\n"                                          \
204         "       .pushsection .text.fixup,\"ax\"\n"      \
205         "       .align  2\n"                            \
206         "3:     mov     %0, #1\n"                       \
207         "       b       2b\n"                           \
208         "       .popsection\n"                          \
209         "       .pushsection __ex_table,\"a\"\n"        \
210         "       .align  3\n"                            \
211         "       .long   1b, 3b\n"                       \
212         "       .popsection\n"                          \
213         : "=r" (err), "=&r" (val), "=r" (addr)          \
214         : "" (err), "2" (addr))
215 
216 #define __get16_unaligned_check(ins,val,addr)                   \
217         do {                                                    \
218                 unsigned int err = 0, v, a = addr;              \
219                 __get8_unaligned_check(ins,v,a,err);            \
220                 val =  v << ((BE) ? 8 : 0);                     \
221                 __get8_unaligned_check(ins,v,a,err);            \
222                 val |= v << ((BE) ? 0 : 8);                     \
223                 if (err)                                        \
224                         goto fault;                             \
225         } while (0)
226 
227 #define get16_unaligned_check(val,addr) \
228         __get16_unaligned_check("ldrb",val,addr)
229 
230 #define get16t_unaligned_check(val,addr) \
231         __get16_unaligned_check("ldrbt",val,addr)
232 
233 #define __get32_unaligned_check(ins,val,addr)                   \
234         do {                                                    \
235                 unsigned int err = 0, v, a = addr;              \
236                 __get8_unaligned_check(ins,v,a,err);            \
237                 val =  v << ((BE) ? 24 :  0);                   \
238                 __get8_unaligned_check(ins,v,a,err);            \
239                 val |= v << ((BE) ? 16 :  8);                   \
240                 __get8_unaligned_check(ins,v,a,err);            \
241                 val |= v << ((BE) ?  8 : 16);                   \
242                 __get8_unaligned_check(ins,v,a,err);            \
243                 val |= v << ((BE) ?  0 : 24);                   \
244                 if (err)                                        \
245                         goto fault;                             \
246         } while (0)
247 
248 #define get32_unaligned_check(val,addr) \
249         __get32_unaligned_check("ldrb",val,addr)
250 
251 #define get32t_unaligned_check(val,addr) \
252         __get32_unaligned_check("ldrbt",val,addr)
253 
254 #define __put16_unaligned_check(ins,val,addr)                   \
255         do {                                                    \
256                 unsigned int err = 0, v = val, a = addr;        \
257                 __asm__( FIRST_BYTE_16                          \
258          ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
259          THUMB( "1:     "ins"   %1, [%2]\n"     )               \
260          THUMB( "       add     %2, %2, #1\n"   )               \
261                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
262                 "2:     "ins"   %1, [%2]\n"                     \
263                 "3:\n"                                          \
264                 "       .pushsection .text.fixup,\"ax\"\n"      \
265                 "       .align  2\n"                            \
266                 "4:     mov     %0, #1\n"                       \
267                 "       b       3b\n"                           \
268                 "       .popsection\n"                          \
269                 "       .pushsection __ex_table,\"a\"\n"        \
270                 "       .align  3\n"                            \
271                 "       .long   1b, 4b\n"                       \
272                 "       .long   2b, 4b\n"                       \
273                 "       .popsection\n"                          \
274                 : "=r" (err), "=&r" (v), "=&r" (a)              \
275                 : "" (err), "1" (v), "2" (a));                 \
276                 if (err)                                        \
277                         goto fault;                             \
278         } while (0)
279 
280 #define put16_unaligned_check(val,addr)  \
281         __put16_unaligned_check("strb",val,addr)
282 
283 #define put16t_unaligned_check(val,addr) \
284         __put16_unaligned_check("strbt",val,addr)
285 
286 #define __put32_unaligned_check(ins,val,addr)                   \
287         do {                                                    \
288                 unsigned int err = 0, v = val, a = addr;        \
289                 __asm__( FIRST_BYTE_32                          \
290          ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
291          THUMB( "1:     "ins"   %1, [%2]\n"     )               \
292          THUMB( "       add     %2, %2, #1\n"   )               \
293                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
294          ARM(   "2:     "ins"   %1, [%2], #1\n" )               \
295          THUMB( "2:     "ins"   %1, [%2]\n"     )               \
296          THUMB( "       add     %2, %2, #1\n"   )               \
297                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
298          ARM(   "3:     "ins"   %1, [%2], #1\n" )               \
299          THUMB( "3:     "ins"   %1, [%2]\n"     )               \
300          THUMB( "       add     %2, %2, #1\n"   )               \
301                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
302                 "4:     "ins"   %1, [%2]\n"                     \
303                 "5:\n"                                          \
304                 "       .pushsection .text.fixup,\"ax\"\n"      \
305                 "       .align  2\n"                            \
306                 "6:     mov     %0, #1\n"                       \
307                 "       b       5b\n"                           \
308                 "       .popsection\n"                          \
309                 "       .pushsection __ex_table,\"a\"\n"        \
310                 "       .align  3\n"                            \
311                 "       .long   1b, 6b\n"                       \
312                 "       .long   2b, 6b\n"                       \
313                 "       .long   3b, 6b\n"                       \
314                 "       .long   4b, 6b\n"                       \
315                 "       .popsection\n"                          \
316                 : "=r" (err), "=&r" (v), "=&r" (a)              \
317                 : "" (err), "1" (v), "2" (a));                 \
318                 if (err)                                        \
319                         goto fault;                             \
320         } while (0)
321 
322 #define put32_unaligned_check(val,addr) \
323         __put32_unaligned_check("strb", val, addr)
324 
325 #define put32t_unaligned_check(val,addr) \
326         __put32_unaligned_check("strbt", val, addr)
327 
328 static void
329 do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
330 {
331         if (!LDST_U_BIT(instr))
332                 offset.un = -offset.un;
333 
334         if (!LDST_P_BIT(instr))
335                 addr += offset.un;
336 
337         if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
338                 regs->uregs[RN_BITS(instr)] = addr;
339 }
340 
341 static int
342 do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
343 {
344         unsigned int rd = RD_BITS(instr);
345 
346         ai_half += 1;
347 
348         if (user_mode(regs))
349                 goto user;
350 
351         if (LDST_L_BIT(instr)) {
352                 unsigned long val;
353                 get16_unaligned_check(val, addr);
354 
355                 /* signed half-word? */
356                 if (instr & 0x40)
357                         val = (signed long)((signed short) val);
358 
359                 regs->uregs[rd] = val;
360         } else
361                 put16_unaligned_check(regs->uregs[rd], addr);
362 
363         return TYPE_LDST;
364 
365  user:
366         if (LDST_L_BIT(instr)) {
367                 unsigned long val;
368                 unsigned int __ua_flags = uaccess_save_and_enable();
369 
370                 get16t_unaligned_check(val, addr);
371                 uaccess_restore(__ua_flags);
372 
373                 /* signed half-word? */
374                 if (instr & 0x40)
375                         val = (signed long)((signed short) val);
376 
377                 regs->uregs[rd] = val;
378         } else {
379                 unsigned int __ua_flags = uaccess_save_and_enable();
380                 put16t_unaligned_check(regs->uregs[rd], addr);
381                 uaccess_restore(__ua_flags);
382         }
383 
384         return TYPE_LDST;
385 
386  fault:
387         return TYPE_FAULT;
388 }
389 
390 static int
391 do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
392                       struct pt_regs *regs)
393 {
394         unsigned int rd = RD_BITS(instr);
395         unsigned int rd2;
396         int load;
397 
398         if ((instr & 0xfe000000) == 0xe8000000) {
399                 /* ARMv7 Thumb-2 32-bit LDRD/STRD */
400                 rd2 = (instr >> 8) & 0xf;
401                 load = !!(LDST_L_BIT(instr));
402         } else if (((rd & 1) == 1) || (rd == 14))
403                 goto bad;
404         else {
405                 load = ((instr & 0xf0) == 0xd0);
406                 rd2 = rd + 1;
407         }
408 
409         ai_dword += 1;
410 
411         if (user_mode(regs))
412                 goto user;
413 
414         if (load) {
415                 unsigned long val;
416                 get32_unaligned_check(val, addr);
417                 regs->uregs[rd] = val;
418                 get32_unaligned_check(val, addr + 4);
419                 regs->uregs[rd2] = val;
420         } else {
421                 put32_unaligned_check(regs->uregs[rd], addr);
422                 put32_unaligned_check(regs->uregs[rd2], addr + 4);
423         }
424 
425         return TYPE_LDST;
426 
427  user:
428         if (load) {
429                 unsigned long val, val2;
430                 unsigned int __ua_flags = uaccess_save_and_enable();
431 
432                 get32t_unaligned_check(val, addr);
433                 get32t_unaligned_check(val2, addr + 4);
434 
435                 uaccess_restore(__ua_flags);
436 
437                 regs->uregs[rd] = val;
438                 regs->uregs[rd2] = val2;
439         } else {
440                 unsigned int __ua_flags = uaccess_save_and_enable();
441                 put32t_unaligned_check(regs->uregs[rd], addr);
442                 put32t_unaligned_check(regs->uregs[rd2], addr + 4);
443                 uaccess_restore(__ua_flags);
444         }
445 
446         return TYPE_LDST;
447  bad:
448         return TYPE_ERROR;
449  fault:
450         return TYPE_FAULT;
451 }
452 
453 static int
454 do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
455 {
456         unsigned int rd = RD_BITS(instr);
457 
458         ai_word += 1;
459 
460         if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
461                 goto trans;
462 
463         if (LDST_L_BIT(instr)) {
464                 unsigned int val;
465                 get32_unaligned_check(val, addr);
466                 regs->uregs[rd] = val;
467         } else
468                 put32_unaligned_check(regs->uregs[rd], addr);
469         return TYPE_LDST;
470 
471  trans:
472         if (LDST_L_BIT(instr)) {
473                 unsigned int val;
474                 unsigned int __ua_flags = uaccess_save_and_enable();
475                 get32t_unaligned_check(val, addr);
476                 uaccess_restore(__ua_flags);
477                 regs->uregs[rd] = val;
478         } else {
479                 unsigned int __ua_flags = uaccess_save_and_enable();
480                 put32t_unaligned_check(regs->uregs[rd], addr);
481                 uaccess_restore(__ua_flags);
482         }
483         return TYPE_LDST;
484 
485  fault:
486         return TYPE_FAULT;
487 }
488 
489 /*
490  * LDM/STM alignment handler.
491  *
492  * There are 4 variants of this instruction:
493  *
494  * B = rn pointer before instruction, A = rn pointer after instruction
495  *              ------ increasing address ----->
496  *              |    | r0 | r1 | ... | rx |    |
497  * PU = 01             B                    A
498  * PU = 11        B                    A
499  * PU = 00        A                    B
500  * PU = 10             A                    B
501  */
502 static int
503 do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
504 {
505         unsigned int rd, rn, correction, nr_regs, regbits;
506         unsigned long eaddr, newaddr;
507 
508         if (LDM_S_BIT(instr))
509                 goto bad;
510 
511         correction = 4; /* processor implementation defined */
512         regs->ARM_pc += correction;
513 
514         ai_multi += 1;
515 
516         /* count the number of registers in the mask to be transferred */
517         nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
518 
519         rn = RN_BITS(instr);
520         newaddr = eaddr = regs->uregs[rn];
521 
522         if (!LDST_U_BIT(instr))
523                 nr_regs = -nr_regs;
524         newaddr += nr_regs;
525         if (!LDST_U_BIT(instr))
526                 eaddr = newaddr;
527 
528         if (LDST_P_EQ_U(instr)) /* U = P */
529                 eaddr += 4;
530 
531         /*
532          * For alignment faults on the ARM922T/ARM920T the MMU  makes
533          * the FSR (and hence addr) equal to the updated base address
534          * of the multiple access rather than the restored value.
535          * Switch this message off if we've got a ARM92[02], otherwise
536          * [ls]dm alignment faults are noisy!
537          */
538 #if !(defined CONFIG_CPU_ARM922T)  && !(defined CONFIG_CPU_ARM920T)
539         /*
540          * This is a "hint" - we already have eaddr worked out by the
541          * processor for us.
542          */
543         if (addr != eaddr) {
544                 pr_err("LDMSTM: PC = %08lx, instr = %08lx, "
545                         "addr = %08lx, eaddr = %08lx\n",
546                          instruction_pointer(regs), instr, addr, eaddr);
547                 show_regs(regs);
548         }
549 #endif
550 
551         if (user_mode(regs)) {
552                 unsigned int __ua_flags = uaccess_save_and_enable();
553                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
554                      regbits >>= 1, rd += 1)
555                         if (regbits & 1) {
556                                 if (LDST_L_BIT(instr)) {
557                                         unsigned int val;
558                                         get32t_unaligned_check(val, eaddr);
559                                         regs->uregs[rd] = val;
560                                 } else
561                                         put32t_unaligned_check(regs->uregs[rd], eaddr);
562                                 eaddr += 4;
563                         }
564                 uaccess_restore(__ua_flags);
565         } else {
566                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
567                      regbits >>= 1, rd += 1)
568                         if (regbits & 1) {
569                                 if (LDST_L_BIT(instr)) {
570                                         unsigned int val;
571                                         get32_unaligned_check(val, eaddr);
572                                         regs->uregs[rd] = val;
573                                 } else
574                                         put32_unaligned_check(regs->uregs[rd], eaddr);
575                                 eaddr += 4;
576                         }
577         }
578 
579         if (LDST_W_BIT(instr))
580                 regs->uregs[rn] = newaddr;
581         if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
582                 regs->ARM_pc -= correction;
583         return TYPE_DONE;
584 
585 fault:
586         regs->ARM_pc -= correction;
587         return TYPE_FAULT;
588 
589 bad:
590         pr_err("Alignment trap: not handling ldm with s-bit set\n");
591         return TYPE_ERROR;
592 }
593 
594 /*
595  * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
596  * we can reuse ARM userland alignment fault fixups for Thumb.
597  *
598  * This implementation was initially based on the algorithm found in
599  * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
600  * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
601  *
602  * NOTES:
603  * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
604  * 2. If for some reason we're passed an non-ld/st Thumb instruction to
605  *    decode, we return 0xdeadc0de. This should never happen under normal
606  *    circumstances but if it does, we've got other problems to deal with
607  *    elsewhere and we obviously can't fix those problems here.
608  */
609 
610 static unsigned long
611 thumb2arm(u16 tinstr)
612 {
613         u32 L = (tinstr & (1<<11)) >> 11;
614 
615         switch ((tinstr & 0xf800) >> 11) {
616         /* 6.5.1 Format 1: */
617         case 0x6000 >> 11:                              /* 7.1.52 STR(1) */
618         case 0x6800 >> 11:                              /* 7.1.26 LDR(1) */
619         case 0x7000 >> 11:                              /* 7.1.55 STRB(1) */
620         case 0x7800 >> 11:                              /* 7.1.30 LDRB(1) */
621                 return 0xe5800000 |
622                         ((tinstr & (1<<12)) << (22-12)) |       /* fixup */
623                         (L<<20) |                               /* L==1? */
624                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
625                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
626                         ((tinstr & (31<<6)) >>                  /* immed_5 */
627                                 (6 - ((tinstr & (1<<12)) ? 0 : 2)));
628         case 0x8000 >> 11:                              /* 7.1.57 STRH(1) */
629         case 0x8800 >> 11:                              /* 7.1.32 LDRH(1) */
630                 return 0xe1c000b0 |
631                         (L<<20) |                               /* L==1? */
632                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
633                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
634                         ((tinstr & (7<<6)) >> (6-1)) |   /* immed_5[2:0] */
635                         ((tinstr & (3<<9)) >> (9-8));    /* immed_5[4:3] */
636 
637         /* 6.5.1 Format 2: */
638         case 0x5000 >> 11:
639         case 0x5800 >> 11:
640                 {
641                         static const u32 subset[8] = {
642                                 0xe7800000,             /* 7.1.53 STR(2) */
643                                 0xe18000b0,             /* 7.1.58 STRH(2) */
644                                 0xe7c00000,             /* 7.1.56 STRB(2) */
645                                 0xe19000d0,             /* 7.1.34 LDRSB */
646                                 0xe7900000,             /* 7.1.27 LDR(2) */
647                                 0xe19000b0,             /* 7.1.33 LDRH(2) */
648                                 0xe7d00000,             /* 7.1.31 LDRB(2) */
649                                 0xe19000f0              /* 7.1.35 LDRSH */
650                         };
651                         return subset[(tinstr & (7<<9)) >> 9] |
652                             ((tinstr & (7<<0)) << (12-0)) |     /* Rd */
653                             ((tinstr & (7<<3)) << (16-3)) |     /* Rn */
654                             ((tinstr & (7<<6)) >> (6-0));       /* Rm */
655                 }
656 
657         /* 6.5.1 Format 3: */
658         case 0x4800 >> 11:                              /* 7.1.28 LDR(3) */
659                 /* NOTE: This case is not technically possible. We're
660                  *       loading 32-bit memory data via PC relative
661                  *       addressing mode. So we can and should eliminate
662                  *       this case. But I'll leave it here for now.
663                  */
664                 return 0xe59f0000 |
665                     ((tinstr & (7<<8)) << (12-8)) |             /* Rd */
666                     ((tinstr & 255) << (2-0));                  /* immed_8 */
667 
668         /* 6.5.1 Format 4: */
669         case 0x9000 >> 11:                              /* 7.1.54 STR(3) */
670         case 0x9800 >> 11:                              /* 7.1.29 LDR(4) */
671                 return 0xe58d0000 |
672                         (L<<20) |                               /* L==1? */
673                         ((tinstr & (7<<8)) << (12-8)) |         /* Rd */
674                         ((tinstr & 255) << 2);                  /* immed_8 */
675 
676         /* 6.6.1 Format 1: */
677         case 0xc000 >> 11:                              /* 7.1.51 STMIA */
678         case 0xc800 >> 11:                              /* 7.1.25 LDMIA */
679                 {
680                         u32 Rn = (tinstr & (7<<8)) >> 8;
681                         u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
682 
683                         return 0xe8800000 | W | (L<<20) | (Rn<<16) |
684                                 (tinstr&255);
685                 }
686 
687         /* 6.6.1 Format 2: */
688         case 0xb000 >> 11:                              /* 7.1.48 PUSH */
689         case 0xb800 >> 11:                              /* 7.1.47 POP */
690                 if ((tinstr & (3 << 9)) == 0x0400) {
691                         static const u32 subset[4] = {
692                                 0xe92d0000,     /* STMDB sp!,{registers} */
693                                 0xe92d4000,     /* STMDB sp!,{registers,lr} */
694                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
695                                 0xe8bd8000      /* LDMIA sp!,{registers,pc} */
696                         };
697                         return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
698                             (tinstr & 255);             /* register_list */
699                 }
700                 /* Else fall through for illegal instruction case */
701 
702         default:
703                 return BAD_INSTR;
704         }
705 }
706 
707 /*
708  * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
709  * handlable by ARM alignment handler, also find the corresponding handler,
710  * so that we can reuse ARM userland alignment fault fixups for Thumb.
711  *
712  * @pinstr: original Thumb-2 instruction; returns new handlable instruction
713  * @regs: register context.
714  * @poffset: return offset from faulted addr for later writeback
715  *
716  * NOTES:
717  * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
718  * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
719  */
720 static void *
721 do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
722                             union offset_union *poffset)
723 {
724         unsigned long instr = *pinstr;
725         u16 tinst1 = (instr >> 16) & 0xffff;
726         u16 tinst2 = instr & 0xffff;
727 
728         switch (tinst1 & 0xffe0) {
729         /* A6.3.5 Load/Store multiple */
730         case 0xe880:            /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
731         case 0xe8a0:            /* ...above writeback version */
732         case 0xe900:            /* STMDB/STMFD, LDMDB/LDMEA */
733         case 0xe920:            /* ...above writeback version */
734                 /* no need offset decision since handler calculates it */
735                 return do_alignment_ldmstm;
736 
737         case 0xf840:            /* POP/PUSH T3 (single register) */
738                 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
739                         u32 L = !!(LDST_L_BIT(instr));
740                         const u32 subset[2] = {
741                                 0xe92d0000,     /* STMDB sp!,{registers} */
742                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
743                         };
744                         *pinstr = subset[L] | (1<<RD_BITS(instr));
745                         return do_alignment_ldmstm;
746                 }
747                 /* Else fall through for illegal instruction case */
748                 break;
749 
750         /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
751         case 0xe860:
752         case 0xe960:
753         case 0xe8e0:
754         case 0xe9e0:
755                 poffset->un = (tinst2 & 0xff) << 2;
756         case 0xe940:
757         case 0xe9c0:
758                 return do_alignment_ldrdstrd;
759 
760         /*
761          * No need to handle load/store instructions up to word size
762          * since ARMv6 and later CPUs can perform unaligned accesses.
763          */
764         default:
765                 break;
766         }
767         return NULL;
768 }
769 
770 static int
771 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
772 {
773         union offset_union uninitialized_var(offset);
774         unsigned long instr = 0, instrptr;
775         int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
776         unsigned int type;
777         unsigned int fault;
778         u16 tinstr = 0;
779         int isize = 4;
780         int thumb2_32b = 0;
781 
782         if (interrupts_enabled(regs))
783                 local_irq_enable();
784 
785         instrptr = instruction_pointer(regs);
786 
787         if (thumb_mode(regs)) {
788                 u16 *ptr = (u16 *)(instrptr & ~1);
789                 fault = probe_kernel_address(ptr, tinstr);
790                 tinstr = __mem_to_opcode_thumb16(tinstr);
791                 if (!fault) {
792                         if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
793                             IS_T32(tinstr)) {
794                                 /* Thumb-2 32-bit */
795                                 u16 tinst2 = 0;
796                                 fault = probe_kernel_address(ptr + 1, tinst2);
797                                 tinst2 = __mem_to_opcode_thumb16(tinst2);
798                                 instr = __opcode_thumb32_compose(tinstr, tinst2);
799                                 thumb2_32b = 1;
800                         } else {
801                                 isize = 2;
802                                 instr = thumb2arm(tinstr);
803                         }
804                 }
805         } else {
806                 fault = probe_kernel_address(instrptr, instr);
807                 instr = __mem_to_opcode_arm(instr);
808         }
809 
810         if (fault) {
811                 type = TYPE_FAULT;
812                 goto bad_or_fault;
813         }
814 
815         if (user_mode(regs))
816                 goto user;
817 
818         ai_sys += 1;
819         ai_sys_last_pc = (void *)instruction_pointer(regs);
820 
821  fixup:
822 
823         regs->ARM_pc += isize;
824 
825         switch (CODING_BITS(instr)) {
826         case 0x00000000:        /* 3.13.4 load/store instruction extensions */
827                 if (LDSTHD_I_BIT(instr))
828                         offset.un = (instr & 0xf00) >> 4 | (instr & 15);
829                 else
830                         offset.un = regs->uregs[RM_BITS(instr)];
831 
832                 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
833                     (instr & 0x001000f0) == 0x001000f0)   /* LDRSH */
834                         handler = do_alignment_ldrhstrh;
835                 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
836                          (instr & 0x001000f0) == 0x000000f0)   /* STRD */
837                         handler = do_alignment_ldrdstrd;
838                 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
839                         goto swp;
840                 else
841                         goto bad;
842                 break;
843 
844         case 0x04000000:        /* ldr or str immediate */
845                 if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */
846                         goto bad;
847                 offset.un = OFFSET_BITS(instr);
848                 handler = do_alignment_ldrstr;
849                 break;
850 
851         case 0x06000000:        /* ldr or str register */
852                 offset.un = regs->uregs[RM_BITS(instr)];
853 
854                 if (IS_SHIFT(instr)) {
855                         unsigned int shiftval = SHIFT_BITS(instr);
856 
857                         switch(SHIFT_TYPE(instr)) {
858                         case SHIFT_LSL:
859                                 offset.un <<= shiftval;
860                                 break;
861 
862                         case SHIFT_LSR:
863                                 offset.un >>= shiftval;
864                                 break;
865 
866                         case SHIFT_ASR:
867                                 offset.sn >>= shiftval;
868                                 break;
869 
870                         case SHIFT_RORRRX:
871                                 if (shiftval == 0) {
872                                         offset.un >>= 1;
873                                         if (regs->ARM_cpsr & PSR_C_BIT)
874                                                 offset.un |= 1 << 31;
875                                 } else
876                                         offset.un = offset.un >> shiftval |
877                                                           offset.un << (32 - shiftval);
878                                 break;
879                         }
880                 }
881                 handler = do_alignment_ldrstr;
882                 break;
883 
884         case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
885                 if (thumb2_32b) {
886                         offset.un = 0;
887                         handler = do_alignment_t32_to_handler(&instr, regs, &offset);
888                 } else {
889                         offset.un = 0;
890                         handler = do_alignment_ldmstm;
891                 }
892                 break;
893 
894         default:
895                 goto bad;
896         }
897 
898         if (!handler)
899                 goto bad;
900         type = handler(addr, instr, regs);
901 
902         if (type == TYPE_ERROR || type == TYPE_FAULT) {
903                 regs->ARM_pc -= isize;
904                 goto bad_or_fault;
905         }
906 
907         if (type == TYPE_LDST)
908                 do_alignment_finish_ldst(addr, instr, regs, offset);
909 
910         return 0;
911 
912  bad_or_fault:
913         if (type == TYPE_ERROR)
914                 goto bad;
915         /*
916          * We got a fault - fix it up, or die.
917          */
918         do_bad_area(addr, fsr, regs);
919         return 0;
920 
921  swp:
922         pr_err("Alignment trap: not handling swp instruction\n");
923 
924  bad:
925         /*
926          * Oops, we didn't handle the instruction.
927          */
928         pr_err("Alignment trap: not handling instruction "
929                 "%0*lx at [<%08lx>]\n",
930                 isize << 1,
931                 isize == 2 ? tinstr : instr, instrptr);
932         ai_skipped += 1;
933         return 1;
934 
935  user:
936         ai_user += 1;
937 
938         if (ai_usermode & UM_WARN)
939                 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
940                        "Address=0x%08lx FSR 0x%03x\n", current->comm,
941                         task_pid_nr(current), instrptr,
942                         isize << 1,
943                         isize == 2 ? tinstr : instr,
944                         addr, fsr);
945 
946         if (ai_usermode & UM_FIXUP)
947                 goto fixup;
948 
949         if (ai_usermode & UM_SIGNAL) {
950                 siginfo_t si;
951 
952                 si.si_signo = SIGBUS;
953                 si.si_errno = 0;
954                 si.si_code = BUS_ADRALN;
955                 si.si_addr = (void __user *)addr;
956 
957                 force_sig_info(si.si_signo, &si, current);
958         } else {
959                 /*
960                  * We're about to disable the alignment trap and return to
961                  * user space.  But if an interrupt occurs before actually
962                  * reaching user space, then the IRQ vector entry code will
963                  * notice that we were still in kernel space and therefore
964                  * the alignment trap won't be re-enabled in that case as it
965                  * is presumed to be always on from kernel space.
966                  * Let's prevent that race by disabling interrupts here (they
967                  * are disabled on the way back to user space anyway in
968                  * entry-common.S) and disable the alignment trap only if
969                  * there is no work pending for this thread.
970                  */
971                 raw_local_irq_disable();
972                 if (!(current_thread_info()->flags & _TIF_WORK_MASK))
973                         set_cr(cr_no_alignment);
974         }
975 
976         return 0;
977 }
978 
979 static int __init noalign_setup(char *__unused)
980 {
981         set_cr(__clear_cr(CR_A));
982         return 1;
983 }
984 __setup("noalign", noalign_setup);
985 
986 /*
987  * This needs to be done after sysctl_init, otherwise sys/ will be
988  * overwritten.  Actually, this shouldn't be in sys/ at all since
989  * it isn't a sysctl, and it doesn't contain sysctl information.
990  * We now locate it in /proc/cpu/alignment instead.
991  */
992 static int __init alignment_init(void)
993 {
994 #ifdef CONFIG_PROC_FS
995         struct proc_dir_entry *res;
996 
997         res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL,
998                           &alignment_proc_fops);
999         if (!res)
1000                 return -ENOMEM;
1001 #endif
1002 
1003         if (cpu_is_v6_unaligned()) {
1004                 set_cr(__clear_cr(CR_A));
1005                 ai_usermode = safe_usermode(ai_usermode, false);
1006         }
1007 
1008         cr_no_alignment = get_cr() & ~CR_A;
1009 
1010         hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
1011                         "alignment exception");
1012 
1013         /*
1014          * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
1015          * fault, not as alignment error.
1016          *
1017          * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
1018          * needed.
1019          */
1020         if (cpu_architecture() <= CPU_ARCH_ARMv6) {
1021                 hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
1022                                 "alignment exception");
1023         }
1024 
1025         return 0;
1026 }
1027 
1028 fs_initcall(alignment_init);
1029 

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