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Linux/arch/arm/mm/mm-armv.c

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  1 /*
  2  *  linux/arch/arm/mm/mm-armv.c
  3  *
  4  *  Copyright (C) 1998-2000 Russell King
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  *
 10  *  Page table sludge for ARM v3 and v4 processor architectures.
 11  */
 12 #include <linux/sched.h>
 13 #include <linux/mm.h>
 14 #include <linux/init.h>
 15 #include <linux/bootmem.h>
 16 
 17 #include <asm/hardware.h>
 18 #include <asm/pgtable.h>
 19 #include <asm/pgalloc.h>
 20 #include <asm/page.h>
 21 #include <asm/setup.h>
 22 
 23 #include <asm/mach/map.h>
 24 
 25 /*
 26  * These are useful for identifing cache coherency
 27  * problems by allowing the cache or the cache and
 28  * writebuffer to be turned off.  (Note: the write
 29  * buffer should not be on and the cache off).
 30  */
 31 static int __init nocache_setup(char *__unused)
 32 {
 33         cr_alignment &= ~4;
 34         cr_no_alignment &= ~4;
 35         flush_cache_all();
 36         set_cr(cr_alignment);
 37         return 1;
 38 }
 39 
 40 static int __init nowrite_setup(char *__unused)
 41 {
 42         cr_alignment &= ~(8|4);
 43         cr_no_alignment &= ~(8|4);
 44         flush_cache_all();
 45         set_cr(cr_alignment);
 46         return 1;
 47 }
 48 
 49 static int __init noalign_setup(char *__unused)
 50 {
 51         cr_alignment &= ~2;
 52         cr_no_alignment &= ~2;
 53         set_cr(cr_alignment);
 54         return 1;
 55 }
 56 
 57 __setup("noalign", noalign_setup);
 58 __setup("nocache", nocache_setup);
 59 __setup("nowb", nowrite_setup);
 60 
 61 #define FIRST_KERNEL_PGD_NR     (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD)
 62 
 63 #define clean_cache_area(start,size) \
 64         cpu_cache_clean_invalidate_range((unsigned long)start, ((unsigned long)start) + size, 0);
 65 
 66 
 67 /*
 68  * need to get a 16k page for level 1
 69  */
 70 pgd_t *get_pgd_slow(struct mm_struct *mm)
 71 {
 72         pgd_t *new_pgd, *init_pgd;
 73         pmd_t *new_pmd, *init_pmd;
 74         pte_t *new_pte, *init_pte;
 75 
 76         new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 2);
 77         if (!new_pgd)
 78                 goto no_pgd;
 79 
 80         memzero(new_pgd, FIRST_KERNEL_PGD_NR * sizeof(pgd_t));
 81 
 82         init_pgd = pgd_offset_k(0);
 83 
 84         if (vectors_base() == 0) {
 85                 init_pmd = pmd_offset(init_pgd, 0);
 86                 init_pte = pte_offset(init_pmd, 0);
 87 
 88                 /*
 89                  * This lock is here just to satisfy pmd_alloc and pte_lock
 90                  */
 91                 spin_lock(&mm->page_table_lock);
 92 
 93                 /*
 94                  * On ARM, first page must always be allocated since it
 95                  * contains the machine vectors.
 96                  */
 97                 new_pmd = pmd_alloc(mm, new_pgd, 0);
 98                 if (!new_pmd)
 99                         goto no_pmd;
100 
101                 new_pte = pte_alloc(mm, new_pmd, 0);
102                 if (!new_pte)
103                         goto no_pte;
104 
105                 set_pte(new_pte, *init_pte);
106 
107                 spin_unlock(&mm->page_table_lock);
108         }
109 
110         /*
111          * Copy over the kernel and IO PGD entries
112          */
113         memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR,
114                        (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t));
115 
116         /*
117          * FIXME: this should not be necessary
118          */
119         clean_cache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t));
120 
121         return new_pgd;
122 
123 no_pte:
124         spin_unlock(&mm->page_table_lock);
125         pmd_free(new_pmd);
126         check_pgt_cache();
127         free_pages((unsigned long)new_pgd, 2);
128         return NULL;
129 
130 no_pmd:
131         spin_unlock(&mm->page_table_lock);
132         free_pages((unsigned long)new_pgd, 2);
133         return NULL;
134 
135 no_pgd:
136         return NULL;
137 }
138 
139 void free_pgd_slow(pgd_t *pgd)
140 {
141         pmd_t *pmd;
142         pte_t *pte;
143 
144         if (!pgd)
145                 return;
146 
147         /* pgd is always present and good */
148         pmd = (pmd_t *)pgd;
149         if (pmd_none(*pmd))
150                 goto free;
151         if (pmd_bad(*pmd)) {
152                 pmd_ERROR(*pmd);
153                 pmd_clear(pmd);
154                 goto free;
155         }
156 
157         pte = pte_offset(pmd, 0);
158         pmd_clear(pmd);
159         pte_free(pte);
160         pmd_free(pmd);
161         check_pgt_cache();
162 free:
163         free_pages((unsigned long) pgd, 2);
164 }
165 
166 /*
167  * Create a SECTION PGD between VIRT and PHYS in domain
168  * DOMAIN with protection PROT
169  */
170 static inline void
171 alloc_init_section(unsigned long virt, unsigned long phys, int prot)
172 {
173         pmd_t pmd;
174 
175         pmd_val(pmd) = phys | prot;
176 
177         set_pmd(pmd_offset(pgd_offset_k(virt), virt), pmd);
178 }
179 
180 /*
181  * Add a PAGE mapping between VIRT and PHYS in domain
182  * DOMAIN with protection PROT.  Note that due to the
183  * way we map the PTEs, we must allocate two PTE_SIZE'd
184  * blocks - one for the Linux pte table, and one for
185  * the hardware pte table.
186  */
187 static inline void
188 alloc_init_page(unsigned long virt, unsigned long phys, int domain, int prot)
189 {
190         pmd_t *pmdp;
191         pte_t *ptep;
192 
193         pmdp = pmd_offset(pgd_offset_k(virt), virt);
194 
195         if (pmd_none(*pmdp)) {
196                 pte_t *ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
197                                                       sizeof(pte_t));
198 
199                 ptep += PTRS_PER_PTE;
200 
201                 set_pmd(pmdp, __mk_pmd(ptep, PMD_TYPE_TABLE | PMD_DOMAIN(domain)));
202         }
203         ptep = pte_offset(pmdp, virt);
204 
205         set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, __pgprot(prot)));
206 }
207 
208 /*
209  * Clear any PGD mapping.  On a two-level page table system,
210  * the clearance is done by the middle-level functions (pmd)
211  * rather than the top-level (pgd) functions.
212  */
213 static inline void clear_mapping(unsigned long virt)
214 {
215         pmd_clear(pmd_offset(pgd_offset_k(virt), virt));
216 }
217 
218 /*
219  * Create the page directory entries and any necessary
220  * page tables for the mapping specified by `md'.  We
221  * are able to cope here with varying sizes and address
222  * offsets, and we take full advantage of sections.
223  */
224 static void __init create_mapping(struct map_desc *md)
225 {
226         unsigned long virt, length;
227         int prot_sect, prot_pte;
228         long off;
229 
230         if (md->prot_read && md->prot_write &&
231             !md->cacheable && !md->bufferable) {
232                 printk(KERN_WARNING "Security risk: creating user "
233                        "accessible mapping for 0x%08lx at 0x%08lx\n",
234                        md->physical, md->virtual);
235         }
236 
237         if (md->virtual != vectors_base() && md->virtual < PAGE_OFFSET) {
238                 printk(KERN_WARNING "MM: not creating mapping for "
239                        "0x%08lx at 0x%08lx in user region\n",
240                        md->physical, md->virtual);
241         }
242 
243         prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
244                    (md->prot_read  ? L_PTE_USER       : 0) |
245                    (md->prot_write ? L_PTE_WRITE      : 0) |
246                    (md->cacheable  ? L_PTE_CACHEABLE  : 0) |
247                    (md->bufferable ? L_PTE_BUFFERABLE : 0);
248 
249         prot_sect = PMD_TYPE_SECT | PMD_DOMAIN(md->domain) |
250                     (md->prot_read  ? PMD_SECT_AP_READ    : 0) |
251                     (md->prot_write ? PMD_SECT_AP_WRITE   : 0) |
252                     (md->cacheable  ? PMD_SECT_CACHEABLE  : 0) |
253                     (md->bufferable ? PMD_SECT_BUFFERABLE : 0);
254 
255         virt   = md->virtual;
256         off    = md->physical - virt;
257         length = md->length;
258 
259         while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
260                 alloc_init_page(virt, virt + off, md->domain, prot_pte);
261 
262                 virt   += PAGE_SIZE;
263                 length -= PAGE_SIZE;
264         }
265 
266         while (length >= PGDIR_SIZE) {
267                 alloc_init_section(virt, virt + off, prot_sect);
268 
269                 virt   += PGDIR_SIZE;
270                 length -= PGDIR_SIZE;
271         }
272 
273         while (length >= PAGE_SIZE) {
274                 alloc_init_page(virt, virt + off, md->domain, prot_pte);
275 
276                 virt   += PAGE_SIZE;
277                 length -= PAGE_SIZE;
278         }
279 }
280 
281 /*
282  * In order to soft-boot, we need to insert a 1:1 mapping in place of
283  * the user-mode pages.  This will then ensure that we have predictable
284  * results when turning the mmu off
285  */
286 void setup_mm_for_reboot(char mode)
287 {
288         pgd_t *pgd;
289         pmd_t pmd;
290         int i;
291 
292         if (current->mm && current->mm->pgd)
293                 pgd = current->mm->pgd;
294         else
295                 pgd = init_mm.pgd;
296 
297         for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++) {
298                 pmd_val(pmd) = (i << PGDIR_SHIFT) |
299                         PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
300                         PMD_TYPE_SECT;
301                 set_pmd(pmd_offset(pgd + i, i << PGDIR_SHIFT), pmd);
302         }
303 }
304 
305 /*
306  * Setup initial mappings.  We use the page we allocated for zero page to hold
307  * the mappings, which will get overwritten by the vectors in traps_init().
308  * The mappings must be in virtual address order.
309  */
310 void __init memtable_init(struct meminfo *mi)
311 {
312         struct map_desc *init_maps, *p, *q;
313         unsigned long address = 0;
314         int i;
315 
316         init_maps = p = alloc_bootmem_low_pages(PAGE_SIZE);
317 
318         for (i = 0; i < mi->nr_banks; i++) {
319                 if (mi->bank[i].size == 0)
320                         continue;
321 
322                 p->physical   = mi->bank[i].start;
323                 p->virtual    = __phys_to_virt(p->physical);
324                 p->length     = mi->bank[i].size;
325                 p->domain     = DOMAIN_KERNEL;
326                 p->prot_read  = 0;
327                 p->prot_write = 1;
328                 p->cacheable  = 1;
329                 p->bufferable = 1;
330 
331                 p ++;
332         }
333 
334 #ifdef FLUSH_BASE
335         p->physical   = FLUSH_BASE_PHYS;
336         p->virtual    = FLUSH_BASE;
337         p->length     = PGDIR_SIZE;
338         p->domain     = DOMAIN_KERNEL;
339         p->prot_read  = 1;
340         p->prot_write = 0;
341         p->cacheable  = 1;
342         p->bufferable = 1;
343 
344         p ++;
345 #endif
346 
347 #ifdef FLUSH_BASE_MINICACHE
348         p->physical   = FLUSH_BASE_PHYS + PGDIR_SIZE;
349         p->virtual    = FLUSH_BASE_MINICACHE;
350         p->length     = PGDIR_SIZE;
351         p->domain     = DOMAIN_KERNEL;
352         p->prot_read  = 1;
353         p->prot_write = 0;
354         p->cacheable  = 1;
355         p->bufferable = 0;
356 
357         p ++;
358 #endif
359 
360         /*
361          * Go through the initial mappings, but clear out any
362          * pgdir entries that are not in the description.
363          */
364         q = init_maps;
365         do {
366                 if (address < q->virtual || q == p) {
367                         clear_mapping(address);
368                         address += PGDIR_SIZE;
369                 } else {
370                         create_mapping(q);
371 
372                         address = q->virtual + q->length;
373                         address = (address + PGDIR_SIZE - 1) & PGDIR_MASK;
374 
375                         q ++;
376                 }
377         } while (address != 0);
378 
379         /*
380          * Create a mapping for the machine vectors at virtual address 0
381          * or 0xffff0000.  We should always try the high mapping.
382          */
383         init_maps->physical   = virt_to_phys(init_maps);
384         init_maps->virtual    = vectors_base();
385         init_maps->length     = PAGE_SIZE;
386         init_maps->domain     = DOMAIN_USER;
387         init_maps->prot_read  = 0;
388         init_maps->prot_write = 0;
389         init_maps->cacheable  = 1;
390         init_maps->bufferable = 0;
391 
392         create_mapping(init_maps);
393 }
394 
395 /*
396  * Create the architecture specific mappings
397  */
398 void __init iotable_init(struct map_desc *io_desc)
399 {
400         int i;
401 
402         for (i = 0; io_desc[i].last == 0; i++)
403                 create_mapping(io_desc + i);
404 }
405 
406 static inline void free_memmap(int node, unsigned long start, unsigned long end)
407 {
408         unsigned long pg, pgend;
409 
410         start = __phys_to_virt(start);
411         end   = __phys_to_virt(end);
412 
413         pg    = PAGE_ALIGN((unsigned long)(virt_to_page(start)));
414         pgend = ((unsigned long)(virt_to_page(end))) & PAGE_MASK;
415 
416         start = __virt_to_phys(pg);
417         end   = __virt_to_phys(pgend);
418 
419         free_bootmem_node(NODE_DATA(node), start, end - start);
420 }
421 
422 static inline void free_unused_memmap_node(int node, struct meminfo *mi)
423 {
424         unsigned long bank_start, prev_bank_end = 0;
425         unsigned int i;
426 
427         /*
428          * [FIXME] This relies on each bank being in address order.  This
429          * may not be the case, especially if the user has provided the
430          * information on the command line.
431          */
432         for (i = 0; i < mi->nr_banks; i++) {
433                 if (mi->bank[i].size == 0 || mi->bank[i].node != node)
434                         continue;
435 
436                 bank_start = mi->bank[i].start & PAGE_MASK;
437 
438                 /*
439                  * If we had a previous bank, and there is a space
440                  * between the current bank and the previous, free it.
441                  */
442                 if (prev_bank_end && prev_bank_end != bank_start)
443                         free_memmap(node, prev_bank_end, bank_start);
444 
445                 prev_bank_end = PAGE_ALIGN(mi->bank[i].start +
446                                            mi->bank[i].size);
447         }
448 }
449 
450 /*
451  * The mem_map array can get very big.  Free
452  * the unused area of the memory map.
453  */
454 void __init create_memmap_holes(struct meminfo *mi)
455 {
456         int node;
457 
458         for (node = 0; node < numnodes; node++)
459                 free_unused_memmap_node(node, mi);
460 }
461 
462 /*
463  * PTE table allocation cache.
464  *
465  * This is a move away from our custom 2K page allocator.  We now use the
466  * slab cache to keep track of these objects.
467  *
468  * With this, it is questionable as to whether the PGT cache gains us
469  * anything.  We may be better off dropping the PTE stuff from our PGT
470  * cache implementation.
471  */
472 kmem_cache_t *pte_cache;
473 
474 /*
475  * The constructor gets called for each object within the cache when the
476  * cache page is created.  Note that if slab tries to misalign the blocks,
477  * we BUG() loudly.
478  */
479 static void pte_cache_ctor(void *pte, kmem_cache_t *cache, unsigned long flags)
480 {
481         unsigned long block = (unsigned long)pte;
482 
483         if (block & 2047)
484                 BUG();
485 
486         memzero(pte, 2 * PTRS_PER_PTE * sizeof(pte_t));
487         cpu_cache_clean_invalidate_range(block, block +
488                         PTRS_PER_PTE * sizeof(pte_t), 0);
489 }
490 
491 void __init pgtable_cache_init(void)
492 {
493         pte_cache = kmem_cache_create("pte-cache",
494                                 2 * PTRS_PER_PTE * sizeof(pte_t), 0, 0,
495                                 pte_cache_ctor, NULL);
496         if (!pte_cache)
497                 BUG();
498 }
499 

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