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TOMOYO Linux Cross Reference
Linux/arch/arm/plat-omap/include/plat/dmtimer.h

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  1 /*
  2  * arch/arm/plat-omap/include/plat/dmtimer.h
  3  *
  4  * OMAP Dual-Mode Timers
  5  *
  6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  7  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
  8  * Thara Gopinath <thara@ti.com>
  9  *
 10  * Platform device conversion and hwmod support.
 11  *
 12  * Copyright (C) 2005 Nokia Corporation
 13  * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
 14  * PWM and clock framwork support by Timo Teras.
 15  *
 16  * This program is free software; you can redistribute it and/or modify it
 17  * under the terms of the GNU General Public License as published by the
 18  * Free Software Foundation; either version 2 of the License, or (at your
 19  * option) any later version.
 20  *
 21  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
 24  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 26  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 29  *
 30  * You should have received a copy of the  GNU General Public License along
 31  * with this program; if not, write  to the Free Software Foundation, Inc.,
 32  * 675 Mass Ave, Cambridge, MA 02139, USA.
 33  */
 34 
 35 #include <linux/clk.h>
 36 #include <linux/delay.h>
 37 #include <linux/io.h>
 38 #include <linux/platform_device.h>
 39 
 40 #ifndef __ASM_ARCH_DMTIMER_H
 41 #define __ASM_ARCH_DMTIMER_H
 42 
 43 /* clock sources */
 44 #define OMAP_TIMER_SRC_SYS_CLK                  0x00
 45 #define OMAP_TIMER_SRC_32_KHZ                   0x01
 46 #define OMAP_TIMER_SRC_EXT_CLK                  0x02
 47 
 48 /* timer interrupt enable bits */
 49 #define OMAP_TIMER_INT_CAPTURE                  (1 << 2)
 50 #define OMAP_TIMER_INT_OVERFLOW                 (1 << 1)
 51 #define OMAP_TIMER_INT_MATCH                    (1 << 0)
 52 
 53 /* trigger types */
 54 #define OMAP_TIMER_TRIGGER_NONE                 0x00
 55 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
 56 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
 57 
 58 /*
 59  * IP revision identifier so that Highlander IP
 60  * in OMAP4 can be distinguished.
 61  */
 62 #define OMAP_TIMER_IP_VERSION_1                        0x1
 63 
 64 /* timer capabilities used in hwmod database */
 65 #define OMAP_TIMER_SECURE                               0x80000000
 66 #define OMAP_TIMER_ALWON                                0x40000000
 67 #define OMAP_TIMER_HAS_PWM                              0x20000000
 68 
 69 struct omap_timer_capability_dev_attr {
 70         u32 timer_capability;
 71 };
 72 
 73 struct omap_dm_timer;
 74 struct clk;
 75 
 76 struct timer_regs {
 77         u32 tidr;
 78         u32 tiocp_cfg;
 79         u32 tistat;
 80         u32 tisr;
 81         u32 tier;
 82         u32 twer;
 83         u32 tclr;
 84         u32 tcrr;
 85         u32 tldr;
 86         u32 ttrg;
 87         u32 twps;
 88         u32 tmar;
 89         u32 tcar1;
 90         u32 tsicr;
 91         u32 tcar2;
 92         u32 tpir;
 93         u32 tnir;
 94         u32 tcvr;
 95         u32 tocr;
 96         u32 towr;
 97 };
 98 
 99 struct dmtimer_platform_data {
100         int (*set_timer_src)(struct platform_device *pdev, int source);
101         int timer_ip_version;
102         u32 needs_manual_reset:1;
103         bool reserved;
104 
105         bool loses_context;
106 
107         int (*get_context_loss_count)(struct device *dev);
108 };
109 
110 struct omap_dm_timer *omap_dm_timer_request(void);
111 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
112 int omap_dm_timer_free(struct omap_dm_timer *timer);
113 void omap_dm_timer_enable(struct omap_dm_timer *timer);
114 void omap_dm_timer_disable(struct omap_dm_timer *timer);
115 
116 int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
117 
118 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
119 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
120 
121 int omap_dm_timer_trigger(struct omap_dm_timer *timer);
122 int omap_dm_timer_start(struct omap_dm_timer *timer);
123 int omap_dm_timer_stop(struct omap_dm_timer *timer);
124 
125 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
126 int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
127 int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
128 int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
129 int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
130 int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
131 
132 int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
133 
134 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
135 int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
136 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
137 int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
138 
139 int omap_dm_timers_active(void);
140 
141 /*
142  * Do not use the defines below, they are not needed. They should be only
143  * used by dmtimer.c and sys_timer related code.
144  */
145 
146 /*
147  * The interrupt registers are different between v1 and v2 ip.
148  * These registers are offsets from timer->iobase.
149  */
150 #define OMAP_TIMER_ID_OFFSET            0x00
151 #define OMAP_TIMER_OCP_CFG_OFFSET       0x10
152 
153 #define OMAP_TIMER_V1_SYS_STAT_OFFSET   0x14
154 #define OMAP_TIMER_V1_STAT_OFFSET       0x18
155 #define OMAP_TIMER_V1_INT_EN_OFFSET     0x1c
156 
157 #define OMAP_TIMER_V2_IRQSTATUS_RAW     0x24
158 #define OMAP_TIMER_V2_IRQSTATUS         0x28
159 #define OMAP_TIMER_V2_IRQENABLE_SET     0x2c
160 #define OMAP_TIMER_V2_IRQENABLE_CLR     0x30
161 
162 /*
163  * The functional registers have a different base on v1 and v2 ip.
164  * These registers are offsets from timer->func_base. The func_base
165  * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
166  *
167  */
168 #define OMAP_TIMER_V2_FUNC_OFFSET               0x14
169 
170 #define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
171 #define _OMAP_TIMER_CTRL_OFFSET         0x24
172 #define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
173 #define         OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
174 #define         OMAP_TIMER_CTRL_PT              (1 << 12)
175 #define         OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
176 #define         OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
177 #define         OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
178 #define         OMAP_TIMER_CTRL_SCPWM           (1 << 7)
179 #define         OMAP_TIMER_CTRL_CE              (1 << 6) /* compare enable */
180 #define         OMAP_TIMER_CTRL_PRE             (1 << 5) /* prescaler enable */
181 #define         OMAP_TIMER_CTRL_PTV_SHIFT       2 /* prescaler value shift */
182 #define         OMAP_TIMER_CTRL_POSTED          (1 << 2)
183 #define         OMAP_TIMER_CTRL_AR              (1 << 1) /* auto-reload enable */
184 #define         OMAP_TIMER_CTRL_ST              (1 << 0) /* start timer */
185 #define _OMAP_TIMER_COUNTER_OFFSET      0x28
186 #define _OMAP_TIMER_LOAD_OFFSET         0x2c
187 #define _OMAP_TIMER_TRIGGER_OFFSET      0x30
188 #define _OMAP_TIMER_WRITE_PEND_OFFSET   0x34
189 #define         WP_NONE                 0       /* no write pending bit */
190 #define         WP_TCLR                 (1 << 0)
191 #define         WP_TCRR                 (1 << 1)
192 #define         WP_TLDR                 (1 << 2)
193 #define         WP_TTGR                 (1 << 3)
194 #define         WP_TMAR                 (1 << 4)
195 #define         WP_TPIR                 (1 << 5)
196 #define         WP_TNIR                 (1 << 6)
197 #define         WP_TCVR                 (1 << 7)
198 #define         WP_TOCR                 (1 << 8)
199 #define         WP_TOWR                 (1 << 9)
200 #define _OMAP_TIMER_MATCH_OFFSET        0x38
201 #define _OMAP_TIMER_CAPTURE_OFFSET      0x3c
202 #define _OMAP_TIMER_IF_CTRL_OFFSET      0x40
203 #define _OMAP_TIMER_CAPTURE2_OFFSET             0x44    /* TCAR2, 34xx only */
204 #define _OMAP_TIMER_TICK_POS_OFFSET             0x48    /* TPIR, 34xx only */
205 #define _OMAP_TIMER_TICK_NEG_OFFSET             0x4c    /* TNIR, 34xx only */
206 #define _OMAP_TIMER_TICK_COUNT_OFFSET           0x50    /* TCVR, 34xx only */
207 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET    0x54    /* TOCR, 34xx only */
208 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET  0x58    /* TOWR, 34xx only */
209 
210 /* register offsets with the write pending bit encoded */
211 #define WPSHIFT                                 16
212 
213 #define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
214                                                         | (WP_NONE << WPSHIFT))
215 
216 #define OMAP_TIMER_CTRL_REG                     (_OMAP_TIMER_CTRL_OFFSET \
217                                                         | (WP_TCLR << WPSHIFT))
218 
219 #define OMAP_TIMER_COUNTER_REG                  (_OMAP_TIMER_COUNTER_OFFSET \
220                                                         | (WP_TCRR << WPSHIFT))
221 
222 #define OMAP_TIMER_LOAD_REG                     (_OMAP_TIMER_LOAD_OFFSET \
223                                                         | (WP_TLDR << WPSHIFT))
224 
225 #define OMAP_TIMER_TRIGGER_REG                  (_OMAP_TIMER_TRIGGER_OFFSET \
226                                                         | (WP_TTGR << WPSHIFT))
227 
228 #define OMAP_TIMER_WRITE_PEND_REG               (_OMAP_TIMER_WRITE_PEND_OFFSET \
229                                                         | (WP_NONE << WPSHIFT))
230 
231 #define OMAP_TIMER_MATCH_REG                    (_OMAP_TIMER_MATCH_OFFSET \
232                                                         | (WP_TMAR << WPSHIFT))
233 
234 #define OMAP_TIMER_CAPTURE_REG                  (_OMAP_TIMER_CAPTURE_OFFSET \
235                                                         | (WP_NONE << WPSHIFT))
236 
237 #define OMAP_TIMER_IF_CTRL_REG                  (_OMAP_TIMER_IF_CTRL_OFFSET \
238                                                         | (WP_NONE << WPSHIFT))
239 
240 #define OMAP_TIMER_CAPTURE2_REG                 (_OMAP_TIMER_CAPTURE2_OFFSET \
241                                                         | (WP_NONE << WPSHIFT))
242 
243 #define OMAP_TIMER_TICK_POS_REG                 (_OMAP_TIMER_TICK_POS_OFFSET \
244                                                         | (WP_TPIR << WPSHIFT))
245 
246 #define OMAP_TIMER_TICK_NEG_REG                 (_OMAP_TIMER_TICK_NEG_OFFSET \
247                                                         | (WP_TNIR << WPSHIFT))
248 
249 #define OMAP_TIMER_TICK_COUNT_REG               (_OMAP_TIMER_TICK_COUNT_OFFSET \
250                                                         | (WP_TCVR << WPSHIFT))
251 
252 #define OMAP_TIMER_TICK_INT_MASK_SET_REG                                \
253                 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
254 
255 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
256                 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
257 
258 struct omap_dm_timer {
259         unsigned long phys_base;
260         int id;
261         int irq;
262         struct clk *iclk, *fclk;
263 
264         void __iomem    *io_base;
265         void __iomem    *sys_stat;      /* TISTAT timer status */
266         void __iomem    *irq_stat;      /* TISR/IRQSTATUS interrupt status */
267         void __iomem    *irq_ena;       /* irq enable */
268         void __iomem    *irq_dis;       /* irq disable, only on v2 ip */
269         void __iomem    *pend;          /* write pending */
270         void __iomem    *func_base;     /* function register base */
271 
272         unsigned long rate;
273         unsigned reserved:1;
274         unsigned posted:1;
275         struct timer_regs context;
276         bool loses_context;
277         int ctx_loss_count;
278         int revision;
279         struct platform_device *pdev;
280         struct list_head node;
281 
282         int (*get_context_loss_count)(struct device *dev);
283 };
284 
285 int omap_dm_timer_prepare(struct omap_dm_timer *timer);
286 
287 static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
288                                                 int posted)
289 {
290         if (posted)
291                 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
292                         cpu_relax();
293 
294         return __raw_readl(timer->func_base + (reg & 0xff));
295 }
296 
297 static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
298                                         u32 reg, u32 val, int posted)
299 {
300         if (posted)
301                 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
302                         cpu_relax();
303 
304         __raw_writel(val, timer->func_base + (reg & 0xff));
305 }
306 
307 static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
308 {
309         u32 tidr;
310 
311         /* Assume v1 ip if bits [31:16] are zero */
312         tidr = __raw_readl(timer->io_base);
313         if (!(tidr >> 16)) {
314                 timer->revision = 1;
315                 timer->sys_stat = timer->io_base +
316                                 OMAP_TIMER_V1_SYS_STAT_OFFSET;
317                 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
318                 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
319                 timer->irq_dis = 0;
320                 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
321                 timer->func_base = timer->io_base;
322         } else {
323                 timer->revision = 2;
324                 timer->sys_stat = 0;
325                 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
326                 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
327                 timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
328                 timer->pend = timer->io_base +
329                         _OMAP_TIMER_WRITE_PEND_OFFSET +
330                                 OMAP_TIMER_V2_FUNC_OFFSET;
331                 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
332         }
333 }
334 
335 /* Assumes the source clock has been set by caller */
336 static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
337                                         int autoidle, int wakeup)
338 {
339         u32 l;
340 
341         l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
342         l |= 0x02 << 3;  /* Set to smart-idle mode */
343         l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
344 
345         if (autoidle)
346                 l |= 0x1 << 0;
347 
348         if (wakeup)
349                 l |= 1 << 2;
350 
351         __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
352 
353         /* Match hardware reset default of posted mode */
354         __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
355                                         OMAP_TIMER_CTRL_POSTED, 0);
356 }
357 
358 static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
359                                                 struct clk *parent)
360 {
361         int ret;
362 
363         clk_disable(timer_fck);
364         ret = clk_set_parent(timer_fck, parent);
365         clk_enable(timer_fck);
366 
367         /*
368          * When the functional clock disappears, too quick writes seem
369          * to cause an abort. XXX Is this still necessary?
370          */
371         __delay(300000);
372 
373         return ret;
374 }
375 
376 static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
377                                         int posted, unsigned long rate)
378 {
379         u32 l;
380 
381         l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
382         if (l & OMAP_TIMER_CTRL_ST) {
383                 l &= ~0x1;
384                 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
385 #ifdef CONFIG_ARCH_OMAP2PLUS
386                 /* Readback to make sure write has completed */
387                 __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
388                 /*
389                  * Wait for functional clock period x 3.5 to make sure that
390                  * timer is stopped
391                  */
392                 udelay(3500000 / rate + 1);
393 #endif
394         }
395 
396         /* Ack possibly pending interrupt */
397         __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
398 }
399 
400 static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
401                                                 u32 ctrl, unsigned int load,
402                                                 int posted)
403 {
404         __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
405         __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
406 }
407 
408 static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
409                                                 unsigned int value)
410 {
411         __raw_writel(value, timer->irq_ena);
412         __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
413 }
414 
415 static inline unsigned int
416 __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
417 {
418         return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
419 }
420 
421 static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
422                                                 unsigned int value)
423 {
424         __raw_writel(value, timer->irq_stat);
425 }
426 
427 #endif /* __ASM_ARCH_DMTIMER_H */
428 

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