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Linux/arch/arm64/include/asm/debug-monitors.h

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  1 /*
  2  * Copyright (C) 2012 ARM Ltd.
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License version 2 as
  6  * published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope that it will be useful,
  9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11  * GNU General Public License for more details.
 12  *
 13  * You should have received a copy of the GNU General Public License
 14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 15  */
 16 #ifndef __ASM_DEBUG_MONITORS_H
 17 #define __ASM_DEBUG_MONITORS_H
 18 
 19 #ifdef __KERNEL__
 20 
 21 #include <linux/errno.h>
 22 #include <linux/types.h>
 23 #include <asm/brk-imm.h>
 24 #include <asm/esr.h>
 25 #include <asm/insn.h>
 26 #include <asm/ptrace.h>
 27 
 28 /* Low-level stepping controls. */
 29 #define DBG_MDSCR_SS            (1 << 0)
 30 #define DBG_SPSR_SS             (1 << 21)
 31 
 32 /* MDSCR_EL1 enabling bits */
 33 #define DBG_MDSCR_KDE           (1 << 13)
 34 #define DBG_MDSCR_MDE           (1 << 15)
 35 #define DBG_MDSCR_MASK          ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)
 36 
 37 #define DBG_ESR_EVT(x)          (((x) >> 27) & 0x7)
 38 
 39 /* AArch64 */
 40 #define DBG_ESR_EVT_HWBP        0x0
 41 #define DBG_ESR_EVT_HWSS        0x1
 42 #define DBG_ESR_EVT_HWWP        0x2
 43 #define DBG_ESR_EVT_BRK         0x6
 44 
 45 /*
 46  * Break point instruction encoding
 47  */
 48 #define BREAK_INSTR_SIZE                AARCH64_INSN_SIZE
 49 
 50 /*
 51  * BRK instruction encoding
 52  * The #imm16 value should be placed at bits[20:5] within BRK ins
 53  */
 54 #define AARCH64_BREAK_MON       0xd4200000
 55 
 56 /*
 57  * BRK instruction for provoking a fault on purpose
 58  * Unlike kgdb, #imm16 value with unallocated handler is used for faulting.
 59  */
 60 #define AARCH64_BREAK_FAULT     (AARCH64_BREAK_MON | (FAULT_BRK_IMM << 5))
 61 
 62 #define AARCH64_BREAK_KGDB_DYN_DBG      \
 63         (AARCH64_BREAK_MON | (KGDB_DYN_DBG_BRK_IMM << 5))
 64 
 65 #define CACHE_FLUSH_IS_SAFE             1
 66 
 67 /* kprobes BRK opcodes with ESR encoding  */
 68 #define BRK64_ESR_MASK          0xFFFF
 69 #define BRK64_ESR_KPROBES       0x0004
 70 #define BRK64_OPCODE_KPROBES    (AARCH64_BREAK_MON | (BRK64_ESR_KPROBES << 5))
 71 /* uprobes BRK opcodes with ESR encoding  */
 72 #define BRK64_ESR_UPROBES       0x0005
 73 #define BRK64_OPCODE_UPROBES    (AARCH64_BREAK_MON | (BRK64_ESR_UPROBES << 5))
 74 
 75 /* AArch32 */
 76 #define DBG_ESR_EVT_BKPT        0x4
 77 #define DBG_ESR_EVT_VECC        0x5
 78 
 79 #define AARCH32_BREAK_ARM       0x07f001f0
 80 #define AARCH32_BREAK_THUMB     0xde01
 81 #define AARCH32_BREAK_THUMB2_LO 0xf7f0
 82 #define AARCH32_BREAK_THUMB2_HI 0xa000
 83 
 84 #ifndef __ASSEMBLY__
 85 struct task_struct;
 86 
 87 #define DBG_ARCH_ID_RESERVED    0       /* In case of ptrace ABI updates. */
 88 
 89 #define DBG_HOOK_HANDLED        0
 90 #define DBG_HOOK_ERROR          1
 91 
 92 struct step_hook {
 93         struct list_head node;
 94         int (*fn)(struct pt_regs *regs, unsigned int esr);
 95 };
 96 
 97 void register_step_hook(struct step_hook *hook);
 98 void unregister_step_hook(struct step_hook *hook);
 99 
100 struct break_hook {
101         struct list_head node;
102         u32 esr_val;
103         u32 esr_mask;
104         int (*fn)(struct pt_regs *regs, unsigned int esr);
105 };
106 
107 void register_break_hook(struct break_hook *hook);
108 void unregister_break_hook(struct break_hook *hook);
109 
110 u8 debug_monitors_arch(void);
111 
112 enum dbg_active_el {
113         DBG_ACTIVE_EL0 = 0,
114         DBG_ACTIVE_EL1,
115 };
116 
117 void enable_debug_monitors(enum dbg_active_el el);
118 void disable_debug_monitors(enum dbg_active_el el);
119 
120 void user_rewind_single_step(struct task_struct *task);
121 void user_fastforward_single_step(struct task_struct *task);
122 
123 void kernel_enable_single_step(struct pt_regs *regs);
124 void kernel_disable_single_step(void);
125 int kernel_active_single_step(void);
126 
127 #ifdef CONFIG_HAVE_HW_BREAKPOINT
128 int reinstall_suspended_bps(struct pt_regs *regs);
129 #else
130 static inline int reinstall_suspended_bps(struct pt_regs *regs)
131 {
132         return -ENODEV;
133 }
134 #endif
135 
136 int aarch32_break_handler(struct pt_regs *regs);
137 
138 #endif  /* __ASSEMBLY */
139 #endif  /* __KERNEL__ */
140 #endif  /* __ASM_DEBUG_MONITORS_H */
141 

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