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TOMOYO Linux Cross Reference
Linux/arch/arm64/include/asm/kvm_host.h

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  1 /*
  2  * Copyright (C) 2012,2013 - ARM Ltd
  3  * Author: Marc Zyngier <marc.zyngier@arm.com>
  4  *
  5  * Derived from arch/arm/include/asm/kvm_host.h:
  6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
  7  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 20  */
 21 
 22 #ifndef __ARM64_KVM_HOST_H__
 23 #define __ARM64_KVM_HOST_H__
 24 
 25 #include <linux/types.h>
 26 #include <linux/kvm_types.h>
 27 #include <asm/cpufeature.h>
 28 #include <asm/daifflags.h>
 29 #include <asm/fpsimd.h>
 30 #include <asm/kvm.h>
 31 #include <asm/kvm_asm.h>
 32 #include <asm/kvm_mmio.h>
 33 #include <asm/thread_info.h>
 34 
 35 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
 36 
 37 #define KVM_USER_MEM_SLOTS 512
 38 #define KVM_HALT_POLL_NS_DEFAULT 500000
 39 
 40 #include <kvm/arm_vgic.h>
 41 #include <kvm/arm_arch_timer.h>
 42 #include <kvm/arm_pmu.h>
 43 
 44 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
 45 
 46 #define KVM_VCPU_MAX_FEATURES 4
 47 
 48 #define KVM_REQ_SLEEP \
 49         KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
 50 #define KVM_REQ_IRQ_PENDING     KVM_ARCH_REQ(1)
 51 
 52 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
 53 
 54 int __attribute_const__ kvm_target_cpu(void);
 55 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
 56 int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext);
 57 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
 58 
 59 struct kvm_arch {
 60         /* The VMID generation used for the virt. memory system */
 61         u64    vmid_gen;
 62         u32    vmid;
 63 
 64         /* stage2 entry level table */
 65         pgd_t *pgd;
 66 
 67         /* VTTBR value associated with above pgd and vmid */
 68         u64    vttbr;
 69         /* VTCR_EL2 value for this VM */
 70         u64    vtcr;
 71 
 72         /* The last vcpu id that ran on each physical CPU */
 73         int __percpu *last_vcpu_ran;
 74 
 75         /* The maximum number of vCPUs depends on the used GIC model */
 76         int max_vcpus;
 77 
 78         /* Interrupt controller */
 79         struct vgic_dist        vgic;
 80 
 81         /* Mandated version of PSCI */
 82         u32 psci_version;
 83 };
 84 
 85 #define KVM_NR_MEM_OBJS     40
 86 
 87 /*
 88  * We don't want allocation failures within the mmu code, so we preallocate
 89  * enough memory for a single page fault in a cache.
 90  */
 91 struct kvm_mmu_memory_cache {
 92         int nobjs;
 93         void *objects[KVM_NR_MEM_OBJS];
 94 };
 95 
 96 struct kvm_vcpu_fault_info {
 97         u32 esr_el2;            /* Hyp Syndrom Register */
 98         u64 far_el2;            /* Hyp Fault Address Register */
 99         u64 hpfar_el2;          /* Hyp IPA Fault Address Register */
100         u64 disr_el1;           /* Deferred [SError] Status Register */
101 };
102 
103 /*
104  * 0 is reserved as an invalid value.
105  * Order should be kept in sync with the save/restore code.
106  */
107 enum vcpu_sysreg {
108         __INVALID_SYSREG__,
109         MPIDR_EL1,      /* MultiProcessor Affinity Register */
110         CSSELR_EL1,     /* Cache Size Selection Register */
111         SCTLR_EL1,      /* System Control Register */
112         ACTLR_EL1,      /* Auxiliary Control Register */
113         CPACR_EL1,      /* Coprocessor Access Control */
114         TTBR0_EL1,      /* Translation Table Base Register 0 */
115         TTBR1_EL1,      /* Translation Table Base Register 1 */
116         TCR_EL1,        /* Translation Control Register */
117         ESR_EL1,        /* Exception Syndrome Register */
118         AFSR0_EL1,      /* Auxiliary Fault Status Register 0 */
119         AFSR1_EL1,      /* Auxiliary Fault Status Register 1 */
120         FAR_EL1,        /* Fault Address Register */
121         MAIR_EL1,       /* Memory Attribute Indirection Register */
122         VBAR_EL1,       /* Vector Base Address Register */
123         CONTEXTIDR_EL1, /* Context ID Register */
124         TPIDR_EL0,      /* Thread ID, User R/W */
125         TPIDRRO_EL0,    /* Thread ID, User R/O */
126         TPIDR_EL1,      /* Thread ID, Privileged */
127         AMAIR_EL1,      /* Aux Memory Attribute Indirection Register */
128         CNTKCTL_EL1,    /* Timer Control Register (EL1) */
129         PAR_EL1,        /* Physical Address Register */
130         MDSCR_EL1,      /* Monitor Debug System Control Register */
131         MDCCINT_EL1,    /* Monitor Debug Comms Channel Interrupt Enable Reg */
132         DISR_EL1,       /* Deferred Interrupt Status Register */
133 
134         /* Performance Monitors Registers */
135         PMCR_EL0,       /* Control Register */
136         PMSELR_EL0,     /* Event Counter Selection Register */
137         PMEVCNTR0_EL0,  /* Event Counter Register (0-30) */
138         PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
139         PMCCNTR_EL0,    /* Cycle Counter Register */
140         PMEVTYPER0_EL0, /* Event Type Register (0-30) */
141         PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
142         PMCCFILTR_EL0,  /* Cycle Count Filter Register */
143         PMCNTENSET_EL0, /* Count Enable Set Register */
144         PMINTENSET_EL1, /* Interrupt Enable Set Register */
145         PMOVSSET_EL0,   /* Overflow Flag Status Set Register */
146         PMSWINC_EL0,    /* Software Increment Register */
147         PMUSERENR_EL0,  /* User Enable Register */
148 
149         /* 32bit specific registers. Keep them at the end of the range */
150         DACR32_EL2,     /* Domain Access Control Register */
151         IFSR32_EL2,     /* Instruction Fault Status Register */
152         FPEXC32_EL2,    /* Floating-Point Exception Control Register */
153         DBGVCR32_EL2,   /* Debug Vector Catch Register */
154 
155         NR_SYS_REGS     /* Nothing after this line! */
156 };
157 
158 /* 32bit mapping */
159 #define c0_MPIDR        (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
160 #define c0_CSSELR       (CSSELR_EL1 * 2)/* Cache Size Selection Register */
161 #define c1_SCTLR        (SCTLR_EL1 * 2) /* System Control Register */
162 #define c1_ACTLR        (ACTLR_EL1 * 2) /* Auxiliary Control Register */
163 #define c1_CPACR        (CPACR_EL1 * 2) /* Coprocessor Access Control */
164 #define c2_TTBR0        (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
165 #define c2_TTBR0_high   (c2_TTBR0 + 1)  /* TTBR0 top 32 bits */
166 #define c2_TTBR1        (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
167 #define c2_TTBR1_high   (c2_TTBR1 + 1)  /* TTBR1 top 32 bits */
168 #define c2_TTBCR        (TCR_EL1 * 2)   /* Translation Table Base Control R. */
169 #define c3_DACR         (DACR32_EL2 * 2)/* Domain Access Control Register */
170 #define c5_DFSR         (ESR_EL1 * 2)   /* Data Fault Status Register */
171 #define c5_IFSR         (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
172 #define c5_ADFSR        (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
173 #define c5_AIFSR        (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
174 #define c6_DFAR         (FAR_EL1 * 2)   /* Data Fault Address Register */
175 #define c6_IFAR         (c6_DFAR + 1)   /* Instruction Fault Address Register */
176 #define c7_PAR          (PAR_EL1 * 2)   /* Physical Address Register */
177 #define c7_PAR_high     (c7_PAR + 1)    /* PAR top 32 bits */
178 #define c10_PRRR        (MAIR_EL1 * 2)  /* Primary Region Remap Register */
179 #define c10_NMRR        (c10_PRRR + 1)  /* Normal Memory Remap Register */
180 #define c12_VBAR        (VBAR_EL1 * 2)  /* Vector Base Address Register */
181 #define c13_CID         (CONTEXTIDR_EL1 * 2)    /* Context ID Register */
182 #define c13_TID_URW     (TPIDR_EL0 * 2) /* Thread ID, User R/W */
183 #define c13_TID_URO     (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
184 #define c13_TID_PRIV    (TPIDR_EL1 * 2) /* Thread ID, Privileged */
185 #define c10_AMAIR0      (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
186 #define c10_AMAIR1      (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
187 #define c14_CNTKCTL     (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
188 
189 #define cp14_DBGDSCRext (MDSCR_EL1 * 2)
190 #define cp14_DBGBCR0    (DBGBCR0_EL1 * 2)
191 #define cp14_DBGBVR0    (DBGBVR0_EL1 * 2)
192 #define cp14_DBGBXVR0   (cp14_DBGBVR0 + 1)
193 #define cp14_DBGWCR0    (DBGWCR0_EL1 * 2)
194 #define cp14_DBGWVR0    (DBGWVR0_EL1 * 2)
195 #define cp14_DBGDCCINT  (MDCCINT_EL1 * 2)
196 
197 #define NR_COPRO_REGS   (NR_SYS_REGS * 2)
198 
199 struct kvm_cpu_context {
200         struct kvm_regs gp_regs;
201         union {
202                 u64 sys_regs[NR_SYS_REGS];
203                 u32 copro[NR_COPRO_REGS];
204         };
205 
206         struct kvm_vcpu *__hyp_running_vcpu;
207 };
208 
209 typedef struct kvm_cpu_context kvm_cpu_context_t;
210 
211 struct kvm_vcpu_arch {
212         struct kvm_cpu_context ctxt;
213 
214         /* HYP configuration */
215         u64 hcr_el2;
216         u32 mdcr_el2;
217 
218         /* Exception Information */
219         struct kvm_vcpu_fault_info fault;
220 
221         /* State of various workarounds, see kvm_asm.h for bit assignment */
222         u64 workaround_flags;
223 
224         /* Miscellaneous vcpu state flags */
225         u64 flags;
226 
227         /*
228          * We maintain more than a single set of debug registers to support
229          * debugging the guest from the host and to maintain separate host and
230          * guest state during world switches. vcpu_debug_state are the debug
231          * registers of the vcpu as the guest sees them.  host_debug_state are
232          * the host registers which are saved and restored during
233          * world switches. external_debug_state contains the debug
234          * values we want to debug the guest. This is set via the
235          * KVM_SET_GUEST_DEBUG ioctl.
236          *
237          * debug_ptr points to the set of debug registers that should be loaded
238          * onto the hardware when running the guest.
239          */
240         struct kvm_guest_debug_arch *debug_ptr;
241         struct kvm_guest_debug_arch vcpu_debug_state;
242         struct kvm_guest_debug_arch external_debug_state;
243 
244         /* Pointer to host CPU context */
245         kvm_cpu_context_t *host_cpu_context;
246 
247         struct thread_info *host_thread_info;   /* hyp VA */
248         struct user_fpsimd_state *host_fpsimd_state;    /* hyp VA */
249 
250         struct {
251                 /* {Break,watch}point registers */
252                 struct kvm_guest_debug_arch regs;
253                 /* Statistical profiling extension */
254                 u64 pmscr_el1;
255         } host_debug_state;
256 
257         /* VGIC state */
258         struct vgic_cpu vgic_cpu;
259         struct arch_timer_cpu timer_cpu;
260         struct kvm_pmu pmu;
261 
262         /*
263          * Anything that is not used directly from assembly code goes
264          * here.
265          */
266 
267         /*
268          * Guest registers we preserve during guest debugging.
269          *
270          * These shadow registers are updated by the kvm_handle_sys_reg
271          * trap handler if the guest accesses or updates them while we
272          * are using guest debug.
273          */
274         struct {
275                 u32     mdscr_el1;
276         } guest_debug_preserved;
277 
278         /* vcpu power-off state */
279         bool power_off;
280 
281         /* Don't run the guest (internal implementation need) */
282         bool pause;
283 
284         /* IO related fields */
285         struct kvm_decode mmio_decode;
286 
287         /* Cache some mmu pages needed inside spinlock regions */
288         struct kvm_mmu_memory_cache mmu_page_cache;
289 
290         /* Target CPU and feature flags */
291         int target;
292         DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
293 
294         /* Detect first run of a vcpu */
295         bool has_run_once;
296 
297         /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
298         u64 vsesr_el2;
299 
300         /* True when deferrable sysregs are loaded on the physical CPU,
301          * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */
302         bool sysregs_loaded_on_cpu;
303 };
304 
305 /* vcpu_arch flags field values: */
306 #define KVM_ARM64_DEBUG_DIRTY           (1 << 0)
307 #define KVM_ARM64_FP_ENABLED            (1 << 1) /* guest FP regs loaded */
308 #define KVM_ARM64_FP_HOST               (1 << 2) /* host FP regs loaded */
309 #define KVM_ARM64_HOST_SVE_IN_USE       (1 << 3) /* backup for host TIF_SVE */
310 #define KVM_ARM64_HOST_SVE_ENABLED      (1 << 4) /* SVE enabled for EL0 */
311 
312 #define vcpu_gp_regs(v)         (&(v)->arch.ctxt.gp_regs)
313 
314 /*
315  * Only use __vcpu_sys_reg if you know you want the memory backed version of a
316  * register, and not the one most recently accessed by a running VCPU.  For
317  * example, for userspace access or for system registers that are never context
318  * switched, but only emulated.
319  */
320 #define __vcpu_sys_reg(v,r)     ((v)->arch.ctxt.sys_regs[(r)])
321 
322 u64 vcpu_read_sys_reg(struct kvm_vcpu *vcpu, int reg);
323 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
324 
325 /*
326  * CP14 and CP15 live in the same array, as they are backed by the
327  * same system registers.
328  */
329 #define vcpu_cp14(v,r)          ((v)->arch.ctxt.copro[(r)])
330 #define vcpu_cp15(v,r)          ((v)->arch.ctxt.copro[(r)])
331 
332 struct kvm_vm_stat {
333         ulong remote_tlb_flush;
334 };
335 
336 struct kvm_vcpu_stat {
337         u64 halt_successful_poll;
338         u64 halt_attempted_poll;
339         u64 halt_poll_invalid;
340         u64 halt_wakeup;
341         u64 hvc_exit_stat;
342         u64 wfe_exit_stat;
343         u64 wfi_exit_stat;
344         u64 mmio_exit_user;
345         u64 mmio_exit_kernel;
346         u64 exits;
347 };
348 
349 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
350 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
351 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
352 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
353 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
354 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
355                               struct kvm_vcpu_events *events);
356 
357 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
358                               struct kvm_vcpu_events *events);
359 
360 #define KVM_ARCH_WANT_MMU_NOTIFIER
361 int kvm_unmap_hva_range(struct kvm *kvm,
362                         unsigned long start, unsigned long end);
363 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
364 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
365 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
366 
367 struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
368 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
369 void kvm_arm_halt_guest(struct kvm *kvm);
370 void kvm_arm_resume_guest(struct kvm *kvm);
371 
372 u64 __kvm_call_hyp(void *hypfn, ...);
373 #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)
374 
375 void force_vm_exit(const cpumask_t *mask);
376 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
377 
378 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
379                 int exception_index);
380 void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run,
381                        int exception_index);
382 
383 int kvm_perf_init(void);
384 int kvm_perf_teardown(void);
385 
386 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
387 
388 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
389 
390 DECLARE_PER_CPU(kvm_cpu_context_t, kvm_host_cpu_state);
391 
392 void __kvm_enable_ssbs(void);
393 
394 static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
395                                        unsigned long hyp_stack_ptr,
396                                        unsigned long vector_ptr)
397 {
398         /*
399          * Calculate the raw per-cpu offset without a translation from the
400          * kernel's mapping to the linear mapping, and store it in tpidr_el2
401          * so that we can use adr_l to access per-cpu variables in EL2.
402          */
403         u64 tpidr_el2 = ((u64)this_cpu_ptr(&kvm_host_cpu_state) -
404                          (u64)kvm_ksym_ref(kvm_host_cpu_state));
405 
406         /*
407          * Call initialization code, and switch to the full blown HYP code.
408          * If the cpucaps haven't been finalized yet, something has gone very
409          * wrong, and hyp will crash and burn when it uses any
410          * cpus_have_const_cap() wrapper.
411          */
412         BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
413         __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr, tpidr_el2);
414 
415         /*
416          * Disabling SSBD on a non-VHE system requires us to enable SSBS
417          * at EL2.
418          */
419         if (!has_vhe() && this_cpu_has_cap(ARM64_SSBS) &&
420             arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
421                 kvm_call_hyp(__kvm_enable_ssbs);
422         }
423 }
424 
425 static inline bool kvm_arch_check_sve_has_vhe(void)
426 {
427         /*
428          * The Arm architecture specifies that implementation of SVE
429          * requires VHE also to be implemented.  The KVM code for arm64
430          * relies on this when SVE is present:
431          */
432         if (system_supports_sve())
433                 return has_vhe();
434         else
435                 return true;
436 }
437 
438 static inline void kvm_arch_hardware_unsetup(void) {}
439 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
440 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
441 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
442 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
443 
444 void kvm_arm_init_debug(void);
445 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
446 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
447 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
448 bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu, struct kvm_run *run);
449 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
450                                struct kvm_device_attr *attr);
451 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
452                                struct kvm_device_attr *attr);
453 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
454                                struct kvm_device_attr *attr);
455 
456 static inline void __cpu_init_stage2(void) {}
457 
458 /* Guest/host FPSIMD coordination helpers */
459 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
460 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
461 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
462 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
463 
464 #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */
465 static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
466 {
467         return kvm_arch_vcpu_run_map_fp(vcpu);
468 }
469 #endif
470 
471 static inline void kvm_arm_vhe_guest_enter(void)
472 {
473         local_daif_mask();
474 }
475 
476 static inline void kvm_arm_vhe_guest_exit(void)
477 {
478         local_daif_restore(DAIF_PROCCTX_NOIRQ);
479 
480         /*
481          * When we exit from the guest we change a number of CPU configuration
482          * parameters, such as traps.  Make sure these changes take effect
483          * before running the host or additional guests.
484          */
485         isb();
486 }
487 
488 static inline bool kvm_arm_harden_branch_predictor(void)
489 {
490         return cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR);
491 }
492 
493 #define KVM_SSBD_UNKNOWN                -1
494 #define KVM_SSBD_FORCE_DISABLE          0
495 #define KVM_SSBD_KERNEL         1
496 #define KVM_SSBD_FORCE_ENABLE           2
497 #define KVM_SSBD_MITIGATED              3
498 
499 static inline int kvm_arm_have_ssbd(void)
500 {
501         switch (arm64_get_ssbd_state()) {
502         case ARM64_SSBD_FORCE_DISABLE:
503                 return KVM_SSBD_FORCE_DISABLE;
504         case ARM64_SSBD_KERNEL:
505                 return KVM_SSBD_KERNEL;
506         case ARM64_SSBD_FORCE_ENABLE:
507                 return KVM_SSBD_FORCE_ENABLE;
508         case ARM64_SSBD_MITIGATED:
509                 return KVM_SSBD_MITIGATED;
510         case ARM64_SSBD_UNKNOWN:
511         default:
512                 return KVM_SSBD_UNKNOWN;
513         }
514 }
515 
516 void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu);
517 void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu);
518 
519 void kvm_set_ipa_limit(void);
520 
521 #define __KVM_HAVE_ARCH_VM_ALLOC
522 struct kvm *kvm_arch_alloc_vm(void);
523 void kvm_arch_free_vm(struct kvm *kvm);
524 
525 int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type);
526 
527 #endif /* __ARM64_KVM_HOST_H__ */
528 

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