~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/arch/arm64/kernel/perf_event.c

Version: ~ [ linux-5.12-rc1 ] ~ [ linux-5.11.2 ] ~ [ linux-5.10.19 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.101 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.177 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.222 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.258 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.258 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.18.140 ] ~ [ linux-3.16.85 ] ~ [ linux-3.14.79 ] ~ [ linux-3.12.74 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * PMU support
  3  *
  4  * Copyright (C) 2012 ARM Limited
  5  * Author: Will Deacon <will.deacon@arm.com>
  6  *
  7  * This code is based heavily on the ARMv7 perf event code.
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 20  */
 21 
 22 #include <asm/irq_regs.h>
 23 #include <asm/perf_event.h>
 24 #include <asm/sysreg.h>
 25 #include <asm/virt.h>
 26 
 27 #include <linux/acpi.h>
 28 #include <linux/of.h>
 29 #include <linux/perf/arm_pmu.h>
 30 #include <linux/platform_device.h>
 31 
 32 /*
 33  * ARMv8 PMUv3 Performance Events handling code.
 34  * Common event types (some are defined in asm/perf_event.h).
 35  */
 36 
 37 /* At least one of the following is required. */
 38 #define ARMV8_PMUV3_PERFCTR_INST_RETIRED                        0x08
 39 #define ARMV8_PMUV3_PERFCTR_INST_SPEC                           0x1B
 40 
 41 /* Common architectural events. */
 42 #define ARMV8_PMUV3_PERFCTR_LD_RETIRED                          0x06
 43 #define ARMV8_PMUV3_PERFCTR_ST_RETIRED                          0x07
 44 #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN                           0x09
 45 #define ARMV8_PMUV3_PERFCTR_EXC_RETURN                          0x0A
 46 #define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED                   0x0B
 47 #define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED                    0x0C
 48 #define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED                    0x0D
 49 #define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED                   0x0E
 50 #define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED              0x0F
 51 #define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED                  0x1C
 52 #define ARMV8_PMUV3_PERFCTR_CHAIN                               0x1E
 53 #define ARMV8_PMUV3_PERFCTR_BR_RETIRED                          0x21
 54 
 55 /* Common microarchitectural events. */
 56 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL                    0x01
 57 #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL                      0x02
 58 #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL                      0x05
 59 #define ARMV8_PMUV3_PERFCTR_MEM_ACCESS                          0x13
 60 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE                           0x14
 61 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB                        0x15
 62 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE                           0x16
 63 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL                    0x17
 64 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB                        0x18
 65 #define ARMV8_PMUV3_PERFCTR_BUS_ACCESS                          0x19
 66 #define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR                        0x1A
 67 #define ARMV8_PMUV3_PERFCTR_BUS_CYCLES                          0x1D
 68 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE                  0x1F
 69 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE                  0x20
 70 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED                 0x22
 71 #define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND                      0x23
 72 #define ARMV8_PMUV3_PERFCTR_STALL_BACKEND                       0x24
 73 #define ARMV8_PMUV3_PERFCTR_L1D_TLB                             0x25
 74 #define ARMV8_PMUV3_PERFCTR_L1I_TLB                             0x26
 75 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE                           0x27
 76 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL                    0x28
 77 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE                  0x29
 78 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL                    0x2A
 79 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE                           0x2B
 80 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB                        0x2C
 81 #define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL                      0x2D
 82 #define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL                      0x2E
 83 #define ARMV8_PMUV3_PERFCTR_L2D_TLB                             0x2F
 84 #define ARMV8_PMUV3_PERFCTR_L2I_TLB                             0x30
 85 
 86 /* ARMv8 recommended implementation defined event types */
 87 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD                       0x40
 88 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR                       0x41
 89 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD                0x42
 90 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR                0x43
 91 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER             0x44
 92 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER             0x45
 93 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM                0x46
 94 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN                 0x47
 95 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL                    0x48
 96 
 97 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD                  0x4C
 98 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR                  0x4D
 99 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD                         0x4E
100 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR                         0x4F
101 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD                       0x50
102 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR                       0x51
103 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD                0x52
104 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR                0x53
105 
106 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM                0x56
107 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN                 0x57
108 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL                    0x58
109 
110 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD                  0x5C
111 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR                  0x5D
112 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD                         0x5E
113 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR                         0x5F
114 
115 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD                      0x60
116 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR                      0x61
117 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED                  0x62
118 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED              0x63
119 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL                  0x64
120 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH                  0x65
121 
122 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD                      0x66
123 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR                      0x67
124 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC                  0x68
125 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC                  0x69
126 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC                0x6A
127 
128 #define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC                         0x6C
129 #define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC                    0x6D
130 #define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC                    0x6E
131 #define ARMV8_IMPDEF_PERFCTR_STREX_SPEC                         0x6F
132 #define ARMV8_IMPDEF_PERFCTR_LD_SPEC                            0x70
133 #define ARMV8_IMPDEF_PERFCTR_ST_SPEC                            0x71
134 #define ARMV8_IMPDEF_PERFCTR_LDST_SPEC                          0x72
135 #define ARMV8_IMPDEF_PERFCTR_DP_SPEC                            0x73
136 #define ARMV8_IMPDEF_PERFCTR_ASE_SPEC                           0x74
137 #define ARMV8_IMPDEF_PERFCTR_VFP_SPEC                           0x75
138 #define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC                      0x76
139 #define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC                        0x77
140 #define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC                      0x78
141 #define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC                     0x79
142 #define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC                   0x7A
143 
144 #define ARMV8_IMPDEF_PERFCTR_ISB_SPEC                           0x7C
145 #define ARMV8_IMPDEF_PERFCTR_DSB_SPEC                           0x7D
146 #define ARMV8_IMPDEF_PERFCTR_DMB_SPEC                           0x7E
147 
148 #define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF                          0x81
149 #define ARMV8_IMPDEF_PERFCTR_EXC_SVC                            0x82
150 #define ARMV8_IMPDEF_PERFCTR_EXC_PABORT                         0x83
151 #define ARMV8_IMPDEF_PERFCTR_EXC_DABORT                         0x84
152 
153 #define ARMV8_IMPDEF_PERFCTR_EXC_IRQ                            0x86
154 #define ARMV8_IMPDEF_PERFCTR_EXC_FIQ                            0x87
155 #define ARMV8_IMPDEF_PERFCTR_EXC_SMC                            0x88
156 
157 #define ARMV8_IMPDEF_PERFCTR_EXC_HVC                            0x8A
158 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT                    0x8B
159 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT                    0x8C
160 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER                     0x8D
161 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ                       0x8E
162 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ                       0x8F
163 #define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC                         0x90
164 #define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC                         0x91
165 
166 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD                       0xA0
167 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR                       0xA1
168 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD                0xA2
169 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR                0xA3
170 
171 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM                0xA6
172 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN                 0xA7
173 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL                    0xA8
174 
175 /* ARMv8 Cortex-A53 specific event types. */
176 #define ARMV8_A53_PERFCTR_PREF_LINEFILL                         0xC2
177 
178 /* ARMv8 Cavium ThunderX specific event types. */
179 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST                 0xE9
180 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS             0xEA
181 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS               0xEB
182 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS             0xEC
183 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS               0xED
184 
185 /* PMUv3 HW events mapping. */
186 
187 /*
188  * ARMv8 Architectural defined events, not all of these may
189  * be supported on any given implementation. Undefined events will
190  * be disabled at run-time.
191  */
192 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
193         PERF_MAP_ALL_UNSUPPORTED,
194         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
195         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
196         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
197         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
198         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
199         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
200         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
201         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
202         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
203 };
204 
205 /* ARM Cortex-A53 HW events mapping. */
206 static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = {
207         PERF_MAP_ALL_UNSUPPORTED,
208         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
209         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
210         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
211         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
212         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
213         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
214         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
215 };
216 
217 /* ARM Cortex-A57 and Cortex-A72 events mapping. */
218 static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = {
219         PERF_MAP_ALL_UNSUPPORTED,
220         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
221         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
222         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
223         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
224         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
225         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
226 };
227 
228 static const unsigned armv8_thunder_perf_map[PERF_COUNT_HW_MAX] = {
229         PERF_MAP_ALL_UNSUPPORTED,
230         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
231         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
232         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
233         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
234         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
235         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
236         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
237         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
238 };
239 
240 /* Broadcom Vulcan events mapping */
241 static const unsigned armv8_vulcan_perf_map[PERF_COUNT_HW_MAX] = {
242         PERF_MAP_ALL_UNSUPPORTED,
243         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
244         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
245         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
246         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
247         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_BR_RETIRED,
248         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
249         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
250         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
251         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
252 };
253 
254 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
255                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
256                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
257         PERF_CACHE_MAP_ALL_UNSUPPORTED,
258 
259         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
260         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
261         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
262         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
263 
264         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
265         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
266 
267         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
268         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
269 
270         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
271         [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
272 
273         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
274         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
275         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
276         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
277 };
278 
279 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
280                                               [PERF_COUNT_HW_CACHE_OP_MAX]
281                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
282         PERF_CACHE_MAP_ALL_UNSUPPORTED,
283 
284         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
285         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
286         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
287         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
288         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
289 
290         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
291         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
292 
293         [C(LL)][C(OP_READ)][C(RESULT_ACCESS)]   = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
294         [C(LL)][C(OP_READ)][C(RESULT_MISS)]     = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
295         [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
296         [C(LL)][C(OP_WRITE)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
297 
298         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
299         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
300 
301         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
302         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
303         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
304         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
305 };
306 
307 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
308                                               [PERF_COUNT_HW_CACHE_OP_MAX]
309                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
310         PERF_CACHE_MAP_ALL_UNSUPPORTED,
311 
312         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
313         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
314         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
315         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
316 
317         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
318         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
319 
320         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
321         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
322 
323         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
324 
325         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
326         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
327         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
328         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
329 };
330 
331 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
332                                                    [PERF_COUNT_HW_CACHE_OP_MAX]
333                                                    [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
334         PERF_CACHE_MAP_ALL_UNSUPPORTED,
335 
336         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
337         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
338         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
339         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
340         [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
341         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
342 
343         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
344         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
345         [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
346         [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
347 
348         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
349         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
350         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
351         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
352 
353         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
354 
355         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
356         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
357         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
358         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
359 };
360 
361 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
362                                               [PERF_COUNT_HW_CACHE_OP_MAX]
363                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
364         PERF_CACHE_MAP_ALL_UNSUPPORTED,
365 
366         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
367         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
368         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
369         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
370 
371         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
372         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
373 
374         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
375         [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
376 
377         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
378         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
379         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
380         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
381 
382         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
383         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
384         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
385         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
386 
387         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
388         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
389 };
390 
391 static ssize_t
392 armv8pmu_events_sysfs_show(struct device *dev,
393                            struct device_attribute *attr, char *page)
394 {
395         struct perf_pmu_events_attr *pmu_attr;
396 
397         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
398 
399         return sprintf(page, "event=0x%03llx\n", pmu_attr->id);
400 }
401 
402 #define ARMV8_EVENT_ATTR_RESOLVE(m) #m
403 #define ARMV8_EVENT_ATTR(name, config) \
404         PMU_EVENT_ATTR(name, armv8_event_attr_##name, \
405                        config, armv8pmu_events_sysfs_show)
406 
407 ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR);
408 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL);
409 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL);
410 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL);
411 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE);
412 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL);
413 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED);
414 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED);
415 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED);
416 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);
417 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN);
418 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED);
419 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED);
420 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED);
421 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED);
422 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED);
423 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED);
424 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES);
425 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED);
426 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);
427 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE);
428 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB);
429 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE);
430 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL);
431 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB);
432 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);
433 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR);
434 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC);
435 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED);
436 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);
437 /* Don't expose the chain event in /sys, since it's useless in isolation */
438 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);
439 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);
440 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);
441 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED);
442 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND);
443 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND);
444 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB);
445 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB);
446 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE);
447 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL);
448 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE);
449 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);
450 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);
451 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);
452 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);
453 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL);
454 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);
455 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB);
456 
457 static struct attribute *armv8_pmuv3_event_attrs[] = {
458         &armv8_event_attr_sw_incr.attr.attr,
459         &armv8_event_attr_l1i_cache_refill.attr.attr,
460         &armv8_event_attr_l1i_tlb_refill.attr.attr,
461         &armv8_event_attr_l1d_cache_refill.attr.attr,
462         &armv8_event_attr_l1d_cache.attr.attr,
463         &armv8_event_attr_l1d_tlb_refill.attr.attr,
464         &armv8_event_attr_ld_retired.attr.attr,
465         &armv8_event_attr_st_retired.attr.attr,
466         &armv8_event_attr_inst_retired.attr.attr,
467         &armv8_event_attr_exc_taken.attr.attr,
468         &armv8_event_attr_exc_return.attr.attr,
469         &armv8_event_attr_cid_write_retired.attr.attr,
470         &armv8_event_attr_pc_write_retired.attr.attr,
471         &armv8_event_attr_br_immed_retired.attr.attr,
472         &armv8_event_attr_br_return_retired.attr.attr,
473         &armv8_event_attr_unaligned_ldst_retired.attr.attr,
474         &armv8_event_attr_br_mis_pred.attr.attr,
475         &armv8_event_attr_cpu_cycles.attr.attr,
476         &armv8_event_attr_br_pred.attr.attr,
477         &armv8_event_attr_mem_access.attr.attr,
478         &armv8_event_attr_l1i_cache.attr.attr,
479         &armv8_event_attr_l1d_cache_wb.attr.attr,
480         &armv8_event_attr_l2d_cache.attr.attr,
481         &armv8_event_attr_l2d_cache_refill.attr.attr,
482         &armv8_event_attr_l2d_cache_wb.attr.attr,
483         &armv8_event_attr_bus_access.attr.attr,
484         &armv8_event_attr_memory_error.attr.attr,
485         &armv8_event_attr_inst_spec.attr.attr,
486         &armv8_event_attr_ttbr_write_retired.attr.attr,
487         &armv8_event_attr_bus_cycles.attr.attr,
488         &armv8_event_attr_l1d_cache_allocate.attr.attr,
489         &armv8_event_attr_l2d_cache_allocate.attr.attr,
490         &armv8_event_attr_br_retired.attr.attr,
491         &armv8_event_attr_br_mis_pred_retired.attr.attr,
492         &armv8_event_attr_stall_frontend.attr.attr,
493         &armv8_event_attr_stall_backend.attr.attr,
494         &armv8_event_attr_l1d_tlb.attr.attr,
495         &armv8_event_attr_l1i_tlb.attr.attr,
496         &armv8_event_attr_l2i_cache.attr.attr,
497         &armv8_event_attr_l2i_cache_refill.attr.attr,
498         &armv8_event_attr_l3d_cache_allocate.attr.attr,
499         &armv8_event_attr_l3d_cache_refill.attr.attr,
500         &armv8_event_attr_l3d_cache.attr.attr,
501         &armv8_event_attr_l3d_cache_wb.attr.attr,
502         &armv8_event_attr_l2d_tlb_refill.attr.attr,
503         &armv8_event_attr_l2i_tlb_refill.attr.attr,
504         &armv8_event_attr_l2d_tlb.attr.attr,
505         &armv8_event_attr_l2i_tlb.attr.attr,
506         NULL,
507 };
508 
509 static umode_t
510 armv8pmu_event_attr_is_visible(struct kobject *kobj,
511                                struct attribute *attr, int unused)
512 {
513         struct device *dev = kobj_to_dev(kobj);
514         struct pmu *pmu = dev_get_drvdata(dev);
515         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
516         struct perf_pmu_events_attr *pmu_attr;
517 
518         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
519 
520         if (test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
521                 return attr->mode;
522 
523         return 0;
524 }
525 
526 static struct attribute_group armv8_pmuv3_events_attr_group = {
527         .name = "events",
528         .attrs = armv8_pmuv3_event_attrs,
529         .is_visible = armv8pmu_event_attr_is_visible,
530 };
531 
532 PMU_FORMAT_ATTR(event, "config:0-15");
533 
534 static struct attribute *armv8_pmuv3_format_attrs[] = {
535         &format_attr_event.attr,
536         NULL,
537 };
538 
539 static struct attribute_group armv8_pmuv3_format_attr_group = {
540         .name = "format",
541         .attrs = armv8_pmuv3_format_attrs,
542 };
543 
544 /*
545  * Perf Events' indices
546  */
547 #define ARMV8_IDX_CYCLE_COUNTER 0
548 #define ARMV8_IDX_COUNTER0      1
549 #define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \
550         (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
551 
552 /*
553  * ARMv8 low level PMU access
554  */
555 
556 /*
557  * Perf Event to low level counters mapping
558  */
559 #define ARMV8_IDX_TO_COUNTER(x) \
560         (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
561 
562 static inline u32 armv8pmu_pmcr_read(void)
563 {
564         return read_sysreg(pmcr_el0);
565 }
566 
567 static inline void armv8pmu_pmcr_write(u32 val)
568 {
569         val &= ARMV8_PMU_PMCR_MASK;
570         isb();
571         write_sysreg(val, pmcr_el0);
572 }
573 
574 static inline int armv8pmu_has_overflowed(u32 pmovsr)
575 {
576         return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
577 }
578 
579 static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx)
580 {
581         return idx >= ARMV8_IDX_CYCLE_COUNTER &&
582                 idx <= ARMV8_IDX_COUNTER_LAST(cpu_pmu);
583 }
584 
585 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
586 {
587         return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
588 }
589 
590 static inline int armv8pmu_select_counter(int idx)
591 {
592         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
593         write_sysreg(counter, pmselr_el0);
594         isb();
595 
596         return idx;
597 }
598 
599 static inline u32 armv8pmu_read_counter(struct perf_event *event)
600 {
601         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
602         struct hw_perf_event *hwc = &event->hw;
603         int idx = hwc->idx;
604         u32 value = 0;
605 
606         if (!armv8pmu_counter_valid(cpu_pmu, idx))
607                 pr_err("CPU%u reading wrong counter %d\n",
608                         smp_processor_id(), idx);
609         else if (idx == ARMV8_IDX_CYCLE_COUNTER)
610                 value = read_sysreg(pmccntr_el0);
611         else if (armv8pmu_select_counter(idx) == idx)
612                 value = read_sysreg(pmxevcntr_el0);
613 
614         return value;
615 }
616 
617 static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
618 {
619         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
620         struct hw_perf_event *hwc = &event->hw;
621         int idx = hwc->idx;
622 
623         if (!armv8pmu_counter_valid(cpu_pmu, idx))
624                 pr_err("CPU%u writing wrong counter %d\n",
625                         smp_processor_id(), idx);
626         else if (idx == ARMV8_IDX_CYCLE_COUNTER) {
627                 /*
628                  * Set the upper 32bits as this is a 64bit counter but we only
629                  * count using the lower 32bits and we want an interrupt when
630                  * it overflows.
631                  */
632                 u64 value64 = 0xffffffff00000000ULL | value;
633 
634                 write_sysreg(value64, pmccntr_el0);
635         } else if (armv8pmu_select_counter(idx) == idx)
636                 write_sysreg(value, pmxevcntr_el0);
637 }
638 
639 static inline void armv8pmu_write_evtype(int idx, u32 val)
640 {
641         if (armv8pmu_select_counter(idx) == idx) {
642                 val &= ARMV8_PMU_EVTYPE_MASK;
643                 write_sysreg(val, pmxevtyper_el0);
644         }
645 }
646 
647 static inline int armv8pmu_enable_counter(int idx)
648 {
649         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
650         write_sysreg(BIT(counter), pmcntenset_el0);
651         return idx;
652 }
653 
654 static inline int armv8pmu_disable_counter(int idx)
655 {
656         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
657         write_sysreg(BIT(counter), pmcntenclr_el0);
658         return idx;
659 }
660 
661 static inline int armv8pmu_enable_intens(int idx)
662 {
663         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
664         write_sysreg(BIT(counter), pmintenset_el1);
665         return idx;
666 }
667 
668 static inline int armv8pmu_disable_intens(int idx)
669 {
670         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
671         write_sysreg(BIT(counter), pmintenclr_el1);
672         isb();
673         /* Clear the overflow flag in case an interrupt is pending. */
674         write_sysreg(BIT(counter), pmovsclr_el0);
675         isb();
676 
677         return idx;
678 }
679 
680 static inline u32 armv8pmu_getreset_flags(void)
681 {
682         u32 value;
683 
684         /* Read */
685         value = read_sysreg(pmovsclr_el0);
686 
687         /* Write to clear flags */
688         value &= ARMV8_PMU_OVSR_MASK;
689         write_sysreg(value, pmovsclr_el0);
690 
691         return value;
692 }
693 
694 static void armv8pmu_enable_event(struct perf_event *event)
695 {
696         unsigned long flags;
697         struct hw_perf_event *hwc = &event->hw;
698         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
699         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
700         int idx = hwc->idx;
701 
702         /*
703          * Enable counter and interrupt, and set the counter to count
704          * the event that we're interested in.
705          */
706         raw_spin_lock_irqsave(&events->pmu_lock, flags);
707 
708         /*
709          * Disable counter
710          */
711         armv8pmu_disable_counter(idx);
712 
713         /*
714          * Set event (if destined for PMNx counters).
715          */
716         armv8pmu_write_evtype(idx, hwc->config_base);
717 
718         /*
719          * Enable interrupt for this counter
720          */
721         armv8pmu_enable_intens(idx);
722 
723         /*
724          * Enable counter
725          */
726         armv8pmu_enable_counter(idx);
727 
728         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
729 }
730 
731 static void armv8pmu_disable_event(struct perf_event *event)
732 {
733         unsigned long flags;
734         struct hw_perf_event *hwc = &event->hw;
735         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
736         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
737         int idx = hwc->idx;
738 
739         /*
740          * Disable counter and interrupt
741          */
742         raw_spin_lock_irqsave(&events->pmu_lock, flags);
743 
744         /*
745          * Disable counter
746          */
747         armv8pmu_disable_counter(idx);
748 
749         /*
750          * Disable interrupt for this counter
751          */
752         armv8pmu_disable_intens(idx);
753 
754         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
755 }
756 
757 static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
758 {
759         u32 pmovsr;
760         struct perf_sample_data data;
761         struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
762         struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
763         struct pt_regs *regs;
764         int idx;
765 
766         /*
767          * Get and reset the IRQ flags
768          */
769         pmovsr = armv8pmu_getreset_flags();
770 
771         /*
772          * Did an overflow occur?
773          */
774         if (!armv8pmu_has_overflowed(pmovsr))
775                 return IRQ_NONE;
776 
777         /*
778          * Handle the counter(s) overflow(s)
779          */
780         regs = get_irq_regs();
781 
782         for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
783                 struct perf_event *event = cpuc->events[idx];
784                 struct hw_perf_event *hwc;
785 
786                 /* Ignore if we don't have an event. */
787                 if (!event)
788                         continue;
789 
790                 /*
791                  * We have a single interrupt for all counters. Check that
792                  * each counter has overflowed before we process it.
793                  */
794                 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
795                         continue;
796 
797                 hwc = &event->hw;
798                 armpmu_event_update(event);
799                 perf_sample_data_init(&data, 0, hwc->last_period);
800                 if (!armpmu_event_set_period(event))
801                         continue;
802 
803                 if (perf_event_overflow(event, &data, regs))
804                         cpu_pmu->disable(event);
805         }
806 
807         /*
808          * Handle the pending perf events.
809          *
810          * Note: this call *must* be run with interrupts disabled. For
811          * platforms that can have the PMU interrupts raised as an NMI, this
812          * will not work.
813          */
814         irq_work_run();
815 
816         return IRQ_HANDLED;
817 }
818 
819 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
820 {
821         unsigned long flags;
822         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
823 
824         raw_spin_lock_irqsave(&events->pmu_lock, flags);
825         /* Enable all counters */
826         armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
827         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
828 }
829 
830 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
831 {
832         unsigned long flags;
833         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
834 
835         raw_spin_lock_irqsave(&events->pmu_lock, flags);
836         /* Disable all counters */
837         armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
838         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
839 }
840 
841 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
842                                   struct perf_event *event)
843 {
844         int idx;
845         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
846         struct hw_perf_event *hwc = &event->hw;
847         unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
848 
849         /* Always place a cycle counter into the cycle counter. */
850         if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
851                 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
852                         return -EAGAIN;
853 
854                 return ARMV8_IDX_CYCLE_COUNTER;
855         }
856 
857         /*
858          * For anything other than a cycle counter, try and use
859          * the events counters
860          */
861         for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
862                 if (!test_and_set_bit(idx, cpuc->used_mask))
863                         return idx;
864         }
865 
866         /* The counters are all in use. */
867         return -EAGAIN;
868 }
869 
870 /*
871  * Add an event filter to a given event. This will only work for PMUv2 PMUs.
872  */
873 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
874                                      struct perf_event_attr *attr)
875 {
876         unsigned long config_base = 0;
877 
878         if (attr->exclude_idle)
879                 return -EPERM;
880 
881         /*
882          * If we're running in hyp mode, then we *are* the hypervisor.
883          * Therefore we ignore exclude_hv in this configuration, since
884          * there's no hypervisor to sample anyway. This is consistent
885          * with other architectures (x86 and Power).
886          */
887         if (is_kernel_in_hyp_mode()) {
888                 if (!attr->exclude_kernel)
889                         config_base |= ARMV8_PMU_INCLUDE_EL2;
890         } else {
891                 if (attr->exclude_kernel)
892                         config_base |= ARMV8_PMU_EXCLUDE_EL1;
893                 if (!attr->exclude_hv)
894                         config_base |= ARMV8_PMU_INCLUDE_EL2;
895         }
896         if (attr->exclude_user)
897                 config_base |= ARMV8_PMU_EXCLUDE_EL0;
898 
899         /*
900          * Install the filter into config_base as this is used to
901          * construct the event type.
902          */
903         event->config_base = config_base;
904 
905         return 0;
906 }
907 
908 static void armv8pmu_reset(void *info)
909 {
910         struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
911         u32 idx, nb_cnt = cpu_pmu->num_events;
912 
913         /* The counter and interrupt enable registers are unknown at reset. */
914         for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
915                 armv8pmu_disable_counter(idx);
916                 armv8pmu_disable_intens(idx);
917         }
918 
919         /*
920          * Initialize & Reset PMNC. Request overflow interrupt for
921          * 64 bit cycle counter but cheat in armv8pmu_write_counter().
922          */
923         armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
924                             ARMV8_PMU_PMCR_LC);
925 }
926 
927 static int armv8_pmuv3_map_event(struct perf_event *event)
928 {
929         int hw_event_id;
930         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
931 
932         hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
933                                        &armv8_pmuv3_perf_cache_map,
934                                        ARMV8_PMU_EVTYPE_EVENT);
935         if (hw_event_id < 0)
936                 return hw_event_id;
937 
938         /* disable micro/arch events not supported by this PMU */
939         if ((hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS) &&
940                 !test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
941                         return -EOPNOTSUPP;
942         }
943 
944         return hw_event_id;
945 }
946 
947 static int armv8_a53_map_event(struct perf_event *event)
948 {
949         return armpmu_map_event(event, &armv8_a53_perf_map,
950                                 &armv8_a53_perf_cache_map,
951                                 ARMV8_PMU_EVTYPE_EVENT);
952 }
953 
954 static int armv8_a57_map_event(struct perf_event *event)
955 {
956         return armpmu_map_event(event, &armv8_a57_perf_map,
957                                 &armv8_a57_perf_cache_map,
958                                 ARMV8_PMU_EVTYPE_EVENT);
959 }
960 
961 static int armv8_thunder_map_event(struct perf_event *event)
962 {
963         return armpmu_map_event(event, &armv8_thunder_perf_map,
964                                 &armv8_thunder_perf_cache_map,
965                                 ARMV8_PMU_EVTYPE_EVENT);
966 }
967 
968 static int armv8_vulcan_map_event(struct perf_event *event)
969 {
970         return armpmu_map_event(event, &armv8_vulcan_perf_map,
971                                 &armv8_vulcan_perf_cache_map,
972                                 ARMV8_PMU_EVTYPE_EVENT);
973 }
974 
975 struct armv8pmu_probe_info {
976         struct arm_pmu *pmu;
977         bool present;
978 };
979 
980 static void __armv8pmu_probe_pmu(void *info)
981 {
982         struct armv8pmu_probe_info *probe = info;
983         struct arm_pmu *cpu_pmu = probe->pmu;
984         u64 dfr0;
985         u32 pmceid[2];
986         int pmuver;
987 
988         dfr0 = read_sysreg(id_aa64dfr0_el1);
989         pmuver = cpuid_feature_extract_signed_field(dfr0,
990                         ID_AA64DFR0_PMUVER_SHIFT);
991         if (pmuver < 1)
992                 return;
993 
994         probe->present = true;
995 
996         /* Read the nb of CNTx counters supported from PMNC */
997         cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
998                 & ARMV8_PMU_PMCR_N_MASK;
999 
1000         /* Add the CPU cycles counter */
1001         cpu_pmu->num_events += 1;
1002 
1003         pmceid[0] = read_sysreg(pmceid0_el0);
1004         pmceid[1] = read_sysreg(pmceid1_el0);
1005 
1006         bitmap_from_u32array(cpu_pmu->pmceid_bitmap,
1007                              ARMV8_PMUV3_MAX_COMMON_EVENTS, pmceid,
1008                              ARRAY_SIZE(pmceid));
1009 }
1010 
1011 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
1012 {
1013         struct armv8pmu_probe_info probe = {
1014                 .pmu = cpu_pmu,
1015                 .present = false,
1016         };
1017         int ret;
1018 
1019         ret = smp_call_function_any(&cpu_pmu->supported_cpus,
1020                                     __armv8pmu_probe_pmu,
1021                                     &probe, 1);
1022         if (ret)
1023                 return ret;
1024 
1025         return probe.present ? 0 : -ENODEV;
1026 }
1027 
1028 static int armv8_pmu_init(struct arm_pmu *cpu_pmu)
1029 {
1030         int ret = armv8pmu_probe_pmu(cpu_pmu);
1031         if (ret)
1032                 return ret;
1033 
1034         cpu_pmu->handle_irq             = armv8pmu_handle_irq,
1035         cpu_pmu->enable                 = armv8pmu_enable_event,
1036         cpu_pmu->disable                = armv8pmu_disable_event,
1037         cpu_pmu->read_counter           = armv8pmu_read_counter,
1038         cpu_pmu->write_counter          = armv8pmu_write_counter,
1039         cpu_pmu->get_event_idx          = armv8pmu_get_event_idx,
1040         cpu_pmu->start                  = armv8pmu_start,
1041         cpu_pmu->stop                   = armv8pmu_stop,
1042         cpu_pmu->reset                  = armv8pmu_reset,
1043         cpu_pmu->max_period             = (1LLU << 32) - 1,
1044         cpu_pmu->set_event_filter       = armv8pmu_set_event_filter;
1045 
1046         return 0;
1047 }
1048 
1049 static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
1050 {
1051         int ret = armv8_pmu_init(cpu_pmu);
1052         if (ret)
1053                 return ret;
1054 
1055         cpu_pmu->name                   = "armv8_pmuv3";
1056         cpu_pmu->map_event              = armv8_pmuv3_map_event;
1057         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1058                 &armv8_pmuv3_events_attr_group;
1059         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1060                 &armv8_pmuv3_format_attr_group;
1061 
1062         return 0;
1063 }
1064 
1065 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1066 {
1067         int ret = armv8_pmu_init(cpu_pmu);
1068         if (ret)
1069                 return ret;
1070 
1071         cpu_pmu->name                   = "armv8_cortex_a53";
1072         cpu_pmu->map_event              = armv8_a53_map_event;
1073         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1074                 &armv8_pmuv3_events_attr_group;
1075         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1076                 &armv8_pmuv3_format_attr_group;
1077 
1078         return 0;
1079 }
1080 
1081 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1082 {
1083         int ret = armv8_pmu_init(cpu_pmu);
1084         if (ret)
1085                 return ret;
1086 
1087         cpu_pmu->name                   = "armv8_cortex_a57";
1088         cpu_pmu->map_event              = armv8_a57_map_event;
1089         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1090                 &armv8_pmuv3_events_attr_group;
1091         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1092                 &armv8_pmuv3_format_attr_group;
1093 
1094         return 0;
1095 }
1096 
1097 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1098 {
1099         int ret = armv8_pmu_init(cpu_pmu);
1100         if (ret)
1101                 return ret;
1102 
1103         cpu_pmu->name                   = "armv8_cortex_a72";
1104         cpu_pmu->map_event              = armv8_a57_map_event;
1105         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1106                 &armv8_pmuv3_events_attr_group;
1107         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1108                 &armv8_pmuv3_format_attr_group;
1109 
1110         return 0;
1111 }
1112 
1113 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1114 {
1115         int ret = armv8_pmu_init(cpu_pmu);
1116         if (ret)
1117                 return ret;
1118 
1119         cpu_pmu->name                   = "armv8_cavium_thunder";
1120         cpu_pmu->map_event              = armv8_thunder_map_event;
1121         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1122                 &armv8_pmuv3_events_attr_group;
1123         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1124                 &armv8_pmuv3_format_attr_group;
1125 
1126         return 0;
1127 }
1128 
1129 static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1130 {
1131         int ret = armv8_pmu_init(cpu_pmu);
1132         if (ret)
1133                 return ret;
1134 
1135         cpu_pmu->name                   = "armv8_brcm_vulcan";
1136         cpu_pmu->map_event              = armv8_vulcan_map_event;
1137         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1138                 &armv8_pmuv3_events_attr_group;
1139         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1140                 &armv8_pmuv3_format_attr_group;
1141 
1142         return 0;
1143 }
1144 
1145 static const struct of_device_id armv8_pmu_of_device_ids[] = {
1146         {.compatible = "arm,armv8-pmuv3",       .data = armv8_pmuv3_init},
1147         {.compatible = "arm,cortex-a53-pmu",    .data = armv8_a53_pmu_init},
1148         {.compatible = "arm,cortex-a57-pmu",    .data = armv8_a57_pmu_init},
1149         {.compatible = "arm,cortex-a72-pmu",    .data = armv8_a72_pmu_init},
1150         {.compatible = "cavium,thunder-pmu",    .data = armv8_thunder_pmu_init},
1151         {.compatible = "brcm,vulcan-pmu",       .data = armv8_vulcan_pmu_init},
1152         {},
1153 };
1154 
1155 static int armv8_pmu_device_probe(struct platform_device *pdev)
1156 {
1157         return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
1158 }
1159 
1160 static struct platform_driver armv8_pmu_driver = {
1161         .driver         = {
1162                 .name   = ARMV8_PMU_PDEV_NAME,
1163                 .of_match_table = armv8_pmu_of_device_ids,
1164         },
1165         .probe          = armv8_pmu_device_probe,
1166 };
1167 
1168 static int __init armv8_pmu_driver_init(void)
1169 {
1170         if (acpi_disabled)
1171                 return platform_driver_register(&armv8_pmu_driver);
1172         else
1173                 return arm_pmu_acpi_probe(armv8_pmuv3_init);
1174 }
1175 device_initcall(armv8_pmu_driver_init)
1176 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp