1 /*
2 * Based on arch/arm/kernel/setup.c
3 *
4 * Copyright (C) 1995-2001 Russell King
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <linux/acpi.h>
21 #include <linux/export.h>
22 #include <linux/kernel.h>
23 #include <linux/stddef.h>
24 #include <linux/ioport.h>
25 #include <linux/delay.h>
26 #include <linux/initrd.h>
27 #include <linux/console.h>
28 #include <linux/cache.h>
29 #include <linux/screen_info.h>
30 #include <linux/init.h>
31 #include <linux/kexec.h>
32 #include <linux/root_dev.h>
33 #include <linux/cpu.h>
34 #include <linux/interrupt.h>
35 #include <linux/smp.h>
36 #include <linux/fs.h>
37 #include <linux/proc_fs.h>
38 #include <linux/memblock.h>
39 #include <linux/of_fdt.h>
40 #include <linux/efi.h>
41 #include <linux/psci.h>
42 #include <linux/sched/task.h>
43 #include <linux/mm.h>
44
45 #include <asm/acpi.h>
46 #include <asm/fixmap.h>
47 #include <asm/cpu.h>
48 #include <asm/cputype.h>
49 #include <asm/daifflags.h>
50 #include <asm/elf.h>
51 #include <asm/cpufeature.h>
52 #include <asm/cpu_ops.h>
53 #include <asm/kasan.h>
54 #include <asm/numa.h>
55 #include <asm/sections.h>
56 #include <asm/setup.h>
57 #include <asm/smp_plat.h>
58 #include <asm/cacheflush.h>
59 #include <asm/tlbflush.h>
60 #include <asm/traps.h>
61 #include <asm/memblock.h>
62 #include <asm/efi.h>
63 #include <asm/xen/hypervisor.h>
64 #include <asm/mmu_context.h>
65
66 static int num_standard_resources;
67 static struct resource *standard_resources;
68
69 phys_addr_t __fdt_pointer __initdata;
70
71 /*
72 * Standard memory resources
73 */
74 static struct resource mem_res[] = {
75 {
76 .name = "Kernel code",
77 .start = 0,
78 .end = 0,
79 .flags = IORESOURCE_SYSTEM_RAM
80 },
81 {
82 .name = "Kernel data",
83 .start = 0,
84 .end = 0,
85 .flags = IORESOURCE_SYSTEM_RAM
86 }
87 };
88
89 #define kernel_code mem_res[0]
90 #define kernel_data mem_res[1]
91
92 /*
93 * The recorded values of x0 .. x3 upon kernel entry.
94 */
95 u64 __cacheline_aligned boot_args[4];
96
97 void __init smp_setup_processor_id(void)
98 {
99 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
100 cpu_logical_map(0) = mpidr;
101
102 /*
103 * clear __my_cpu_offset on boot CPU to avoid hang caused by
104 * using percpu variable early, for example, lockdep will
105 * access percpu variable inside lock_release
106 */
107 set_my_cpu_offset(0);
108 pr_info("Booting Linux on physical CPU 0x%010lx [0x%08x]\n",
109 (unsigned long)mpidr, read_cpuid_id());
110 }
111
112 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
113 {
114 return phys_id == cpu_logical_map(cpu);
115 }
116
117 struct mpidr_hash mpidr_hash;
118 /**
119 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
120 * level in order to build a linear index from an
121 * MPIDR value. Resulting algorithm is a collision
122 * free hash carried out through shifting and ORing
123 */
124 static void __init smp_build_mpidr_hash(void)
125 {
126 u32 i, affinity, fs[4], bits[4], ls;
127 u64 mask = 0;
128 /*
129 * Pre-scan the list of MPIDRS and filter out bits that do
130 * not contribute to affinity levels, ie they never toggle.
131 */
132 for_each_possible_cpu(i)
133 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
134 pr_debug("mask of set bits %#llx\n", mask);
135 /*
136 * Find and stash the last and first bit set at all affinity levels to
137 * check how many bits are required to represent them.
138 */
139 for (i = 0; i < 4; i++) {
140 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
141 /*
142 * Find the MSB bit and LSB bits position
143 * to determine how many bits are required
144 * to express the affinity level.
145 */
146 ls = fls(affinity);
147 fs[i] = affinity ? ffs(affinity) - 1 : 0;
148 bits[i] = ls - fs[i];
149 }
150 /*
151 * An index can be created from the MPIDR_EL1 by isolating the
152 * significant bits at each affinity level and by shifting
153 * them in order to compress the 32 bits values space to a
154 * compressed set of values. This is equivalent to hashing
155 * the MPIDR_EL1 through shifting and ORing. It is a collision free
156 * hash though not minimal since some levels might contain a number
157 * of CPUs that is not an exact power of 2 and their bit
158 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
159 */
160 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
161 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
162 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
163 (bits[1] + bits[0]);
164 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
165 fs[3] - (bits[2] + bits[1] + bits[0]);
166 mpidr_hash.mask = mask;
167 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
168 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
169 mpidr_hash.shift_aff[0],
170 mpidr_hash.shift_aff[1],
171 mpidr_hash.shift_aff[2],
172 mpidr_hash.shift_aff[3],
173 mpidr_hash.mask,
174 mpidr_hash.bits);
175 /*
176 * 4x is an arbitrary value used to warn on a hash table much bigger
177 * than expected on most systems.
178 */
179 if (mpidr_hash_size() > 4 * num_possible_cpus())
180 pr_warn("Large number of MPIDR hash buckets detected\n");
181 }
182
183 static void __init setup_machine_fdt(phys_addr_t dt_phys)
184 {
185 void *dt_virt = fixmap_remap_fdt(dt_phys);
186 const char *name;
187
188 if (!dt_virt || !early_init_dt_scan(dt_virt)) {
189 pr_crit("\n"
190 "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n"
191 "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
192 "\nPlease check your bootloader.",
193 &dt_phys, dt_virt);
194
195 while (true)
196 cpu_relax();
197 }
198
199 name = of_flat_dt_get_machine_name();
200 if (!name)
201 return;
202
203 pr_info("Machine model: %s\n", name);
204 dump_stack_set_arch_desc("%s (DT)", name);
205 }
206
207 static void __init request_standard_resources(void)
208 {
209 struct memblock_region *region;
210 struct resource *res;
211 unsigned long i = 0;
212
213 kernel_code.start = __pa_symbol(_text);
214 kernel_code.end = __pa_symbol(__init_begin - 1);
215 kernel_data.start = __pa_symbol(_sdata);
216 kernel_data.end = __pa_symbol(_end - 1);
217
218 num_standard_resources = memblock.memory.cnt;
219 standard_resources = memblock_alloc_low(num_standard_resources *
220 sizeof(*standard_resources),
221 SMP_CACHE_BYTES);
222
223 for_each_memblock(memory, region) {
224 res = &standard_resources[i++];
225 if (memblock_is_nomap(region)) {
226 res->name = "reserved";
227 res->flags = IORESOURCE_MEM;
228 } else {
229 res->name = "System RAM";
230 res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
231 }
232 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
233 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
234
235 request_resource(&iomem_resource, res);
236
237 if (kernel_code.start >= res->start &&
238 kernel_code.end <= res->end)
239 request_resource(res, &kernel_code);
240 if (kernel_data.start >= res->start &&
241 kernel_data.end <= res->end)
242 request_resource(res, &kernel_data);
243 #ifdef CONFIG_KEXEC_CORE
244 /* Userspace will find "Crash kernel" region in /proc/iomem. */
245 if (crashk_res.end && crashk_res.start >= res->start &&
246 crashk_res.end <= res->end)
247 request_resource(res, &crashk_res);
248 #endif
249 }
250 }
251
252 static int __init reserve_memblock_reserved_regions(void)
253 {
254 u64 i, j;
255
256 for (i = 0; i < num_standard_resources; ++i) {
257 struct resource *mem = &standard_resources[i];
258 phys_addr_t r_start, r_end, mem_size = resource_size(mem);
259
260 if (!memblock_is_region_reserved(mem->start, mem_size))
261 continue;
262
263 for_each_reserved_mem_region(j, &r_start, &r_end) {
264 resource_size_t start, end;
265
266 start = max(PFN_PHYS(PFN_DOWN(r_start)), mem->start);
267 end = min(PFN_PHYS(PFN_UP(r_end)) - 1, mem->end);
268
269 if (start > mem->end || end < mem->start)
270 continue;
271
272 reserve_region_with_split(mem, start, end, "reserved");
273 }
274 }
275
276 return 0;
277 }
278 arch_initcall(reserve_memblock_reserved_regions);
279
280 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
281
282 void __init setup_arch(char **cmdline_p)
283 {
284 init_mm.start_code = (unsigned long) _text;
285 init_mm.end_code = (unsigned long) _etext;
286 init_mm.end_data = (unsigned long) _edata;
287 init_mm.brk = (unsigned long) _end;
288
289 *cmdline_p = boot_command_line;
290
291 early_fixmap_init();
292 early_ioremap_init();
293
294 setup_machine_fdt(__fdt_pointer);
295
296 parse_early_param();
297
298 /*
299 * Unmask asynchronous aborts and fiq after bringing up possible
300 * earlycon. (Report possible System Errors once we can report this
301 * occurred).
302 */
303 local_daif_restore(DAIF_PROCCTX_NOIRQ);
304
305 /*
306 * TTBR0 is only used for the identity mapping at this stage. Make it
307 * point to zero page to avoid speculatively fetching new entries.
308 */
309 cpu_uninstall_idmap();
310
311 xen_early_init();
312 efi_init();
313 arm64_memblock_init();
314
315 paging_init();
316
317 acpi_table_upgrade();
318
319 /* Parse the ACPI tables for possible boot-time configuration */
320 acpi_boot_table_init();
321
322 if (acpi_disabled)
323 unflatten_device_tree();
324
325 bootmem_init();
326
327 kasan_init();
328
329 request_standard_resources();
330
331 early_ioremap_reset();
332
333 if (acpi_disabled)
334 psci_dt_init();
335 else
336 psci_acpi_init();
337
338 cpu_read_bootcpu_ops();
339 smp_init_cpus();
340 smp_build_mpidr_hash();
341
342 /* Init percpu seeds for random tags after cpus are set up. */
343 kasan_init_tags();
344
345 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
346 /*
347 * Make sure init_thread_info.ttbr0 always generates translation
348 * faults in case uaccess_enable() is inadvertently called by the init
349 * thread.
350 */
351 init_task.thread_info.ttbr0 = __pa_symbol(empty_zero_page);
352 #endif
353
354 #ifdef CONFIG_VT
355 conswitchp = &dummy_con;
356 #endif
357 if (boot_args[1] || boot_args[2] || boot_args[3]) {
358 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
359 "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
360 "This indicates a broken bootloader or old kernel\n",
361 boot_args[1], boot_args[2], boot_args[3]);
362 }
363 }
364
365 static int __init topology_init(void)
366 {
367 int i;
368
369 for_each_online_node(i)
370 register_one_node(i);
371
372 for_each_possible_cpu(i) {
373 struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
374 cpu->hotpluggable = 1;
375 register_cpu(cpu, i);
376 }
377
378 return 0;
379 }
380 subsys_initcall(topology_init);
381
382 /*
383 * Dump out kernel offset information on panic.
384 */
385 static int dump_kernel_offset(struct notifier_block *self, unsigned long v,
386 void *p)
387 {
388 const unsigned long offset = kaslr_offset();
389
390 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && offset > 0) {
391 pr_emerg("Kernel Offset: 0x%lx from 0x%lx\n",
392 offset, KIMAGE_VADDR);
393 pr_emerg("PHYS_OFFSET: 0x%llx\n", PHYS_OFFSET);
394 } else {
395 pr_emerg("Kernel Offset: disabled\n");
396 }
397 return 0;
398 }
399
400 static struct notifier_block kernel_offset_notifier = {
401 .notifier_call = dump_kernel_offset
402 };
403
404 static int __init register_kernel_offset_dumper(void)
405 {
406 atomic_notifier_chain_register(&panic_notifier_list,
407 &kernel_offset_notifier);
408 return 0;
409 }
410 __initcall(register_kernel_offset_dumper);
411
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