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Linux/arch/arm64/mm/context.c

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  1 /*
  2  * Based on arch/arm/mm/context.c
  3  *
  4  * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
  5  * Copyright (C) 2012 ARM Ltd.
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  *
 16  * You should have received a copy of the GNU General Public License
 17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 18  */
 19 
 20 #include <linux/init.h>
 21 #include <linux/sched.h>
 22 #include <linux/mm.h>
 23 #include <linux/smp.h>
 24 #include <linux/percpu.h>
 25 
 26 #include <asm/mmu_context.h>
 27 #include <asm/tlbflush.h>
 28 #include <asm/cachetype.h>
 29 
 30 #define asid_bits(reg) \
 31         (((read_cpuid(ID_AA64MMFR0_EL1) & 0xf0) >> 2) + 8)
 32 
 33 #define ASID_FIRST_VERSION      (1 << MAX_ASID_BITS)
 34 
 35 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
 36 unsigned int cpu_last_asid = ASID_FIRST_VERSION;
 37 
 38 /*
 39  * We fork()ed a process, and we need a new context for the child to run in.
 40  */
 41 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 42 {
 43         mm->context.id = 0;
 44         raw_spin_lock_init(&mm->context.id_lock);
 45 }
 46 
 47 static void flush_context(void)
 48 {
 49         /* set the reserved TTBR0 before flushing the TLB */
 50         cpu_set_reserved_ttbr0();
 51         flush_tlb_all();
 52         if (icache_is_aivivt())
 53                 __flush_icache_all();
 54 }
 55 
 56 #ifdef CONFIG_SMP
 57 
 58 static void set_mm_context(struct mm_struct *mm, unsigned int asid)
 59 {
 60         unsigned long flags;
 61 
 62         /*
 63          * Locking needed for multi-threaded applications where the same
 64          * mm->context.id could be set from different CPUs during the
 65          * broadcast. This function is also called via IPI so the
 66          * mm->context.id_lock has to be IRQ-safe.
 67          */
 68         raw_spin_lock_irqsave(&mm->context.id_lock, flags);
 69         if (likely((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS)) {
 70                 /*
 71                  * Old version of ASID found. Set the new one and reset
 72                  * mm_cpumask(mm).
 73                  */
 74                 mm->context.id = asid;
 75                 cpumask_clear(mm_cpumask(mm));
 76         }
 77         raw_spin_unlock_irqrestore(&mm->context.id_lock, flags);
 78 
 79         /*
 80          * Set the mm_cpumask(mm) bit for the current CPU.
 81          */
 82         cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
 83 }
 84 
 85 /*
 86  * Reset the ASID on the current CPU. This function call is broadcast from the
 87  * CPU handling the ASID rollover and holding cpu_asid_lock.
 88  */
 89 static void reset_context(void *info)
 90 {
 91         unsigned int asid;
 92         unsigned int cpu = smp_processor_id();
 93         struct mm_struct *mm = current->active_mm;
 94 
 95         /*
 96          * current->active_mm could be init_mm for the idle thread immediately
 97          * after secondary CPU boot or hotplug. TTBR0_EL1 is already set to
 98          * the reserved value, so no need to reset any context.
 99          */
100         if (mm == &init_mm)
101                 return;
102 
103         smp_rmb();
104         asid = cpu_last_asid + cpu;
105 
106         flush_context();
107         set_mm_context(mm, asid);
108 
109         /* set the new ASID */
110         cpu_switch_mm(mm->pgd, mm);
111 }
112 
113 #else
114 
115 static inline void set_mm_context(struct mm_struct *mm, unsigned int asid)
116 {
117         mm->context.id = asid;
118         cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
119 }
120 
121 #endif
122 
123 void __new_context(struct mm_struct *mm)
124 {
125         unsigned int asid;
126         unsigned int bits = asid_bits();
127 
128         raw_spin_lock(&cpu_asid_lock);
129 #ifdef CONFIG_SMP
130         /*
131          * Check the ASID again, in case the change was broadcast from another
132          * CPU before we acquired the lock.
133          */
134         if (!unlikely((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS)) {
135                 cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
136                 raw_spin_unlock(&cpu_asid_lock);
137                 return;
138         }
139 #endif
140         /*
141          * At this point, it is guaranteed that the current mm (with an old
142          * ASID) isn't active on any other CPU since the ASIDs are changed
143          * simultaneously via IPI.
144          */
145         asid = ++cpu_last_asid;
146 
147         /*
148          * If we've used up all our ASIDs, we need to start a new version and
149          * flush the TLB.
150          */
151         if (unlikely((asid & ((1 << bits) - 1)) == 0)) {
152                 /* increment the ASID version */
153                 cpu_last_asid += (1 << MAX_ASID_BITS) - (1 << bits);
154                 if (cpu_last_asid == 0)
155                         cpu_last_asid = ASID_FIRST_VERSION;
156                 asid = cpu_last_asid + smp_processor_id();
157                 flush_context();
158 #ifdef CONFIG_SMP
159                 smp_wmb();
160                 smp_call_function(reset_context, NULL, 1);
161 #endif
162                 cpu_last_asid += NR_CPUS - 1;
163         }
164 
165         set_mm_context(mm, asid);
166         raw_spin_unlock(&cpu_asid_lock);
167 }
168 

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