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Linux/arch/blackfin/kernel/bfin_dma_5xx.c

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  1 /*
  2  * bfin_dma_5xx.c - Blackfin DMA implementation
  3  *
  4  * Copyright 2004-2008 Analog Devices Inc.
  5  *
  6  * Licensed under the GPL-2 or later.
  7  */
  8 
  9 #include <linux/errno.h>
 10 #include <linux/interrupt.h>
 11 #include <linux/kernel.h>
 12 #include <linux/module.h>
 13 #include <linux/param.h>
 14 #include <linux/proc_fs.h>
 15 #include <linux/sched.h>
 16 #include <linux/seq_file.h>
 17 #include <linux/spinlock.h>
 18 
 19 #include <asm/blackfin.h>
 20 #include <asm/cacheflush.h>
 21 #include <asm/dma.h>
 22 #include <asm/uaccess.h>
 23 #include <asm/early_printk.h>
 24 
 25 /*
 26  * To make sure we work around 05000119 - we always check DMA_DONE bit,
 27  * never the DMA_RUN bit
 28  */
 29 
 30 struct dma_channel dma_ch[MAX_DMA_CHANNELS];
 31 EXPORT_SYMBOL(dma_ch);
 32 
 33 static int __init blackfin_dma_init(void)
 34 {
 35         int i;
 36 
 37         printk(KERN_INFO "Blackfin DMA Controller\n");
 38 
 39 
 40 #if ANOMALY_05000480
 41         bfin_write_DMAC_TC_PER(0x0111);
 42 #endif
 43 
 44         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
 45                 atomic_set(&dma_ch[i].chan_status, 0);
 46                 dma_ch[i].regs = dma_io_base_addr[i];
 47         }
 48         /* Mark MEMDMA Channel 0 as requested since we're using it internally */
 49         request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
 50         request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
 51 
 52 #if defined(CONFIG_DEB_DMA_URGENT)
 53         bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
 54                          | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT);
 55 #endif
 56 
 57         return 0;
 58 }
 59 arch_initcall(blackfin_dma_init);
 60 
 61 #ifdef CONFIG_PROC_FS
 62 static int proc_dma_show(struct seq_file *m, void *v)
 63 {
 64         int i;
 65 
 66         for (i = 0; i < MAX_DMA_CHANNELS; ++i)
 67                 if (dma_channel_active(i))
 68                         seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
 69 
 70         return 0;
 71 }
 72 
 73 static int proc_dma_open(struct inode *inode, struct file *file)
 74 {
 75         return single_open(file, proc_dma_show, NULL);
 76 }
 77 
 78 static const struct file_operations proc_dma_operations = {
 79         .open           = proc_dma_open,
 80         .read           = seq_read,
 81         .llseek         = seq_lseek,
 82         .release        = single_release,
 83 };
 84 
 85 static int __init proc_dma_init(void)
 86 {
 87         return proc_create("dma", 0, NULL, &proc_dma_operations) != NULL;
 88 }
 89 late_initcall(proc_dma_init);
 90 #endif
 91 
 92 static void set_dma_peripheral_map(unsigned int channel, const char *device_id)
 93 {
 94 #ifdef CONFIG_BF54x
 95         unsigned int per_map;
 96 
 97         switch (channel) {
 98                 case CH_UART2_RX: per_map = 0xC << 12; break;
 99                 case CH_UART2_TX: per_map = 0xD << 12; break;
100                 case CH_UART3_RX: per_map = 0xE << 12; break;
101                 case CH_UART3_TX: per_map = 0xF << 12; break;
102                 default:          return;
103         }
104 
105         if (strncmp(device_id, "BFIN_UART", 9) == 0)
106                 dma_ch[channel].regs->peripheral_map = per_map;
107 #endif
108 }
109 
110 /**
111  *      request_dma - request a DMA channel
112  *
113  * Request the specific DMA channel from the system if it's available.
114  */
115 int request_dma(unsigned int channel, const char *device_id)
116 {
117         pr_debug("request_dma() : BEGIN\n");
118 
119         if (device_id == NULL)
120                 printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel);
121 
122 #if defined(CONFIG_BF561) && ANOMALY_05000182
123         if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) {
124                 if (get_cclk() > 500000000) {
125                         printk(KERN_WARNING
126                                "Request IMDMA failed due to ANOMALY 05000182\n");
127                         return -EFAULT;
128                 }
129         }
130 #endif
131 
132         if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) {
133                 pr_debug("DMA CHANNEL IN USE\n");
134                 return -EBUSY;
135         }
136 
137         set_dma_peripheral_map(channel, device_id);
138         dma_ch[channel].device_id = device_id;
139         dma_ch[channel].irq = 0;
140 
141         /* This is to be enabled by putting a restriction -
142          * you have to request DMA, before doing any operations on
143          * descriptor/channel
144          */
145         pr_debug("request_dma() : END\n");
146         return 0;
147 }
148 EXPORT_SYMBOL(request_dma);
149 
150 int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data)
151 {
152         int ret;
153         unsigned int irq;
154 
155         BUG_ON(channel >= MAX_DMA_CHANNELS || !callback ||
156                         !atomic_read(&dma_ch[channel].chan_status));
157 
158         irq = channel2irq(channel);
159         ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data);
160         if (ret)
161                 return ret;
162 
163         dma_ch[channel].irq = irq;
164         dma_ch[channel].data = data;
165 
166         return 0;
167 }
168 EXPORT_SYMBOL(set_dma_callback);
169 
170 /**
171  *      clear_dma_buffer - clear DMA fifos for specified channel
172  *
173  * Set the Buffer Clear bit in the Configuration register of specific DMA
174  * channel. This will stop the descriptor based DMA operation.
175  */
176 static void clear_dma_buffer(unsigned int channel)
177 {
178         dma_ch[channel].regs->cfg |= RESTART;
179         SSYNC();
180         dma_ch[channel].regs->cfg &= ~RESTART;
181 }
182 
183 void free_dma(unsigned int channel)
184 {
185         pr_debug("freedma() : BEGIN\n");
186         BUG_ON(channel >= MAX_DMA_CHANNELS ||
187                         !atomic_read(&dma_ch[channel].chan_status));
188 
189         /* Halt the DMA */
190         disable_dma(channel);
191         clear_dma_buffer(channel);
192 
193         if (dma_ch[channel].irq)
194                 free_irq(dma_ch[channel].irq, dma_ch[channel].data);
195 
196         /* Clear the DMA Variable in the Channel */
197         atomic_set(&dma_ch[channel].chan_status, 0);
198 
199         pr_debug("freedma() : END\n");
200 }
201 EXPORT_SYMBOL(free_dma);
202 
203 #ifdef CONFIG_PM
204 # ifndef MAX_DMA_SUSPEND_CHANNELS
205 #  define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
206 # endif
207 int blackfin_dma_suspend(void)
208 {
209         int i;
210 
211         for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
212                 if (dma_ch[i].regs->cfg & DMAEN) {
213                         printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
214                         return -EBUSY;
215                 }
216 
217                 if (i < MAX_DMA_SUSPEND_CHANNELS)
218                         dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
219         }
220 
221         return 0;
222 }
223 
224 void blackfin_dma_resume(void)
225 {
226         int i;
227 
228         for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
229                 dma_ch[i].regs->cfg = 0;
230 
231                 if (i < MAX_DMA_SUSPEND_CHANNELS)
232                         dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
233         }
234 }
235 #endif
236 
237 /**
238  *      blackfin_dma_early_init - minimal DMA init
239  *
240  * Setup a few DMA registers so we can safely do DMA transfers early on in
241  * the kernel booting process.  Really this just means using dma_memcpy().
242  */
243 void __init blackfin_dma_early_init(void)
244 {
245         early_shadow_stamp();
246         bfin_write_MDMA_S0_CONFIG(0);
247         bfin_write_MDMA_S1_CONFIG(0);
248 }
249 
250 void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
251 {
252         unsigned long dst = (unsigned long)pdst;
253         unsigned long src = (unsigned long)psrc;
254         struct dma_register *dst_ch, *src_ch;
255 
256         early_shadow_stamp();
257 
258         /* We assume that everything is 4 byte aligned, so include
259          * a basic sanity check
260          */
261         BUG_ON(dst % 4);
262         BUG_ON(src % 4);
263         BUG_ON(size % 4);
264 
265         src_ch = 0;
266         /* Find an avalible memDMA channel */
267         while (1) {
268                 if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) {
269                         dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
270                         src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
271                 } else {
272                         dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
273                         src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
274                 }
275 
276                 if (!bfin_read16(&src_ch->cfg))
277                         break;
278                 else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) {
279                         bfin_write16(&src_ch->cfg, 0);
280                         break;
281                 }
282         }
283 
284         /* Force a sync in case a previous config reset on this channel
285          * occurred.  This is needed so subsequent writes to DMA registers
286          * are not spuriously lost/corrupted.
287          */
288         __builtin_bfin_ssync();
289 
290         /* Destination */
291         bfin_write32(&dst_ch->start_addr, dst);
292         bfin_write16(&dst_ch->x_count, size >> 2);
293         bfin_write16(&dst_ch->x_modify, 1 << 2);
294         bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
295 
296         /* Source */
297         bfin_write32(&src_ch->start_addr, src);
298         bfin_write16(&src_ch->x_count, size >> 2);
299         bfin_write16(&src_ch->x_modify, 1 << 2);
300         bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR);
301 
302         /* Enable */
303         bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32);
304         bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32);
305 
306         /* Since we are atomic now, don't use the workaround ssync */
307         __builtin_bfin_ssync();
308 }
309 
310 void __init early_dma_memcpy_done(void)
311 {
312         early_shadow_stamp();
313 
314         while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) ||
315                (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE)))
316                 continue;
317 
318         bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
319         bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR);
320         /*
321          * Now that DMA is done, we would normally flush cache, but
322          * i/d cache isn't running this early, so we don't bother,
323          * and just clear out the DMA channel for next time
324          */
325         bfin_write_MDMA_S0_CONFIG(0);
326         bfin_write_MDMA_S1_CONFIG(0);
327         bfin_write_MDMA_D0_CONFIG(0);
328         bfin_write_MDMA_D1_CONFIG(0);
329 
330         __builtin_bfin_ssync();
331 }
332 
333 /**
334  *      __dma_memcpy - program the MDMA registers
335  *
336  * Actually program MDMA0 and wait for the transfer to finish.  Disable IRQs
337  * while programming registers so that everything is fully configured.  Wait
338  * for DMA to finish with IRQs enabled.  If interrupted, the initial DMA_DONE
339  * check will make sure we don't clobber any existing transfer.
340  */
341 static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf)
342 {
343         static DEFINE_SPINLOCK(mdma_lock);
344         unsigned long flags;
345 
346         spin_lock_irqsave(&mdma_lock, flags);
347 
348         /* Force a sync in case a previous config reset on this channel
349          * occurred.  This is needed so subsequent writes to DMA registers
350          * are not spuriously lost/corrupted.  Do it under irq lock and
351          * without the anomaly version (because we are atomic already).
352          */
353         __builtin_bfin_ssync();
354 
355         if (bfin_read_MDMA_S0_CONFIG())
356                 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
357                         continue;
358 
359         if (conf & DMA2D) {
360                 /* For larger bit sizes, we've already divided down cnt so it
361                  * is no longer a multiple of 64k.  So we have to break down
362                  * the limit here so it is a multiple of the incoming size.
363                  * There is no limitation here in terms of total size other
364                  * than the hardware though as the bits lost in the shift are
365                  * made up by MODIFY (== we can hit the whole address space).
366                  * X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4
367                  */
368                 u32 shift = abs(dmod) >> 1;
369                 size_t ycnt = cnt >> (16 - shift);
370                 cnt = 1 << (16 - shift);
371                 bfin_write_MDMA_D0_Y_COUNT(ycnt);
372                 bfin_write_MDMA_S0_Y_COUNT(ycnt);
373                 bfin_write_MDMA_D0_Y_MODIFY(dmod);
374                 bfin_write_MDMA_S0_Y_MODIFY(smod);
375         }
376 
377         bfin_write_MDMA_D0_START_ADDR(daddr);
378         bfin_write_MDMA_D0_X_COUNT(cnt);
379         bfin_write_MDMA_D0_X_MODIFY(dmod);
380         bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
381 
382         bfin_write_MDMA_S0_START_ADDR(saddr);
383         bfin_write_MDMA_S0_X_COUNT(cnt);
384         bfin_write_MDMA_S0_X_MODIFY(smod);
385         bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
386 
387         bfin_write_MDMA_S0_CONFIG(DMAEN | conf);
388         bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf);
389 
390         spin_unlock_irqrestore(&mdma_lock, flags);
391 
392         SSYNC();
393 
394         while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
395                 if (bfin_read_MDMA_S0_CONFIG())
396                         continue;
397                 else
398                         return;
399 
400         bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
401 
402         bfin_write_MDMA_S0_CONFIG(0);
403         bfin_write_MDMA_D0_CONFIG(0);
404 }
405 
406 /**
407  *      _dma_memcpy - translate C memcpy settings into MDMA settings
408  *
409  * Handle all the high level steps before we touch the MDMA registers.  So
410  * handle direction, tweaking of sizes, and formatting of addresses.
411  */
412 static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
413 {
414         u32 conf, shift;
415         s16 mod;
416         unsigned long dst = (unsigned long)pdst;
417         unsigned long src = (unsigned long)psrc;
418 
419         if (size == 0)
420                 return NULL;
421 
422         if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) {
423                 conf = WDSIZE_32;
424                 shift = 2;
425         } else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) {
426                 conf = WDSIZE_16;
427                 shift = 1;
428         } else {
429                 conf = WDSIZE_8;
430                 shift = 0;
431         }
432 
433         /* If the two memory regions have a chance of overlapping, make
434          * sure the memcpy still works as expected.  Do this by having the
435          * copy run backwards instead.
436          */
437         mod = 1 << shift;
438         if (src < dst) {
439                 mod *= -1;
440                 dst += size + mod;
441                 src += size + mod;
442         }
443         size >>= shift;
444 
445         if (size > 0x10000)
446                 conf |= DMA2D;
447 
448         __dma_memcpy(dst, mod, src, mod, size, conf);
449 
450         return pdst;
451 }
452 
453 /**
454  *      dma_memcpy - DMA memcpy under mutex lock
455  *
456  * Do not check arguments before starting the DMA memcpy.  Break the transfer
457  * up into two pieces.  The first transfer is in multiples of 64k and the
458  * second transfer is the piece smaller than 64k.
459  */
460 void *dma_memcpy(void *pdst, const void *psrc, size_t size)
461 {
462         unsigned long dst = (unsigned long)pdst;
463         unsigned long src = (unsigned long)psrc;
464 
465         if (bfin_addr_dcacheable(src))
466                 blackfin_dcache_flush_range(src, src + size);
467 
468         if (bfin_addr_dcacheable(dst))
469                 blackfin_dcache_invalidate_range(dst, dst + size);
470 
471         return dma_memcpy_nocache(pdst, psrc, size);
472 }
473 EXPORT_SYMBOL(dma_memcpy);
474 
475 /**
476  *      dma_memcpy_nocache - DMA memcpy under mutex lock
477  *      - No cache flush/invalidate
478  *
479  * Do not check arguments before starting the DMA memcpy.  Break the transfer
480  * up into two pieces.  The first transfer is in multiples of 64k and the
481  * second transfer is the piece smaller than 64k.
482  */
483 void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
484 {
485         size_t bulk, rest;
486 
487         bulk = size & ~0xffff;
488         rest = size - bulk;
489         if (bulk)
490                 _dma_memcpy(pdst, psrc, bulk);
491         _dma_memcpy(pdst + bulk, psrc + bulk, rest);
492         return pdst;
493 }
494 EXPORT_SYMBOL(dma_memcpy_nocache);
495 
496 /**
497  *      safe_dma_memcpy - DMA memcpy w/argument checking
498  *
499  * Verify arguments are safe before heading to dma_memcpy().
500  */
501 void *safe_dma_memcpy(void *dst, const void *src, size_t size)
502 {
503         if (!access_ok(VERIFY_WRITE, dst, size))
504                 return NULL;
505         if (!access_ok(VERIFY_READ, src, size))
506                 return NULL;
507         return dma_memcpy(dst, src, size);
508 }
509 EXPORT_SYMBOL(safe_dma_memcpy);
510 
511 static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len,
512                      u16 size, u16 dma_size)
513 {
514         blackfin_dcache_flush_range(buf, buf + len * size);
515         __dma_memcpy(addr, 0, buf, size, len, dma_size);
516 }
517 
518 static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
519                     u16 size, u16 dma_size)
520 {
521         blackfin_dcache_invalidate_range(buf, buf + len * size);
522         __dma_memcpy(buf, size, addr, 0, len, dma_size);
523 }
524 
525 #define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
526 void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \
527 { \
528         _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
529 } \
530 EXPORT_SYMBOL(dma_##io##s##bwl)
531 MAKE_DMA_IO(out, b, 1,  8, const);
532 MAKE_DMA_IO(in,  b, 1,  8, );
533 MAKE_DMA_IO(out, w, 2, 16, const);
534 MAKE_DMA_IO(in,  w, 2, 16, );
535 MAKE_DMA_IO(out, l, 4, 32, const);
536 MAKE_DMA_IO(in,  l, 4, 32, );
537 

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