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TOMOYO Linux Cross Reference
Linux/arch/blackfin/mach-bf561/include/mach/defBF561.h

Version: ~ [ linux-5.4-rc3 ] ~ [ linux-5.3.6 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.79 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.149 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.196 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.196 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.75 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * Copyright 2005-2010 Analog Devices Inc.
  3  *
  4  * Licensed under the Clear BSD license or the GPL-2 (or later)
  5  */
  6 
  7 #ifndef _DEF_BF561_H
  8 #define _DEF_BF561_H
  9 
 10 /*********************************************************************************** */
 11 /* System MMR Register Map */
 12 /*********************************************************************************** */
 13 
 14 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
 15 
 16 #define PLL_CTL                0xFFC00000       /* PLL Control register (16-bit) */
 17 #define PLL_DIV                         0xFFC00004      /* PLL Divide Register (16-bit) */
 18 #define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register (16-bit) */
 19 #define PLL_STAT               0xFFC0000C       /* PLL Status register (16-bit) */
 20 #define PLL_LOCKCNT            0xFFC00010       /* PLL Lock Count register (16-bit) */
 21 #define CHIPID                 0xFFC00014       /* Chip ID Register */
 22 
 23 /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
 24 #define DOUBLE_FAULT            (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
 25 #define RESET_DOUBLE            (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
 26 #define RESET_WDOG              (SWRST_WDT_B|SWRST_WDT_A)
 27 #define RESET_SOFTWARE          (SWRST_OCCURRED)
 28 
 29 /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
 30 #define SWRST                   0xFFC00100      /* Software Reset register */
 31 #define SYSCR                   0xFFC00104      /* System Reset Configuration register */
 32 #define SIC_RVECT               0xFFC00108      /* SIC Reset Vector Address Register */
 33 #define SIC_IMASK0              0xFFC0010C      /* SIC Interrupt Mask register 0 */
 34 #define SIC_IMASK1              0xFFC00110      /* SIC Interrupt Mask register 1 */
 35 #define SIC_IAR0                0xFFC00124      /* SIC Interrupt Assignment Register 0 */
 36 #define SIC_IAR1                0xFFC00128      /* SIC Interrupt Assignment Register 1 */
 37 #define SIC_IAR2                0xFFC0012C      /* SIC Interrupt Assignment Register 2 */
 38 #define SIC_IAR3                0xFFC00130      /* SIC Interrupt Assignment Register 3 */
 39 #define SIC_IAR4                0xFFC00134      /* SIC Interrupt Assignment Register 4 */
 40 #define SIC_IAR5                0xFFC00138      /* SIC Interrupt Assignment Register 5 */
 41 #define SIC_IAR6                0xFFC0013C      /* SIC Interrupt Assignment Register 6 */
 42 #define SIC_IAR7                0xFFC00140      /* SIC Interrupt Assignment Register 7 */
 43 #define SIC_ISR0                0xFFC00114      /* SIC Interrupt Status register 0 */
 44 #define SIC_ISR1                0xFFC00118      /* SIC Interrupt Status register 1 */
 45 #define SIC_IWR0                0xFFC0011C      /* SIC Interrupt Wakeup-Enable register 0 */
 46 #define SIC_IWR1                0xFFC00120      /* SIC Interrupt Wakeup-Enable register 1 */
 47 
 48 /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
 49 #define SICB_SWRST              0xFFC01100      /* reserved */
 50 #define SICB_SYSCR              0xFFC01104      /* reserved */
 51 #define SICB_RVECT              0xFFC01108      /* SIC Reset Vector Address Register */
 52 #define SICB_IMASK0             0xFFC0110C      /* SIC Interrupt Mask register 0 */
 53 #define SICB_IMASK1             0xFFC01110      /* SIC Interrupt Mask register 1 */
 54 #define SICB_IAR0               0xFFC01124      /* SIC Interrupt Assignment Register 0 */
 55 #define SICB_IAR1               0xFFC01128      /* SIC Interrupt Assignment Register 1 */
 56 #define SICB_IAR2               0xFFC0112C      /* SIC Interrupt Assignment Register 2 */
 57 #define SICB_IAR3               0xFFC01130      /* SIC Interrupt Assignment Register 3 */
 58 #define SICB_IAR4               0xFFC01134      /* SIC Interrupt Assignment Register 4 */
 59 #define SICB_IAR5               0xFFC01138      /* SIC Interrupt Assignment Register 5 */
 60 #define SICB_IAR6               0xFFC0113C      /* SIC Interrupt Assignment Register 6 */
 61 #define SICB_IAR7               0xFFC01140      /* SIC Interrupt Assignment Register 7 */
 62 #define SICB_ISR0               0xFFC01114      /* SIC Interrupt Status register 0 */
 63 #define SICB_ISR1               0xFFC01118      /* SIC Interrupt Status register 1 */
 64 #define SICB_IWR0               0xFFC0111C      /* SIC Interrupt Wakeup-Enable register 0 */
 65 #define SICB_IWR1               0xFFC01120      /* SIC Interrupt Wakeup-Enable register 1 */
 66 
 67 /* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
 68 #define WDOGA_CTL                               0xFFC00200      /* Watchdog Control register */
 69 #define WDOGA_CNT                               0xFFC00204      /* Watchdog Count register */
 70 #define WDOGA_STAT                              0xFFC00208      /* Watchdog Status register */
 71 
 72 /* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
 73 #define WDOGB_CTL                               0xFFC01200      /* Watchdog Control register */
 74 #define WDOGB_CNT                               0xFFC01204      /* Watchdog Count register */
 75 #define WDOGB_STAT                              0xFFC01208      /* Watchdog Status register */
 76 
 77 /* UART Controller (0xFFC00400 - 0xFFC004FF) */
 78 
 79 /*
 80  * Because include/linux/serial_reg.h have defined UART_*,
 81  * So we define blackfin uart regs to BFIN_UART0_*.
 82  */
 83 #define BFIN_UART_THR                   0xFFC00400  /* Transmit Holding register */
 84 #define BFIN_UART_RBR                   0xFFC00400  /* Receive Buffer register */
 85 #define BFIN_UART_DLL                   0xFFC00400  /* Divisor Latch (Low-Byte) */
 86 #define BFIN_UART_IER                   0xFFC00404  /* Interrupt Enable Register */
 87 #define BFIN_UART_DLH                   0xFFC00404  /* Divisor Latch (High-Byte) */
 88 #define BFIN_UART_IIR                   0xFFC00408  /* Interrupt Identification Register */
 89 #define BFIN_UART_LCR                   0xFFC0040C  /* Line Control Register */
 90 #define BFIN_UART_MCR                   0xFFC00410  /* Modem Control Register */
 91 #define BFIN_UART_LSR                   0xFFC00414  /* Line Status Register */
 92 #define BFIN_UART_MSR                   0xFFC00418  /* Modem Status Register */
 93 #define BFIN_UART_SCR                   0xFFC0041C  /* SCR Scratch Register */
 94 #define BFIN_UART_GCTL                  0xFFC00424  /* Global Control Register */
 95 
 96 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
 97 #define SPI0_REGBASE                    0xFFC00500
 98 #define SPI_CTL                         0xFFC00500      /* SPI Control Register */
 99 #define SPI_FLG                         0xFFC00504      /* SPI Flag register */
100 #define SPI_STAT                        0xFFC00508      /* SPI Status register */
101 #define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register */
102 #define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register */
103 #define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register */
104 #define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register */
105 
106 /* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
107 #define TIMER0_CONFIG                           0xFFC00600      /* Timer0 Configuration register */
108 #define TIMER0_COUNTER                          0xFFC00604      /* Timer0 Counter register */
109 #define TIMER0_PERIOD                           0xFFC00608      /* Timer0 Period register */
110 #define TIMER0_WIDTH                            0xFFC0060C      /* Timer0 Width register */
111 
112 #define TIMER1_CONFIG                           0xFFC00610      /* Timer1 Configuration register */
113 #define TIMER1_COUNTER                          0xFFC00614      /* Timer1 Counter register */
114 #define TIMER1_PERIOD                           0xFFC00618      /* Timer1 Period register */
115 #define TIMER1_WIDTH                            0xFFC0061C      /* Timer1 Width register */
116 
117 #define TIMER2_CONFIG                           0xFFC00620      /* Timer2 Configuration register */
118 #define TIMER2_COUNTER                          0xFFC00624      /* Timer2 Counter register */
119 #define TIMER2_PERIOD                           0xFFC00628      /* Timer2 Period register */
120 #define TIMER2_WIDTH                            0xFFC0062C      /* Timer2 Width register */
121 
122 #define TIMER3_CONFIG                           0xFFC00630      /* Timer3 Configuration register */
123 #define TIMER3_COUNTER                          0xFFC00634      /* Timer3 Counter register */
124 #define TIMER3_PERIOD                           0xFFC00638      /* Timer3 Period register */
125 #define TIMER3_WIDTH                            0xFFC0063C      /* Timer3 Width register */
126 
127 #define TIMER4_CONFIG                           0xFFC00640      /* Timer4 Configuration register */
128 #define TIMER4_COUNTER                          0xFFC00644      /* Timer4 Counter register */
129 #define TIMER4_PERIOD                           0xFFC00648      /* Timer4 Period register */
130 #define TIMER4_WIDTH                            0xFFC0064C      /* Timer4 Width register */
131 
132 #define TIMER5_CONFIG                           0xFFC00650      /* Timer5 Configuration register */
133 #define TIMER5_COUNTER                          0xFFC00654      /* Timer5 Counter register */
134 #define TIMER5_PERIOD                           0xFFC00658      /* Timer5 Period register */
135 #define TIMER5_WIDTH                            0xFFC0065C      /* Timer5 Width register */
136 
137 #define TIMER6_CONFIG                           0xFFC00660      /* Timer6 Configuration register */
138 #define TIMER6_COUNTER                          0xFFC00664      /* Timer6 Counter register */
139 #define TIMER6_PERIOD                           0xFFC00668      /* Timer6 Period register */
140 #define TIMER6_WIDTH                            0xFFC0066C      /* Timer6 Width register */
141 
142 #define TIMER7_CONFIG                           0xFFC00670      /* Timer7 Configuration register */
143 #define TIMER7_COUNTER                          0xFFC00674      /* Timer7 Counter register */
144 #define TIMER7_PERIOD                           0xFFC00678      /* Timer7 Period register */
145 #define TIMER7_WIDTH                            0xFFC0067C      /* Timer7 Width register */
146 
147 #define TMRS8_ENABLE                            0xFFC00680      /* Timer Enable Register */
148 #define TMRS8_DISABLE                           0xFFC00684      /* Timer Disable register */
149 #define TMRS8_STATUS                            0xFFC00688      /* Timer Status register */
150 
151 /* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
152 #define TIMER8_CONFIG                           0xFFC01600      /* Timer8 Configuration register */
153 #define TIMER8_COUNTER                          0xFFC01604      /* Timer8 Counter register */
154 #define TIMER8_PERIOD                           0xFFC01608      /* Timer8 Period register */
155 #define TIMER8_WIDTH                            0xFFC0160C      /* Timer8 Width register */
156 
157 #define TIMER9_CONFIG                           0xFFC01610      /* Timer9 Configuration register */
158 #define TIMER9_COUNTER                          0xFFC01614      /* Timer9 Counter register */
159 #define TIMER9_PERIOD                           0xFFC01618      /* Timer9 Period register */
160 #define TIMER9_WIDTH                            0xFFC0161C      /* Timer9 Width register */
161 
162 #define TIMER10_CONFIG                          0xFFC01620      /* Timer10 Configuration register */
163 #define TIMER10_COUNTER                         0xFFC01624      /* Timer10 Counter register */
164 #define TIMER10_PERIOD                          0xFFC01628      /* Timer10 Period register */
165 #define TIMER10_WIDTH                           0xFFC0162C      /* Timer10 Width register */
166 
167 #define TIMER11_CONFIG                          0xFFC01630      /* Timer11 Configuration register */
168 #define TIMER11_COUNTER                         0xFFC01634      /* Timer11 Counter register */
169 #define TIMER11_PERIOD                          0xFFC01638      /* Timer11 Period register */
170 #define TIMER11_WIDTH                           0xFFC0163C      /* Timer11 Width register */
171 
172 #define TMRS4_ENABLE                            0xFFC01640      /* Timer Enable Register */
173 #define TMRS4_DISABLE                           0xFFC01644      /* Timer Disable register */
174 #define TMRS4_STATUS                            0xFFC01648      /* Timer Status register */
175 
176 /* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
177 #define FIO0_FLAG_D                             0xFFC00700      /* Flag Data register */
178 #define FIO0_FLAG_C                             0xFFC00704      /* Flag Clear register */
179 #define FIO0_FLAG_S                             0xFFC00708      /* Flag Set register */
180 #define FIO0_FLAG_T                             0xFFC0070C      /* Flag Toggle register */
181 #define FIO0_MASKA_D                            0xFFC00710      /* Flag Mask Interrupt A Data register */
182 #define FIO0_MASKA_C                            0xFFC00714      /* Flag Mask Interrupt A Clear register */
183 #define FIO0_MASKA_S                            0xFFC00718      /* Flag Mask Interrupt A Set register */
184 #define FIO0_MASKA_T                            0xFFC0071C      /* Flag Mask Interrupt A Toggle register */
185 #define FIO0_MASKB_D                            0xFFC00720      /* Flag Mask Interrupt B Data register */
186 #define FIO0_MASKB_C                            0xFFC00724      /* Flag Mask Interrupt B Clear register */
187 #define FIO0_MASKB_S                            0xFFC00728      /* Flag Mask Interrupt B Set register */
188 #define FIO0_MASKB_T                            0xFFC0072C      /* Flag Mask Interrupt B Toggle register */
189 #define FIO0_DIR                                        0xFFC00730      /* Flag Direction register */
190 #define FIO0_POLAR                                      0xFFC00734      /* Flag Polarity register */
191 #define FIO0_EDGE                                       0xFFC00738      /* Flag Interrupt Sensitivity register */
192 #define FIO0_BOTH                                       0xFFC0073C      /* Flag Set on Both Edges register */
193 #define FIO0_INEN                                       0xFFC00740      /* Flag Input Enable register */
194 
195 /* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
196 #define FIO1_FLAG_D                             0xFFC01500      /* Flag Data register (mask used to directly */
197 #define FIO1_FLAG_C                             0xFFC01504      /* Flag Clear register */
198 #define FIO1_FLAG_S                             0xFFC01508      /* Flag Set register */
199 #define FIO1_FLAG_T                             0xFFC0150C      /* Flag Toggle register (mask used to */
200 #define FIO1_MASKA_D                            0xFFC01510      /* Flag Mask Interrupt A Data register */
201 #define FIO1_MASKA_C                            0xFFC01514      /* Flag Mask Interrupt A Clear register */
202 #define FIO1_MASKA_S                            0xFFC01518      /* Flag Mask Interrupt A Set register */
203 #define FIO1_MASKA_T                            0xFFC0151C      /* Flag Mask Interrupt A Toggle register */
204 #define FIO1_MASKB_D                            0xFFC01520      /* Flag Mask Interrupt B Data register */
205 #define FIO1_MASKB_C                            0xFFC01524      /* Flag Mask Interrupt B Clear register */
206 #define FIO1_MASKB_S                            0xFFC01528      /* Flag Mask Interrupt B Set register */
207 #define FIO1_MASKB_T                            0xFFC0152C      /* Flag Mask Interrupt B Toggle register */
208 #define FIO1_DIR                                        0xFFC01530      /* Flag Direction register */
209 #define FIO1_POLAR                                      0xFFC01534      /* Flag Polarity register */
210 #define FIO1_EDGE                                       0xFFC01538      /* Flag Interrupt Sensitivity register */
211 #define FIO1_BOTH                                       0xFFC0153C      /* Flag Set on Both Edges register */
212 #define FIO1_INEN                                       0xFFC01540      /* Flag Input Enable register */
213 
214 /* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
215 #define FIO2_FLAG_D                             0xFFC01700      /* Flag Data register (mask used to directly */
216 #define FIO2_FLAG_C                             0xFFC01704      /* Flag Clear register */
217 #define FIO2_FLAG_S                             0xFFC01708      /* Flag Set register */
218 #define FIO2_FLAG_T                             0xFFC0170C      /* Flag Toggle register (mask used to */
219 #define FIO2_MASKA_D                            0xFFC01710      /* Flag Mask Interrupt A Data register */
220 #define FIO2_MASKA_C                            0xFFC01714      /* Flag Mask Interrupt A Clear register */
221 #define FIO2_MASKA_S                            0xFFC01718      /* Flag Mask Interrupt A Set register */
222 #define FIO2_MASKA_T                            0xFFC0171C      /* Flag Mask Interrupt A Toggle register */
223 #define FIO2_MASKB_D                            0xFFC01720      /* Flag Mask Interrupt B Data register */
224 #define FIO2_MASKB_C                            0xFFC01724      /* Flag Mask Interrupt B Clear register */
225 #define FIO2_MASKB_S                            0xFFC01728      /* Flag Mask Interrupt B Set register */
226 #define FIO2_MASKB_T                            0xFFC0172C      /* Flag Mask Interrupt B Toggle register */
227 #define FIO2_DIR                                        0xFFC01730      /* Flag Direction register */
228 #define FIO2_POLAR                                      0xFFC01734      /* Flag Polarity register */
229 #define FIO2_EDGE                                       0xFFC01738      /* Flag Interrupt Sensitivity register */
230 #define FIO2_BOTH                                       0xFFC0173C      /* Flag Set on Both Edges register */
231 #define FIO2_INEN                                       0xFFC01740      /* Flag Input Enable register */
232 
233 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
234 #define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register */
235 #define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register */
236 #define SPORT0_TCLKDIV                  0xFFC00808      /* SPORT0 Transmit Clock Divider */
237 #define SPORT0_TFSDIV                   0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider */
238 #define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register */
239 #define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register */
240 #define SPORT0_RCR1                             0xFFC00820      /* SPORT0 Transmit Configuration 1 Register */
241 #define SPORT0_RCR2                             0xFFC00824      /* SPORT0 Transmit Configuration 2 Register */
242 #define SPORT0_RCLKDIV                  0xFFC00828      /* SPORT0 Receive Clock Divider */
243 #define SPORT0_RFSDIV                   0xFFC0082C      /* SPORT0 Receive Frame Sync Divider */
244 #define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register */
245 #define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register */
246 #define SPORT0_MCMC1                    0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1 */
247 #define SPORT0_MCMC2                    0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2 */
248 #define SPORT0_MTCS0                    0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0 */
249 #define SPORT0_MTCS1                    0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1 */
250 #define SPORT0_MTCS2                    0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2 */
251 #define SPORT0_MTCS3                    0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3 */
252 #define SPORT0_MRCS0                    0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0 */
253 #define SPORT0_MRCS1                    0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1 */
254 #define SPORT0_MRCS2                    0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2 */
255 #define SPORT0_MRCS3                    0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3 */
256 
257 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
258 #define SPORT1_TCR1                             0xFFC00900      /* SPORT1 Transmit Configuration 1 Register */
259 #define SPORT1_TCR2                             0xFFC00904      /* SPORT1 Transmit Configuration 2 Register */
260 #define SPORT1_TCLKDIV                  0xFFC00908      /* SPORT1 Transmit Clock Divider */
261 #define SPORT1_TFSDIV                   0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider */
262 #define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register */
263 #define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register */
264 #define SPORT1_RCR1                             0xFFC00920      /* SPORT1 Transmit Configuration 1 Register */
265 #define SPORT1_RCR2                             0xFFC00924      /* SPORT1 Transmit Configuration 2 Register */
266 #define SPORT1_RCLKDIV                  0xFFC00928      /* SPORT1 Receive Clock Divider */
267 #define SPORT1_RFSDIV                   0xFFC0092C      /* SPORT1 Receive Frame Sync Divider */
268 #define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register */
269 #define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register */
270 #define SPORT1_MCMC1                    0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1 */
271 #define SPORT1_MCMC2                    0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2 */
272 #define SPORT1_MTCS0                    0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0 */
273 #define SPORT1_MTCS1                    0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1 */
274 #define SPORT1_MTCS2                    0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2 */
275 #define SPORT1_MTCS3                    0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3 */
276 #define SPORT1_MRCS0                    0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0 */
277 #define SPORT1_MRCS1                    0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1 */
278 #define SPORT1_MRCS2                    0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2 */
279 #define SPORT1_MRCS3                    0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3 */
280 
281 /* Asynchronous Memory Controller - External Bus Interface Unit  */
282 #define EBIU_AMGCTL                                     0xFFC00A00      /* Asynchronous Memory Global Control Register */
283 #define EBIU_AMBCTL0                            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0 */
284 #define EBIU_AMBCTL1                            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1 */
285 
286 /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
287 #define EBIU_SDGCTL                                     0xFFC00A10      /* SDRAM Global Control Register */
288 #define EBIU_SDBCTL                                     0xFFC00A14      /* SDRAM Bank Control Register */
289 #define EBIU_SDRRC                                      0xFFC00A18      /* SDRAM Refresh Rate Control Register */
290 #define EBIU_SDSTAT                                     0xFFC00A1C      /* SDRAM Status Register */
291 
292 /* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
293 #define PPI0_CONTROL                            0xFFC01000      /* PPI0 Control register */
294 #define PPI0_STATUS                             0xFFC01004      /* PPI0 Status register */
295 #define PPI0_COUNT                                      0xFFC01008      /* PPI0 Transfer Count register */
296 #define PPI0_DELAY                                      0xFFC0100C      /* PPI0 Delay Count register */
297 #define PPI0_FRAME                                      0xFFC01010      /* PPI0 Frame Length register */
298 
299 /*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
300 #define PPI1_CONTROL                            0xFFC01300      /* PPI1 Control register */
301 #define PPI1_STATUS                             0xFFC01304      /* PPI1 Status register */
302 #define PPI1_COUNT                                      0xFFC01308      /* PPI1 Transfer Count register */
303 #define PPI1_DELAY                                      0xFFC0130C      /* PPI1 Delay Count register */
304 #define PPI1_FRAME                                      0xFFC01310      /* PPI1 Frame Length register */
305 
306 /*DMA traffic control registers */
307 #define DMAC0_TC_PER  0xFFC00B0C        /* Traffic control periods */
308 #define DMAC0_TC_CNT  0xFFC00B10        /* Traffic control current counts        */
309 #define DMAC1_TC_PER  0xFFC01B0C        /* Traffic control periods */
310 #define DMAC1_TC_CNT  0xFFC01B10        /* Traffic control current counts */
311 
312 /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
313 #define DMA1_0_CONFIG 0xFFC01C08        /* DMA1 Channel 0 Configuration register */
314 #define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
315 #define DMA1_0_START_ADDR 0xFFC01C04    /* DMA1 Channel 0 Start Address */
316 #define DMA1_0_X_COUNT 0xFFC01C10       /* DMA1 Channel 0 Inner Loop Count */
317 #define DMA1_0_Y_COUNT 0xFFC01C18       /* DMA1 Channel 0 Outer Loop Count */
318 #define DMA1_0_X_MODIFY 0xFFC01C14      /* DMA1 Channel 0 Inner Loop Addr Increment */
319 #define DMA1_0_Y_MODIFY 0xFFC01C1C      /* DMA1 Channel 0 Outer Loop Addr Increment */
320 #define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
321 #define DMA1_0_CURR_ADDR 0xFFC01C24     /* DMA1 Channel 0 Current Address Pointer */
322 #define DMA1_0_CURR_X_COUNT 0xFFC01C30  /* DMA1 Channel 0 Current Inner Loop Count */
323 #define DMA1_0_CURR_Y_COUNT 0xFFC01C38  /* DMA1 Channel 0 Current Outer Loop Count */
324 #define DMA1_0_IRQ_STATUS 0xFFC01C28    /* DMA1 Channel 0 Interrupt/Status Register */
325 #define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C        /* DMA1 Channel 0 Peripheral Map Register */
326 
327 #define DMA1_1_CONFIG 0xFFC01C48        /* DMA1 Channel 1 Configuration register */
328 #define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
329 #define DMA1_1_START_ADDR 0xFFC01C44    /* DMA1 Channel 1 Start Address */
330 #define DMA1_1_X_COUNT 0xFFC01C50       /* DMA1 Channel 1 Inner Loop Count */
331 #define DMA1_1_Y_COUNT 0xFFC01C58       /* DMA1 Channel 1 Outer Loop Count */
332 #define DMA1_1_X_MODIFY 0xFFC01C54      /* DMA1 Channel 1 Inner Loop Addr Increment */
333 #define DMA1_1_Y_MODIFY 0xFFC01C5C      /* DMA1 Channel 1 Outer Loop Addr Increment */
334 #define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
335 #define DMA1_1_CURR_ADDR 0xFFC01C64     /* DMA1 Channel 1 Current Address Pointer */
336 #define DMA1_1_CURR_X_COUNT 0xFFC01C70  /* DMA1 Channel 1 Current Inner Loop Count */
337 #define DMA1_1_CURR_Y_COUNT 0xFFC01C78  /* DMA1 Channel 1 Current Outer Loop Count */
338 #define DMA1_1_IRQ_STATUS 0xFFC01C68    /* DMA1 Channel 1 Interrupt/Status Register */
339 #define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C        /* DMA1 Channel 1 Peripheral Map Register */
340 
341 #define DMA1_2_CONFIG 0xFFC01C88        /* DMA1 Channel 2 Configuration register */
342 #define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
343 #define DMA1_2_START_ADDR 0xFFC01C84    /* DMA1 Channel 2 Start Address */
344 #define DMA1_2_X_COUNT 0xFFC01C90       /* DMA1 Channel 2 Inner Loop Count */
345 #define DMA1_2_Y_COUNT 0xFFC01C98       /* DMA1 Channel 2 Outer Loop Count */
346 #define DMA1_2_X_MODIFY 0xFFC01C94      /* DMA1 Channel 2 Inner Loop Addr Increment */
347 #define DMA1_2_Y_MODIFY 0xFFC01C9C      /* DMA1 Channel 2 Outer Loop Addr Increment */
348 #define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
349 #define DMA1_2_CURR_ADDR 0xFFC01CA4     /* DMA1 Channel 2 Current Address Pointer */
350 #define DMA1_2_CURR_X_COUNT 0xFFC01CB0  /* DMA1 Channel 2 Current Inner Loop Count */
351 #define DMA1_2_CURR_Y_COUNT 0xFFC01CB8  /* DMA1 Channel 2 Current Outer Loop Count */
352 #define DMA1_2_IRQ_STATUS 0xFFC01CA8    /* DMA1 Channel 2 Interrupt/Status Register */
353 #define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC        /* DMA1 Channel 2 Peripheral Map Register */
354 
355 #define DMA1_3_CONFIG 0xFFC01CC8        /* DMA1 Channel 3 Configuration register */
356 #define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
357 #define DMA1_3_START_ADDR 0xFFC01CC4    /* DMA1 Channel 3 Start Address */
358 #define DMA1_3_X_COUNT 0xFFC01CD0       /* DMA1 Channel 3 Inner Loop Count */
359 #define DMA1_3_Y_COUNT 0xFFC01CD8       /* DMA1 Channel 3 Outer Loop Count */
360 #define DMA1_3_X_MODIFY 0xFFC01CD4      /* DMA1 Channel 3 Inner Loop Addr Increment */
361 #define DMA1_3_Y_MODIFY 0xFFC01CDC      /* DMA1 Channel 3 Outer Loop Addr Increment */
362 #define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
363 #define DMA1_3_CURR_ADDR 0xFFC01CE4     /* DMA1 Channel 3 Current Address Pointer */
364 #define DMA1_3_CURR_X_COUNT 0xFFC01CF0  /* DMA1 Channel 3 Current Inner Loop Count */
365 #define DMA1_3_CURR_Y_COUNT 0xFFC01CF8  /* DMA1 Channel 3 Current Outer Loop Count */
366 #define DMA1_3_IRQ_STATUS 0xFFC01CE8    /* DMA1 Channel 3 Interrupt/Status Register */
367 #define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC        /* DMA1 Channel 3 Peripheral Map Register */
368 
369 #define DMA1_4_CONFIG 0xFFC01D08        /* DMA1 Channel 4 Configuration register */
370 #define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
371 #define DMA1_4_START_ADDR 0xFFC01D04    /* DMA1 Channel 4 Start Address */
372 #define DMA1_4_X_COUNT 0xFFC01D10       /* DMA1 Channel 4 Inner Loop Count */
373 #define DMA1_4_Y_COUNT 0xFFC01D18       /* DMA1 Channel 4 Outer Loop Count */
374 #define DMA1_4_X_MODIFY 0xFFC01D14      /* DMA1 Channel 4 Inner Loop Addr Increment */
375 #define DMA1_4_Y_MODIFY 0xFFC01D1C      /* DMA1 Channel 4 Outer Loop Addr Increment */
376 #define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
377 #define DMA1_4_CURR_ADDR 0xFFC01D24     /* DMA1 Channel 4 Current Address Pointer */
378 #define DMA1_4_CURR_X_COUNT 0xFFC01D30  /* DMA1 Channel 4 Current Inner Loop Count */
379 #define DMA1_4_CURR_Y_COUNT 0xFFC01D38  /* DMA1 Channel 4 Current Outer Loop Count */
380 #define DMA1_4_IRQ_STATUS 0xFFC01D28    /* DMA1 Channel 4 Interrupt/Status Register */
381 #define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C        /* DMA1 Channel 4 Peripheral Map Register */
382 
383 #define DMA1_5_CONFIG 0xFFC01D48        /* DMA1 Channel 5 Configuration register */
384 #define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
385 #define DMA1_5_START_ADDR 0xFFC01D44    /* DMA1 Channel 5 Start Address */
386 #define DMA1_5_X_COUNT 0xFFC01D50       /* DMA1 Channel 5 Inner Loop Count */
387 #define DMA1_5_Y_COUNT 0xFFC01D58       /* DMA1 Channel 5 Outer Loop Count */
388 #define DMA1_5_X_MODIFY 0xFFC01D54      /* DMA1 Channel 5 Inner Loop Addr Increment */
389 #define DMA1_5_Y_MODIFY 0xFFC01D5C      /* DMA1 Channel 5 Outer Loop Addr Increment */
390 #define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
391 #define DMA1_5_CURR_ADDR 0xFFC01D64     /* DMA1 Channel 5 Current Address Pointer */
392 #define DMA1_5_CURR_X_COUNT 0xFFC01D70  /* DMA1 Channel 5 Current Inner Loop Count */
393 #define DMA1_5_CURR_Y_COUNT 0xFFC01D78  /* DMA1 Channel 5 Current Outer Loop Count */
394 #define DMA1_5_IRQ_STATUS 0xFFC01D68    /* DMA1 Channel 5 Interrupt/Status Register */
395 #define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C        /* DMA1 Channel 5 Peripheral Map Register */
396 
397 #define DMA1_6_CONFIG 0xFFC01D88        /* DMA1 Channel 6 Configuration register */
398 #define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
399 #define DMA1_6_START_ADDR 0xFFC01D84    /* DMA1 Channel 6 Start Address */
400 #define DMA1_6_X_COUNT 0xFFC01D90       /* DMA1 Channel 6 Inner Loop Count */
401 #define DMA1_6_Y_COUNT 0xFFC01D98       /* DMA1 Channel 6 Outer Loop Count */
402 #define DMA1_6_X_MODIFY 0xFFC01D94      /* DMA1 Channel 6 Inner Loop Addr Increment */
403 #define DMA1_6_Y_MODIFY 0xFFC01D9C      /* DMA1 Channel 6 Outer Loop Addr Increment */
404 #define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
405 #define DMA1_6_CURR_ADDR 0xFFC01DA4     /* DMA1 Channel 6 Current Address Pointer */
406 #define DMA1_6_CURR_X_COUNT 0xFFC01DB0  /* DMA1 Channel 6 Current Inner Loop Count */
407 #define DMA1_6_CURR_Y_COUNT 0xFFC01DB8  /* DMA1 Channel 6 Current Outer Loop Count */
408 #define DMA1_6_IRQ_STATUS 0xFFC01DA8    /* DMA1 Channel 6 Interrupt/Status Register */
409 #define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC        /* DMA1 Channel 6 Peripheral Map Register */
410 
411 #define DMA1_7_CONFIG 0xFFC01DC8        /* DMA1 Channel 7 Configuration register */
412 #define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
413 #define DMA1_7_START_ADDR 0xFFC01DC4    /* DMA1 Channel 7 Start Address */
414 #define DMA1_7_X_COUNT 0xFFC01DD0       /* DMA1 Channel 7 Inner Loop Count */
415 #define DMA1_7_Y_COUNT 0xFFC01DD8       /* DMA1 Channel 7 Outer Loop Count */
416 #define DMA1_7_X_MODIFY 0xFFC01DD4      /* DMA1 Channel 7 Inner Loop Addr Increment */
417 #define DMA1_7_Y_MODIFY 0xFFC01DDC      /* DMA1 Channel 7 Outer Loop Addr Increment */
418 #define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
419 #define DMA1_7_CURR_ADDR 0xFFC01DE4     /* DMA1 Channel 7 Current Address Pointer */
420 #define DMA1_7_CURR_X_COUNT 0xFFC01DF0  /* DMA1 Channel 7 Current Inner Loop Count */
421 #define DMA1_7_CURR_Y_COUNT 0xFFC01DF8  /* DMA1 Channel 7 Current Outer Loop Count */
422 #define DMA1_7_IRQ_STATUS 0xFFC01DE8    /* DMA1 Channel 7 Interrupt/Status Register */
423 #define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC        /* DMA1 Channel 7 Peripheral Map Register */
424 
425 #define DMA1_8_CONFIG 0xFFC01E08        /* DMA1 Channel 8 Configuration register */
426 #define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
427 #define DMA1_8_START_ADDR 0xFFC01E04    /* DMA1 Channel 8 Start Address */
428 #define DMA1_8_X_COUNT 0xFFC01E10       /* DMA1 Channel 8 Inner Loop Count */
429 #define DMA1_8_Y_COUNT 0xFFC01E18       /* DMA1 Channel 8 Outer Loop Count */
430 #define DMA1_8_X_MODIFY 0xFFC01E14      /* DMA1 Channel 8 Inner Loop Addr Increment */
431 #define DMA1_8_Y_MODIFY 0xFFC01E1C      /* DMA1 Channel 8 Outer Loop Addr Increment */
432 #define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
433 #define DMA1_8_CURR_ADDR 0xFFC01E24     /* DMA1 Channel 8 Current Address Pointer */
434 #define DMA1_8_CURR_X_COUNT 0xFFC01E30  /* DMA1 Channel 8 Current Inner Loop Count */
435 #define DMA1_8_CURR_Y_COUNT 0xFFC01E38  /* DMA1 Channel 8 Current Outer Loop Count */
436 #define DMA1_8_IRQ_STATUS 0xFFC01E28    /* DMA1 Channel 8 Interrupt/Status Register */
437 #define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C        /* DMA1 Channel 8 Peripheral Map Register */
438 
439 #define DMA1_9_CONFIG 0xFFC01E48        /* DMA1 Channel 9 Configuration register */
440 #define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
441 #define DMA1_9_START_ADDR 0xFFC01E44    /* DMA1 Channel 9 Start Address */
442 #define DMA1_9_X_COUNT 0xFFC01E50       /* DMA1 Channel 9 Inner Loop Count */
443 #define DMA1_9_Y_COUNT 0xFFC01E58       /* DMA1 Channel 9 Outer Loop Count */
444 #define DMA1_9_X_MODIFY 0xFFC01E54      /* DMA1 Channel 9 Inner Loop Addr Increment */
445 #define DMA1_9_Y_MODIFY 0xFFC01E5C      /* DMA1 Channel 9 Outer Loop Addr Increment */
446 #define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
447 #define DMA1_9_CURR_ADDR 0xFFC01E64     /* DMA1 Channel 9 Current Address Pointer */
448 #define DMA1_9_CURR_X_COUNT 0xFFC01E70  /* DMA1 Channel 9 Current Inner Loop Count */
449 #define DMA1_9_CURR_Y_COUNT 0xFFC01E78  /* DMA1 Channel 9 Current Outer Loop Count */
450 #define DMA1_9_IRQ_STATUS 0xFFC01E68    /* DMA1 Channel 9 Interrupt/Status Register */
451 #define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C        /* DMA1 Channel 9 Peripheral Map Register */
452 
453 #define DMA1_10_CONFIG 0xFFC01E88       /* DMA1 Channel 10 Configuration register */
454 #define DMA1_10_NEXT_DESC_PTR 0xFFC01E80        /* DMA1 Channel 10 Next Descripter Ptr Reg */
455 #define DMA1_10_START_ADDR 0xFFC01E84   /* DMA1 Channel 10 Start Address */
456 #define DMA1_10_X_COUNT 0xFFC01E90      /* DMA1 Channel 10 Inner Loop Count */
457 #define DMA1_10_Y_COUNT 0xFFC01E98      /* DMA1 Channel 10 Outer Loop Count */
458 #define DMA1_10_X_MODIFY 0xFFC01E94     /* DMA1 Channel 10 Inner Loop Addr Increment */
459 #define DMA1_10_Y_MODIFY 0xFFC01E9C     /* DMA1 Channel 10 Outer Loop Addr Increment */
460 #define DMA1_10_CURR_DESC_PTR 0xFFC01EA0        /* DMA1 Channel 10 Current Descriptor Pointer */
461 #define DMA1_10_CURR_ADDR 0xFFC01EA4    /* DMA1 Channel 10 Current Address Pointer */
462 #define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
463 #define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
464 #define DMA1_10_IRQ_STATUS 0xFFC01EA8   /* DMA1 Channel 10 Interrupt/Status Register */
465 #define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC       /* DMA1 Channel 10 Peripheral Map Register */
466 
467 #define DMA1_11_CONFIG 0xFFC01EC8       /* DMA1 Channel 11 Configuration register */
468 #define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0        /* DMA1 Channel 11 Next Descripter Ptr Reg */
469 #define DMA1_11_START_ADDR 0xFFC01EC4   /* DMA1 Channel 11 Start Address */
470 #define DMA1_11_X_COUNT 0xFFC01ED0      /* DMA1 Channel 11 Inner Loop Count */
471 #define DMA1_11_Y_COUNT 0xFFC01ED8      /* DMA1 Channel 11 Outer Loop Count */
472 #define DMA1_11_X_MODIFY 0xFFC01ED4     /* DMA1 Channel 11 Inner Loop Addr Increment */
473 #define DMA1_11_Y_MODIFY 0xFFC01EDC     /* DMA1 Channel 11 Outer Loop Addr Increment */
474 #define DMA1_11_CURR_DESC_PTR 0xFFC01EE0        /* DMA1 Channel 11 Current Descriptor Pointer */
475 #define DMA1_11_CURR_ADDR 0xFFC01EE4    /* DMA1 Channel 11 Current Address Pointer */
476 #define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
477 #define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
478 #define DMA1_11_IRQ_STATUS 0xFFC01EE8   /* DMA1 Channel 11 Interrupt/Status Register */
479 #define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC       /* DMA1 Channel 11 Peripheral Map Register */
480 
481 /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
482 #define MDMA_D0_CONFIG 0xFFC01F08       /*MemDMA1 Stream 0 Destination Configuration */
483 #define MDMA_D0_NEXT_DESC_PTR 0xFFC01F00        /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
484 #define MDMA_D0_START_ADDR 0xFFC01F04   /*MemDMA1 Stream 0 Destination Start Address */
485 #define MDMA_D0_X_COUNT 0xFFC01F10      /*MemDMA1 Stream 0 Destination Inner-Loop Count */
486 #define MDMA_D0_Y_COUNT 0xFFC01F18      /*MemDMA1 Stream 0 Destination Outer-Loop Count */
487 #define MDMA_D0_X_MODIFY 0xFFC01F14     /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
488 #define MDMA_D0_Y_MODIFY 0xFFC01F1C     /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
489 #define MDMA_D0_CURR_DESC_PTR 0xFFC01F20        /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
490 #define MDMA_D0_CURR_ADDR 0xFFC01F24    /*MemDMA1 Stream 0 Destination Current Address */
491 #define MDMA_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
492 #define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
493 #define MDMA_D0_IRQ_STATUS 0xFFC01F28   /*MemDMA1 Stream 0 Destination Interrupt/Status */
494 #define MDMA_D0_PERIPHERAL_MAP 0xFFC01F2C       /*MemDMA1 Stream 0 Destination Peripheral Map */
495 
496 #define MDMA_S0_CONFIG 0xFFC01F48       /*MemDMA1 Stream 0 Source Configuration */
497 #define MDMA_S0_NEXT_DESC_PTR 0xFFC01F40        /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
498 #define MDMA_S0_START_ADDR 0xFFC01F44   /*MemDMA1 Stream 0 Source Start Address */
499 #define MDMA_S0_X_COUNT 0xFFC01F50      /*MemDMA1 Stream 0 Source Inner-Loop Count */
500 #define MDMA_S0_Y_COUNT 0xFFC01F58      /*MemDMA1 Stream 0 Source Outer-Loop Count */
501 #define MDMA_S0_X_MODIFY 0xFFC01F54     /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
502 #define MDMA_S0_Y_MODIFY 0xFFC01F5C     /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
503 #define MDMA_S0_CURR_DESC_PTR 0xFFC01F60        /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
504 #define MDMA_S0_CURR_ADDR 0xFFC01F64    /*MemDMA1 Stream 0 Source Current Address */
505 #define MDMA_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
506 #define MDMA_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
507 #define MDMA_S0_IRQ_STATUS 0xFFC01F68   /*MemDMA1 Stream 0 Source Interrupt/Status */
508 #define MDMA_S0_PERIPHERAL_MAP 0xFFC01F6C       /*MemDMA1 Stream 0 Source Peripheral Map */
509 
510 #define MDMA_D1_CONFIG 0xFFC01F88       /*MemDMA1 Stream 1 Destination Configuration */
511 #define MDMA_D1_NEXT_DESC_PTR 0xFFC01F80        /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
512 #define MDMA_D1_START_ADDR 0xFFC01F84   /*MemDMA1 Stream 1 Destination Start Address */
513 #define MDMA_D1_X_COUNT 0xFFC01F90      /*MemDMA1 Stream 1 Destination Inner-Loop Count */
514 #define MDMA_D1_Y_COUNT 0xFFC01F98      /*MemDMA1 Stream 1 Destination Outer-Loop Count */
515 #define MDMA_D1_X_MODIFY 0xFFC01F94     /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
516 #define MDMA_D1_Y_MODIFY 0xFFC01F9C     /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
517 #define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0        /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
518 #define MDMA_D1_CURR_ADDR 0xFFC01FA4    /*MemDMA1 Stream 1 Dest Current Address */
519 #define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
520 #define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
521 #define MDMA_D1_IRQ_STATUS 0xFFC01FA8   /*MemDMA1 Stream 1 Dest Interrupt/Status */
522 #define MDMA_D1_PERIPHERAL_MAP 0xFFC01FAC       /*MemDMA1 Stream 1 Dest Peripheral Map */
523 
524 #define MDMA_S1_CONFIG 0xFFC01FC8       /*MemDMA1 Stream 1 Source Configuration */
525 #define MDMA_S1_NEXT_DESC_PTR 0xFFC01FC0        /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
526 #define MDMA_S1_START_ADDR 0xFFC01FC4   /*MemDMA1 Stream 1 Source Start Address */
527 #define MDMA_S1_X_COUNT 0xFFC01FD0      /*MemDMA1 Stream 1 Source Inner-Loop Count */
528 #define MDMA_S1_Y_COUNT 0xFFC01FD8      /*MemDMA1 Stream 1 Source Outer-Loop Count */
529 #define MDMA_S1_X_MODIFY 0xFFC01FD4     /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
530 #define MDMA_S1_Y_MODIFY 0xFFC01FDC     /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
531 #define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0        /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
532 #define MDMA_S1_CURR_ADDR 0xFFC01FE4    /*MemDMA1 Stream 1 Source Current Address */
533 #define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
534 #define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
535 #define MDMA_S1_IRQ_STATUS 0xFFC01FE8   /*MemDMA1 Stream 1 Source Interrupt/Status */
536 #define MDMA_S1_PERIPHERAL_MAP 0xFFC01FEC       /*MemDMA1 Stream 1 Source Peripheral Map */
537 
538 /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
539 #define DMA2_0_CONFIG 0xFFC00C08        /* DMA2 Channel 0 Configuration register */
540 #define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
541 #define DMA2_0_START_ADDR 0xFFC00C04    /* DMA2 Channel 0 Start Address */
542 #define DMA2_0_X_COUNT 0xFFC00C10       /* DMA2 Channel 0 Inner Loop Count */
543 #define DMA2_0_Y_COUNT 0xFFC00C18       /* DMA2 Channel 0 Outer Loop Count */
544 #define DMA2_0_X_MODIFY 0xFFC00C14      /* DMA2 Channel 0 Inner Loop Addr Increment */
545 #define DMA2_0_Y_MODIFY 0xFFC00C1C      /* DMA2 Channel 0 Outer Loop Addr Increment */
546 #define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
547 #define DMA2_0_CURR_ADDR 0xFFC00C24     /* DMA2 Channel 0 Current Address Pointer */
548 #define DMA2_0_CURR_X_COUNT 0xFFC00C30  /* DMA2 Channel 0 Current Inner Loop Count */
549 #define DMA2_0_CURR_Y_COUNT 0xFFC00C38  /* DMA2 Channel 0 Current Outer Loop Count */
550 #define DMA2_0_IRQ_STATUS 0xFFC00C28    /* DMA2 Channel 0 Interrupt/Status Register */
551 #define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C        /* DMA2 Channel 0 Peripheral Map Register */
552 
553 #define DMA2_1_CONFIG 0xFFC00C48        /* DMA2 Channel 1 Configuration register */
554 #define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
555 #define DMA2_1_START_ADDR 0xFFC00C44    /* DMA2 Channel 1 Start Address */
556 #define DMA2_1_X_COUNT 0xFFC00C50       /* DMA2 Channel 1 Inner Loop Count */
557 #define DMA2_1_Y_COUNT 0xFFC00C58       /* DMA2 Channel 1 Outer Loop Count */
558 #define DMA2_1_X_MODIFY 0xFFC00C54      /* DMA2 Channel 1 Inner Loop Addr Increment */
559 #define DMA2_1_Y_MODIFY 0xFFC00C5C      /* DMA2 Channel 1 Outer Loop Addr Increment */
560 #define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
561 #define DMA2_1_CURR_ADDR 0xFFC00C64     /* DMA2 Channel 1 Current Address Pointer */
562 #define DMA2_1_CURR_X_COUNT 0xFFC00C70  /* DMA2 Channel 1 Current Inner Loop Count */
563 #define DMA2_1_CURR_Y_COUNT 0xFFC00C78  /* DMA2 Channel 1 Current Outer Loop Count */
564 #define DMA2_1_IRQ_STATUS 0xFFC00C68    /* DMA2 Channel 1 Interrupt/Status Register */
565 #define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C        /* DMA2 Channel 1 Peripheral Map Register */
566 
567 #define DMA2_2_CONFIG 0xFFC00C88        /* DMA2 Channel 2 Configuration register */
568 #define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
569 #define DMA2_2_START_ADDR 0xFFC00C84    /* DMA2 Channel 2 Start Address */
570 #define DMA2_2_X_COUNT 0xFFC00C90       /* DMA2 Channel 2 Inner Loop Count */
571 #define DMA2_2_Y_COUNT 0xFFC00C98       /* DMA2 Channel 2 Outer Loop Count */
572 #define DMA2_2_X_MODIFY 0xFFC00C94      /* DMA2 Channel 2 Inner Loop Addr Increment */
573 #define DMA2_2_Y_MODIFY 0xFFC00C9C      /* DMA2 Channel 2 Outer Loop Addr Increment */
574 #define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
575 #define DMA2_2_CURR_ADDR 0xFFC00CA4     /* DMA2 Channel 2 Current Address Pointer */
576 #define DMA2_2_CURR_X_COUNT 0xFFC00CB0  /* DMA2 Channel 2 Current Inner Loop Count */
577 #define DMA2_2_CURR_Y_COUNT 0xFFC00CB8  /* DMA2 Channel 2 Current Outer Loop Count */
578 #define DMA2_2_IRQ_STATUS 0xFFC00CA8    /* DMA2 Channel 2 Interrupt/Status Register */
579 #define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC        /* DMA2 Channel 2 Peripheral Map Register */
580 
581 #define DMA2_3_CONFIG 0xFFC00CC8        /* DMA2 Channel 3 Configuration register */
582 #define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
583 #define DMA2_3_START_ADDR 0xFFC00CC4    /* DMA2 Channel 3 Start Address */
584 #define DMA2_3_X_COUNT 0xFFC00CD0       /* DMA2 Channel 3 Inner Loop Count */
585 #define DMA2_3_Y_COUNT 0xFFC00CD8       /* DMA2 Channel 3 Outer Loop Count */
586 #define DMA2_3_X_MODIFY 0xFFC00CD4      /* DMA2 Channel 3 Inner Loop Addr Increment */
587 #define DMA2_3_Y_MODIFY 0xFFC00CDC      /* DMA2 Channel 3 Outer Loop Addr Increment */
588 #define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
589 #define DMA2_3_CURR_ADDR 0xFFC00CE4     /* DMA2 Channel 3 Current Address Pointer */
590 #define DMA2_3_CURR_X_COUNT 0xFFC00CF0  /* DMA2 Channel 3 Current Inner Loop Count */
591 #define DMA2_3_CURR_Y_COUNT 0xFFC00CF8  /* DMA2 Channel 3 Current Outer Loop Count */
592 #define DMA2_3_IRQ_STATUS 0xFFC00CE8    /* DMA2 Channel 3 Interrupt/Status Register */
593 #define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC        /* DMA2 Channel 3 Peripheral Map Register */
594 
595 #define DMA2_4_CONFIG 0xFFC00D08        /* DMA2 Channel 4 Configuration register */
596 #define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
597 #define DMA2_4_START_ADDR 0xFFC00D04    /* DMA2 Channel 4 Start Address */
598 #define DMA2_4_X_COUNT 0xFFC00D10       /* DMA2 Channel 4 Inner Loop Count */
599 #define DMA2_4_Y_COUNT 0xFFC00D18       /* DMA2 Channel 4 Outer Loop Count */
600 #define DMA2_4_X_MODIFY 0xFFC00D14      /* DMA2 Channel 4 Inner Loop Addr Increment */
601 #define DMA2_4_Y_MODIFY 0xFFC00D1C      /* DMA2 Channel 4 Outer Loop Addr Increment */
602 #define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
603 #define DMA2_4_CURR_ADDR 0xFFC00D24     /* DMA2 Channel 4 Current Address Pointer */
604 #define DMA2_4_CURR_X_COUNT 0xFFC00D30  /* DMA2 Channel 4 Current Inner Loop Count */
605 #define DMA2_4_CURR_Y_COUNT 0xFFC00D38  /* DMA2 Channel 4 Current Outer Loop Count */
606 #define DMA2_4_IRQ_STATUS 0xFFC00D28    /* DMA2 Channel 4 Interrupt/Status Register */
607 #define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C        /* DMA2 Channel 4 Peripheral Map Register */
608 
609 #define DMA2_5_CONFIG 0xFFC00D48        /* DMA2 Channel 5 Configuration register */
610 #define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
611 #define DMA2_5_START_ADDR 0xFFC00D44    /* DMA2 Channel 5 Start Address */
612 #define DMA2_5_X_COUNT 0xFFC00D50       /* DMA2 Channel 5 Inner Loop Count */
613 #define DMA2_5_Y_COUNT 0xFFC00D58       /* DMA2 Channel 5 Outer Loop Count */
614 #define DMA2_5_X_MODIFY 0xFFC00D54      /* DMA2 Channel 5 Inner Loop Addr Increment */
615 #define DMA2_5_Y_MODIFY 0xFFC00D5C      /* DMA2 Channel 5 Outer Loop Addr Increment */
616 #define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
617 #define DMA2_5_CURR_ADDR 0xFFC00D64     /* DMA2 Channel 5 Current Address Pointer */
618 #define DMA2_5_CURR_X_COUNT 0xFFC00D70  /* DMA2 Channel 5 Current Inner Loop Count */
619 #define DMA2_5_CURR_Y_COUNT 0xFFC00D78  /* DMA2 Channel 5 Current Outer Loop Count */
620 #define DMA2_5_IRQ_STATUS 0xFFC00D68    /* DMA2 Channel 5 Interrupt/Status Register */
621 #define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C        /* DMA2 Channel 5 Peripheral Map Register */
622 
623 #define DMA2_6_CONFIG 0xFFC00D88        /* DMA2 Channel 6 Configuration register */
624 #define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
625 #define DMA2_6_START_ADDR 0xFFC00D84    /* DMA2 Channel 6 Start Address */
626 #define DMA2_6_X_COUNT 0xFFC00D90       /* DMA2 Channel 6 Inner Loop Count */
627 #define DMA2_6_Y_COUNT 0xFFC00D98       /* DMA2 Channel 6 Outer Loop Count */
628 #define DMA2_6_X_MODIFY 0xFFC00D94      /* DMA2 Channel 6 Inner Loop Addr Increment */
629 #define DMA2_6_Y_MODIFY 0xFFC00D9C      /* DMA2 Channel 6 Outer Loop Addr Increment */
630 #define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
631 #define DMA2_6_CURR_ADDR 0xFFC00DA4     /* DMA2 Channel 6 Current Address Pointer */
632 #define DMA2_6_CURR_X_COUNT 0xFFC00DB0  /* DMA2 Channel 6 Current Inner Loop Count */
633 #define DMA2_6_CURR_Y_COUNT 0xFFC00DB8  /* DMA2 Channel 6 Current Outer Loop Count */
634 #define DMA2_6_IRQ_STATUS 0xFFC00DA8    /* DMA2 Channel 6 Interrupt/Status Register */
635 #define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC        /* DMA2 Channel 6 Peripheral Map Register */
636 
637 #define DMA2_7_CONFIG 0xFFC00DC8        /* DMA2 Channel 7 Configuration register */
638 #define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
639 #define DMA2_7_START_ADDR 0xFFC00DC4    /* DMA2 Channel 7 Start Address */
640 #define DMA2_7_X_COUNT 0xFFC00DD0       /* DMA2 Channel 7 Inner Loop Count */
641 #define DMA2_7_Y_COUNT 0xFFC00DD8       /* DMA2 Channel 7 Outer Loop Count */
642 #define DMA2_7_X_MODIFY 0xFFC00DD4      /* DMA2 Channel 7 Inner Loop Addr Increment */
643 #define DMA2_7_Y_MODIFY 0xFFC00DDC      /* DMA2 Channel 7 Outer Loop Addr Increment */
644 #define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
645 #define DMA2_7_CURR_ADDR 0xFFC00DE4     /* DMA2 Channel 7 Current Address Pointer */
646 #define DMA2_7_CURR_X_COUNT 0xFFC00DF0  /* DMA2 Channel 7 Current Inner Loop Count */
647 #define DMA2_7_CURR_Y_COUNT 0xFFC00DF8  /* DMA2 Channel 7 Current Outer Loop Count */
648 #define DMA2_7_IRQ_STATUS 0xFFC00DE8    /* DMA2 Channel 7 Interrupt/Status Register */
649 #define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC        /* DMA2 Channel 7 Peripheral Map Register */
650 
651 #define DMA2_8_CONFIG 0xFFC00E08        /* DMA2 Channel 8 Configuration register */
652 #define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
653 #define DMA2_8_START_ADDR 0xFFC00E04    /* DMA2 Channel 8 Start Address */
654 #define DMA2_8_X_COUNT 0xFFC00E10       /* DMA2 Channel 8 Inner Loop Count */
655 #define DMA2_8_Y_COUNT 0xFFC00E18       /* DMA2 Channel 8 Outer Loop Count */
656 #define DMA2_8_X_MODIFY 0xFFC00E14      /* DMA2 Channel 8 Inner Loop Addr Increment */
657 #define DMA2_8_Y_MODIFY 0xFFC00E1C      /* DMA2 Channel 8 Outer Loop Addr Increment */
658 #define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
659 #define DMA2_8_CURR_ADDR 0xFFC00E24     /* DMA2 Channel 8 Current Address Pointer */
660 #define DMA2_8_CURR_X_COUNT 0xFFC00E30  /* DMA2 Channel 8 Current Inner Loop Count */
661 #define DMA2_8_CURR_Y_COUNT 0xFFC00E38  /* DMA2 Channel 8 Current Outer Loop Count */
662 #define DMA2_8_IRQ_STATUS 0xFFC00E28    /* DMA2 Channel 8 Interrupt/Status Register */
663 #define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C        /* DMA2 Channel 8 Peripheral Map Register */
664 
665 #define DMA2_9_CONFIG 0xFFC00E48        /* DMA2 Channel 9 Configuration register */
666 #define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
667 #define DMA2_9_START_ADDR 0xFFC00E44    /* DMA2 Channel 9 Start Address */
668 #define DMA2_9_X_COUNT 0xFFC00E50       /* DMA2 Channel 9 Inner Loop Count */
669 #define DMA2_9_Y_COUNT 0xFFC00E58       /* DMA2 Channel 9 Outer Loop Count */
670 #define DMA2_9_X_MODIFY 0xFFC00E54      /* DMA2 Channel 9 Inner Loop Addr Increment */
671 #define DMA2_9_Y_MODIFY 0xFFC00E5C      /* DMA2 Channel 9 Outer Loop Addr Increment */
672 #define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
673 #define DMA2_9_CURR_ADDR 0xFFC00E64     /* DMA2 Channel 9 Current Address Pointer */
674 #define DMA2_9_CURR_X_COUNT 0xFFC00E70  /* DMA2 Channel 9 Current Inner Loop Count */
675 #define DMA2_9_CURR_Y_COUNT 0xFFC00E78  /* DMA2 Channel 9 Current Outer Loop Count */
676 #define DMA2_9_IRQ_STATUS 0xFFC00E68    /* DMA2 Channel 9 Interrupt/Status Register */
677 #define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C        /* DMA2 Channel 9 Peripheral Map Register */
678 
679 #define DMA2_10_CONFIG 0xFFC00E88       /* DMA2 Channel 10 Configuration register */
680 #define DMA2_10_NEXT_DESC_PTR 0xFFC00E80        /* DMA2 Channel 10 Next Descripter Ptr Reg */
681 #define DMA2_10_START_ADDR 0xFFC00E84   /* DMA2 Channel 10 Start Address */
682 #define DMA2_10_X_COUNT 0xFFC00E90      /* DMA2 Channel 10 Inner Loop Count */
683 #define DMA2_10_Y_COUNT 0xFFC00E98      /* DMA2 Channel 10 Outer Loop Count */
684 #define DMA2_10_X_MODIFY 0xFFC00E94     /* DMA2 Channel 10 Inner Loop Addr Increment */
685 #define DMA2_10_Y_MODIFY 0xFFC00E9C     /* DMA2 Channel 10 Outer Loop Addr Increment */
686 #define DMA2_10_CURR_DESC_PTR 0xFFC00EA0        /* DMA2 Channel 10 Current Descriptor Pointer */
687 #define DMA2_10_CURR_ADDR 0xFFC00EA4    /* DMA2 Channel 10 Current Address Pointer */
688 #define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
689 #define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
690 #define DMA2_10_IRQ_STATUS 0xFFC00EA8   /* DMA2 Channel 10 Interrupt/Status Register */
691 #define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC       /* DMA2 Channel 10 Peripheral Map Register */
692 
693 #define DMA2_11_CONFIG 0xFFC00EC8       /* DMA2 Channel 11 Configuration register */
694 #define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0        /* DMA2 Channel 11 Next Descripter Ptr Reg */
695 #define DMA2_11_START_ADDR 0xFFC00EC4   /* DMA2 Channel 11 Start Address */
696 #define DMA2_11_X_COUNT 0xFFC00ED0      /* DMA2 Channel 11 Inner Loop Count */
697 #define DMA2_11_Y_COUNT 0xFFC00ED8      /* DMA2 Channel 11 Outer Loop Count */
698 #define DMA2_11_X_MODIFY 0xFFC00ED4     /* DMA2 Channel 11 Inner Loop Addr Increment */
699 #define DMA2_11_Y_MODIFY 0xFFC00EDC     /* DMA2 Channel 11 Outer Loop Addr Increment */
700 #define DMA2_11_CURR_DESC_PTR 0xFFC00EE0        /* DMA2 Channel 11 Current Descriptor Pointer */
701 #define DMA2_11_CURR_ADDR 0xFFC00EE4    /* DMA2 Channel 11 Current Address Pointer */
702 #define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
703 #define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
704 #define DMA2_11_IRQ_STATUS 0xFFC00EE8   /* DMA2 Channel 11 Interrupt/Status Register */
705 #define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC       /* DMA2 Channel 11 Peripheral Map Register */
706 
707 /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
708 #define MDMA_D2_CONFIG 0xFFC00F08       /*MemDMA2 Stream 0 Destination Configuration register */
709 #define MDMA_D2_NEXT_DESC_PTR 0xFFC00F00        /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
710 #define MDMA_D2_START_ADDR 0xFFC00F04   /*MemDMA2 Stream 0 Destination Start Address */
711 #define MDMA_D2_X_COUNT 0xFFC00F10      /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
712 #define MDMA_D2_Y_COUNT 0xFFC00F18      /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
713 #define MDMA_D2_X_MODIFY 0xFFC00F14     /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
714 #define MDMA_D2_Y_MODIFY 0xFFC00F1C     /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
715 #define MDMA_D2_CURR_DESC_PTR 0xFFC00F20        /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
716 #define MDMA_D2_CURR_ADDR 0xFFC00F24    /*MemDMA2 Stream 0 Destination Current Address */
717 #define MDMA_D2_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
718 #define MDMA_D2_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
719 #define MDMA_D2_IRQ_STATUS 0xFFC00F28   /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
720 #define MDMA_D2_PERIPHERAL_MAP 0xFFC00F2C       /*MemDMA2 Stream 0 Destination Peripheral Map register */
721 
722 #define MDMA_S2_CONFIG 0xFFC00F48       /*MemDMA2 Stream 0 Source Configuration register */
723 #define MDMA_S2_NEXT_DESC_PTR 0xFFC00F40        /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
724 #define MDMA_S2_START_ADDR 0xFFC00F44   /*MemDMA2 Stream 0 Source Start Address */
725 #define MDMA_S2_X_COUNT 0xFFC00F50      /*MemDMA2 Stream 0 Source Inner-Loop Count register */
726 #define MDMA_S2_Y_COUNT 0xFFC00F58      /*MemDMA2 Stream 0 Source Outer-Loop Count register */
727 #define MDMA_S2_X_MODIFY 0xFFC00F54     /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
728 #define MDMA_S2_Y_MODIFY 0xFFC00F5C     /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
729 #define MDMA_S2_CURR_DESC_PTR 0xFFC00F60        /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
730 #define MDMA_S2_CURR_ADDR 0xFFC00F64    /*MemDMA2 Stream 0 Source Current Address */
731 #define MDMA_S2_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
732 #define MDMA_S2_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
733 #define MDMA_S2_IRQ_STATUS 0xFFC00F68   /*MemDMA2 Stream 0 Source Interrupt/Status Register */
734 #define MDMA_S2_PERIPHERAL_MAP 0xFFC00F6C       /*MemDMA2 Stream 0 Source Peripheral Map register */
735 
736 #define MDMA_D3_CONFIG 0xFFC00F88       /*MemDMA2 Stream 1 Destination Configuration register */
737 #define MDMA_D3_NEXT_DESC_PTR 0xFFC00F80        /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
738 #define MDMA_D3_START_ADDR 0xFFC00F84   /*MemDMA2 Stream 1 Destination Start Address */
739 #define MDMA_D3_X_COUNT 0xFFC00F90      /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
740 #define MDMA_D3_Y_COUNT 0xFFC00F98      /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
741 #define MDMA_D3_X_MODIFY 0xFFC00F94     /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
742 #define MDMA_D3_Y_MODIFY 0xFFC00F9C     /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
743 #define MDMA_D3_CURR_DESC_PTR 0xFFC00FA0        /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
744 #define MDMA_D3_CURR_ADDR 0xFFC00FA4    /*MemDMA2 Stream 1 Destination Current Address reg */
745 #define MDMA_D3_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
746 #define MDMA_D3_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
747 #define MDMA_D3_IRQ_STATUS 0xFFC00FA8   /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
748 #define MDMA_D3_PERIPHERAL_MAP 0xFFC00FAC       /*MemDMA2 Stream 1 Destination Peripheral Map register */
749 
750 #define MDMA_S3_CONFIG 0xFFC00FC8       /*MemDMA2 Stream 1 Source Configuration register */
751 #define MDMA_S3_NEXT_DESC_PTR 0xFFC00FC0        /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
752 #define MDMA_S3_START_ADDR 0xFFC00FC4   /*MemDMA2 Stream 1 Source Start Address */
753 #define MDMA_S3_X_COUNT 0xFFC00FD0      /*MemDMA2 Stream 1 Source Inner-Loop Count register */
754 #define MDMA_S3_Y_COUNT 0xFFC00FD8      /*MemDMA2 Stream 1 Source Outer-Loop Count register */
755 #define MDMA_S3_X_MODIFY 0xFFC00FD4     /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
756 #define MDMA_S3_Y_MODIFY 0xFFC00FDC     /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
757 #define MDMA_S3_CURR_DESC_PTR 0xFFC00FE0        /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
758 #define MDMA_S3_CURR_ADDR 0xFFC00FE4    /*MemDMA2 Stream 1 Source Current Address */
759 #define MDMA_S3_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
760 #define MDMA_S3_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
761 #define MDMA_S3_IRQ_STATUS 0xFFC00FE8   /*MemDMA2 Stream 1 Source Interrupt/Status Register */
762 #define MDMA_S3_PERIPHERAL_MAP 0xFFC00FEC       /*MemDMA2 Stream 1 Source Peripheral Map register */
763 
764 /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
765 #define IMDMA_D0_CONFIG 0xFFC01808      /*IMDMA Stream 0 Destination Configuration */
766 #define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800       /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
767 #define IMDMA_D0_START_ADDR 0xFFC01804  /*IMDMA Stream 0 Destination Start Address */
768 #define IMDMA_D0_X_COUNT 0xFFC01810     /*IMDMA Stream 0 Destination Inner-Loop Count */
769 #define IMDMA_D0_Y_COUNT 0xFFC01818     /*IMDMA Stream 0 Destination Outer-Loop Count */
770 #define IMDMA_D0_X_MODIFY 0xFFC01814    /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
771 #define IMDMA_D0_Y_MODIFY 0xFFC0181C    /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
772 #define IMDMA_D0_CURR_DESC_PTR 0xFFC01820       /*IMDMA Stream 0 Destination Current Descriptor Ptr */
773 #define IMDMA_D0_CURR_ADDR 0xFFC01824   /*IMDMA Stream 0 Destination Current Address */
774 #define IMDMA_D0_CURR_X_COUNT 0xFFC01830        /*IMDMA Stream 0 Destination Current Inner-Loop Count */
775 #define IMDMA_D0_CURR_Y_COUNT 0xFFC01838        /*IMDMA Stream 0 Destination Current Outer-Loop Count */
776 #define IMDMA_D0_IRQ_STATUS 0xFFC01828  /*IMDMA Stream 0 Destination Interrupt/Status */
777 
778 #define IMDMA_S0_CONFIG 0xFFC01848      /*IMDMA Stream 0 Source Configuration */
779 #define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840       /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
780 #define IMDMA_S0_START_ADDR 0xFFC01844  /*IMDMA Stream 0 Source Start Address */
781 #define IMDMA_S0_X_COUNT 0xFFC01850     /*IMDMA Stream 0 Source Inner-Loop Count */
782 #define IMDMA_S0_Y_COUNT 0xFFC01858     /*IMDMA Stream 0 Source Outer-Loop Count */
783 #define IMDMA_S0_X_MODIFY 0xFFC01854    /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
784 #define IMDMA_S0_Y_MODIFY 0xFFC0185C    /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
785 #define IMDMA_S0_CURR_DESC_PTR 0xFFC01860       /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
786 #define IMDMA_S0_CURR_ADDR 0xFFC01864   /*IMDMA Stream 0 Source Current Address */
787 #define IMDMA_S0_CURR_X_COUNT 0xFFC01870        /*IMDMA Stream 0 Source Current Inner-Loop Count */
788 #define IMDMA_S0_CURR_Y_COUNT 0xFFC01878        /*IMDMA Stream 0 Source Current Outer-Loop Count */
789 #define IMDMA_S0_IRQ_STATUS 0xFFC01868  /*IMDMA Stream 0 Source Interrupt/Status */
790 
791 #define IMDMA_D1_CONFIG 0xFFC01888      /*IMDMA Stream 1 Destination Configuration */
792 #define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880       /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
793 #define IMDMA_D1_START_ADDR 0xFFC01884  /*IMDMA Stream 1 Destination Start Address */
794 #define IMDMA_D1_X_COUNT 0xFFC01890     /*IMDMA Stream 1 Destination Inner-Loop Count */
795 #define IMDMA_D1_Y_COUNT 0xFFC01898     /*IMDMA Stream 1 Destination Outer-Loop Count */
796 #define IMDMA_D1_X_MODIFY 0xFFC01894    /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
797 #define IMDMA_D1_Y_MODIFY 0xFFC0189C    /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
798 #define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0       /*IMDMA Stream 1 Destination Current Descriptor Ptr */
799 #define IMDMA_D1_CURR_ADDR 0xFFC018A4   /*IMDMA Stream 1 Destination Current Address */
800 #define IMDMA_D1_CURR_X_COUNT 0xFFC018B0        /*IMDMA Stream 1 Destination Current Inner-Loop Count */
801 #define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8        /*IMDMA Stream 1 Destination Current Outer-Loop Count */
802 #define IMDMA_D1_IRQ_STATUS 0xFFC018A8  /*IMDMA Stream 1 Destination Interrupt/Status */
803 
804 #define IMDMA_S1_CONFIG 0xFFC018C8      /*IMDMA Stream 1 Source Configuration */
805 #define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0       /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
806 #define IMDMA_S1_START_ADDR 0xFFC018C4  /*IMDMA Stream 1 Source Start Address */
807 #define IMDMA_S1_X_COUNT 0xFFC018D0     /*IMDMA Stream 1 Source Inner-Loop Count */
808 #define IMDMA_S1_Y_COUNT 0xFFC018D8     /*IMDMA Stream 1 Source Outer-Loop Count */
809 #define IMDMA_S1_X_MODIFY 0xFFC018D4    /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
810 #define IMDMA_S1_Y_MODIFY 0xFFC018DC    /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
811 #define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0       /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
812 #define IMDMA_S1_CURR_ADDR 0xFFC018E4   /*IMDMA Stream 1 Source Current Address */
813 #define IMDMA_S1_CURR_X_COUNT 0xFFC018F0        /*IMDMA Stream 1 Source Current Inner-Loop Count */
814 #define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8        /*IMDMA Stream 1 Source Current Outer-Loop Count */
815 #define IMDMA_S1_IRQ_STATUS 0xFFC018E8  /*IMDMA Stream 1 Source Interrupt/Status */
816 
817 /*********************************************************************************** */
818 /* System MMR Register Bits */
819 /******************************************************************************* */
820 
821 /* CHIPID Masks */
822 #define CHIPID_VERSION         0xF0000000
823 #define CHIPID_FAMILY          0x0FFFF000
824 #define CHIPID_MANUFACTURE     0x00000FFE
825 
826 /* SICA_SYSCR Masks */
827 #define COREB_SRAM_INIT         0x0020
828 
829 /* SWRST Mask */
830 #define SYSTEM_RESET           0x0007   /* Initiates a system software reset */
831 #define DOUBLE_FAULT_A         0x0008   /* Core A Double Fault Causes Reset */
832 #define DOUBLE_FAULT_B         0x0010   /* Core B Double Fault Causes Reset */
833 #define SWRST_DBL_FAULT_A      0x0800   /* SWRST Core A Double Fault */
834 #define SWRST_DBL_FAULT_B      0x1000   /* SWRST Core B Double Fault */
835 #define SWRST_WDT_B                    0x2000   /* SWRST Watchdog B */
836 #define SWRST_WDT_A                    0x4000   /* SWRST Watchdog A */
837 #define SWRST_OCCURRED         0x8000   /* SWRST Status */
838 
839 /* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
840 
841 /* SICu_IARv Masks       */
842 /* u = A or B */
843 /* v = 0 to 7 */
844 /* w = 0 or 1 */
845 
846 /* Per_number = 0 to 63 */
847 /* IVG_number = 7 to 15   */
848 #define Peripheral_IVG(Per_number, IVG_number)    \
849     ((IVG_number) - 7) << (((Per_number) % 8) * 4)      /* Peripheral #Per_number assigned IVG #IVG_number  */
850     /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
851     /*        r0.h = hi(Peripheral_IVG(62, 10)); */
852 
853 /* SICx_IMASKw Masks */
854 /* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers  */
855 #define SIC_UNMASK_ALL         0x00000000       /* Unmask all peripheral interrupts */
856 #define SIC_MASK_ALL           0xFFFFFFFF       /* Mask all peripheral interrupts */
857 #define SIC_MASK(x)            (1 << (x))       /* Mask Peripheral #x interrupt */
858 #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
859 
860 /* SIC_IWR Masks */
861 #define IWR_DISABLE_ALL        0x00000000       /* Wakeup Disable all peripherals */
862 #define IWR_ENABLE_ALL         0xFFFFFFFF       /* Wakeup Enable all peripherals */
863 /* x = pos 0 to 31, for 32-63 use value-32 */
864 #define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
865 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
866 
867 /*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
868 
869 /*  PPI_CONTROL Masks         */
870 #define PORT_EN              0x00000001 /* PPI Port Enable  */
871 #define PORT_DIR             0x00000002 /* PPI Port Direction       */
872 #define XFR_TYPE             0x0000000C /* PPI Transfer Type  */
873 #define PORT_CFG             0x00000030 /* PPI Port Configuration */
874 #define FLD_SEL              0x00000040 /* PPI Active Field Select */
875 #define PACK_EN              0x00000080 /* PPI Packing Mode */
876 #define DMA32                0x00000100 /* PPI 32-bit DMA Enable */
877 #define SKIP_EN              0x00000200 /* PPI Skip Element Enable */
878 #define SKIP_EO              0x00000400 /* PPI Skip Even/Odd Elements */
879 #define DLENGTH              0x00003800 /* PPI Data Length  */
880 #define DLEN_8               0x0        /* PPI Data Length mask for DLEN=8 */
881 #define DLEN(x) (((x-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
882 #define DLEN_10              0x00000800 /* Data Length = 10 Bits */
883 #define DLEN_11              0x00001000 /* Data Length = 11 Bits */
884 #define DLEN_12              0x00001800 /* Data Length = 12 Bits */
885 #define DLEN_13              0x00002000 /* Data Length = 13 Bits */
886 #define DLEN_14              0x00002800 /* Data Length = 14 Bits */
887 #define DLEN_15              0x00003000 /* Data Length = 15 Bits */
888 #define DLEN_16              0x00003800 /* Data Length = 16 Bits */
889 #define POL                  0x0000C000 /* PPI Signal Polarities       */
890 #define POLC            0x4000          /* PPI Clock Polarity */
891 #define POLS            0x8000          /* PPI Frame Sync Polarity */
892 
893 /* PPI_STATUS Masks */
894 #define FLD                  0x00000400 /* Field Indicator   */
895 #define FT_ERR               0x00000800 /* Frame Track Error */
896 #define OVR                  0x00001000 /* FIFO Overflow Error */
897 #define UNDR                 0x00002000 /* FIFO Underrun Error */
898 #define ERR_DET              0x00004000 /* Error Detected Indicator */
899 #define ERR_NCOR             0x00008000 /* Error Not Corrected Indicator */
900 
901 /* **********  DMA CONTROLLER MASKS  *********************8 */
902 
903 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
904 
905 #define CTYPE               0x00000040  /* DMA Channel Type Indicator */
906 #define CTYPE_P             6   /* DMA Channel Type Indicator BIT POSITION */
907 #define PCAP8               0x00000080  /* DMA 8-bit Operation Indicator   */
908 #define PCAP16              0x00000100  /* DMA 16-bit Operation Indicator */
909 #define PCAP32              0x00000200  /* DMA 32-bit Operation Indicator */
910 #define PCAPWR              0x00000400  /* DMA Write Operation Indicator */
911 #define PCAPRD              0x00000800  /* DMA Read Operation Indicator */
912 #define PMAP                0x00007000  /* DMA Peripheral Map Field */
913 
914 /*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
915 
916 /* PWM Timer bit definitions */
917 
918 /* TIMER_ENABLE Register */
919 #define TIMEN0  0x0001
920 #define TIMEN1  0x0002
921 #define TIMEN2  0x0004
922 #define TIMEN3  0x0008
923 #define TIMEN4  0x0010
924 #define TIMEN5  0x0020
925 #define TIMEN6  0x0040
926 #define TIMEN7  0x0080
927 #define TIMEN8  0x0001
928 #define TIMEN9  0x0002
929 #define TIMEN10 0x0004
930 #define TIMEN11 0x0008
931 
932 #define TIMEN0_P        0x00
933 #define TIMEN1_P        0x01
934 #define TIMEN2_P        0x02
935 #define TIMEN3_P        0x03
936 #define TIMEN4_P        0x04
937 #define TIMEN5_P        0x05
938 #define TIMEN6_P        0x06
939 #define TIMEN7_P        0x07
940 #define TIMEN8_P        0x00
941 #define TIMEN9_P        0x01
942 #define TIMEN10_P       0x02
943 #define TIMEN11_P       0x03
944 
945 /* TIMER_DISABLE Register */
946 #define TIMDIS0         0x0001
947 #define TIMDIS1         0x0002
948 #define TIMDIS2         0x0004
949 #define TIMDIS3         0x0008
950 #define TIMDIS4         0x0010
951 #define TIMDIS5         0x0020
952 #define TIMDIS6         0x0040
953 #define TIMDIS7         0x0080
954 #define TIMDIS8         0x0001
955 #define TIMDIS9         0x0002
956 #define TIMDIS10        0x0004
957 #define TIMDIS11        0x0008
958 
959 #define TIMDIS0_P       0x00
960 #define TIMDIS1_P       0x01
961 #define TIMDIS2_P       0x02
962 #define TIMDIS3_P       0x03
963 #define TIMDIS4_P       0x04
964 #define TIMDIS5_P       0x05
965 #define TIMDIS6_P       0x06
966 #define TIMDIS7_P       0x07
967 #define TIMDIS8_P       0x00
968 #define TIMDIS9_P       0x01
969 #define TIMDIS10_P      0x02
970 #define TIMDIS11_P      0x03
971 
972 /* TIMER_STATUS Register */
973 #define TIMIL0          0x00000001
974 #define TIMIL1          0x00000002
975 #define TIMIL2          0x00000004
976 #define TIMIL3          0x00000008
977 #define TIMIL4          0x00010000
978 #define TIMIL5          0x00020000
979 #define TIMIL6          0x00040000
980 #define TIMIL7          0x00080000
981 #define TIMIL8          0x0001
982 #define TIMIL9          0x0002
983 #define TIMIL10         0x0004
984 #define TIMIL11         0x0008
985 #define TOVF_ERR0       0x00000010
986 #define TOVF_ERR1       0x00000020
987 #define TOVF_ERR2       0x00000040
988 #define TOVF_ERR3       0x00000080
989 #define TOVF_ERR4       0x00100000
990 #define TOVF_ERR5       0x00200000
991 #define TOVF_ERR6       0x00400000
992 #define TOVF_ERR7       0x00800000
993 #define TOVF_ERR8       0x0010
994 #define TOVF_ERR9       0x0020
995 #define TOVF_ERR10      0x0040
996 #define TOVF_ERR11      0x0080
997 #define TRUN0           0x00001000
998 #define TRUN1           0x00002000
999 #define TRUN2           0x00004000
1000 #define TRUN3           0x00008000
1001 #define TRUN4           0x10000000
1002 #define TRUN5           0x20000000
1003 #define TRUN6           0x40000000
1004 #define TRUN7           0x80000000
1005 #define TRUN8           0x1000
1006 #define TRUN9           0x2000
1007 #define TRUN10          0x4000
1008 #define TRUN11          0x8000
1009 
1010 #define TIMIL0_P        0x00
1011 #define TIMIL1_P        0x01
1012 #define TIMIL2_P        0x02
1013 #define TIMIL3_P        0x03
1014 #define TIMIL4_P        0x10
1015 #define TIMIL5_P        0x11
1016 #define TIMIL6_P        0x12
1017 #define TIMIL7_P        0x13
1018 #define TIMIL8_P        0x00
1019 #define TIMIL9_P        0x01
1020 #define TIMIL10_P       0x02
1021 #define TIMIL11_P       0x03
1022 #define TOVF_ERR0_P     0x04
1023 #define TOVF_ERR1_P     0x05
1024 #define TOVF_ERR2_P     0x06
1025 #define TOVF_ERR3_P     0x07
1026 #define TOVF_ERR4_P     0x14
1027 #define TOVF_ERR5_P     0x15
1028 #define TOVF_ERR6_P     0x16
1029 #define TOVF_ERR7_P     0x17
1030 #define TOVF_ERR8_P     0x04
1031 #define TOVF_ERR9_P     0x05
1032 #define TOVF_ERR10_P    0x06
1033 #define TOVF_ERR11_P    0x07
1034 #define TRUN0_P         0x0C
1035 #define TRUN1_P         0x0D
1036 #define TRUN2_P         0x0E
1037 #define TRUN3_P         0x0F
1038 #define TRUN4_P         0x1C
1039 #define TRUN5_P         0x1D
1040 #define TRUN6_P         0x1E
1041 #define TRUN7_P         0x1F
1042 #define TRUN8_P         0x0C
1043 #define TRUN9_P         0x0D
1044 #define TRUN10_P        0x0E
1045 #define TRUN11_P        0x0F
1046 
1047 /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1048 #define TOVL_ERR0 TOVF_ERR0
1049 #define TOVL_ERR1 TOVF_ERR1
1050 #define TOVL_ERR2 TOVF_ERR2
1051 #define TOVL_ERR3 TOVF_ERR3
1052 #define TOVL_ERR4 TOVF_ERR4
1053 #define TOVL_ERR5 TOVF_ERR5
1054 #define TOVL_ERR6 TOVF_ERR6
1055 #define TOVL_ERR7 TOVF_ERR7
1056 #define TOVL_ERR8 TOVF_ERR8
1057 #define TOVL_ERR9 TOVF_ERR9
1058 #define TOVL_ERR10 TOVF_ERR10
1059 #define TOVL_ERR11 TOVF_ERR11
1060 #define TOVL_ERR0_P TOVF_ERR0_P
1061 #define TOVL_ERR1_P TOVF_ERR1_P
1062 #define TOVL_ERR2_P TOVF_ERR2_P
1063 #define TOVL_ERR3_P TOVF_ERR3_P
1064 #define TOVL_ERR4_P TOVF_ERR4_P
1065 #define TOVL_ERR5_P TOVF_ERR5_P
1066 #define TOVL_ERR6_P TOVF_ERR6_P
1067 #define TOVL_ERR7_P TOVF_ERR7_P
1068 #define TOVL_ERR8_P TOVF_ERR8_P
1069 #define TOVL_ERR9_P TOVF_ERR9_P
1070 #define TOVL_ERR10_P TOVF_ERR10_P
1071 #define TOVL_ERR11_P TOVF_ERR11_P
1072 
1073 /* TIMERx_CONFIG Registers */
1074 #define PWM_OUT         0x0001
1075 #define WDTH_CAP        0x0002
1076 #define EXT_CLK         0x0003
1077 #define PULSE_HI        0x0004
1078 #define PERIOD_CNT      0x0008
1079 #define IRQ_ENA         0x0010
1080 #define TIN_SEL         0x0020
1081 #define OUT_DIS         0x0040
1082 #define CLK_SEL         0x0080
1083 #define TOGGLE_HI       0x0100
1084 #define EMU_RUN         0x0200
1085 #define ERR_TYP(x)      ((x & 0x03) << 14)
1086 
1087 #define TMODE_P0                0x00
1088 #define TMODE_P1                0x01
1089 #define PULSE_HI_P              0x02
1090 #define PERIOD_CNT_P            0x03
1091 #define IRQ_ENA_P               0x04
1092 #define TIN_SEL_P               0x05
1093 #define OUT_DIS_P               0x06
1094 #define CLK_SEL_P               0x07
1095 #define TOGGLE_HI_P             0x08
1096 #define EMU_RUN_P               0x09
1097 #define ERR_TYP_P0              0x0E
1098 #define ERR_TYP_P1              0x0F
1099 
1100 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
1101 
1102 /* AMGCTL Masks */
1103 #define AMCKEN                  0x0001  /* Enable CLKOUT */
1104 #define AMBEN_B0                0x0002  /* Enable Asynchronous Memory Bank 0 only */
1105 #define AMBEN_B0_B1             0x0004  /* Enable Asynchronous Memory Banks 0 & 1 only */
1106 #define AMBEN_B0_B1_B2  0x0006  /* Enable Asynchronous Memory Banks 0, 1, and 2 */
1107 #define AMBEN_ALL               0x0008  /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
1108 #define B0_PEN                  0x0010  /* Enable 16-bit packing Bank 0  */
1109 #define B1_PEN                  0x0020  /* Enable 16-bit packing Bank 1  */
1110 #define B2_PEN                  0x0040  /* Enable 16-bit packing Bank 2  */
1111 #define B3_PEN                  0x0080  /* Enable 16-bit packing Bank 3  */
1112 
1113 /* AMGCTL Bit Positions */
1114 #define AMCKEN_P                0x00000000      /* Enable CLKOUT */
1115 #define AMBEN_P0                0x00000001      /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1116 #define AMBEN_P1                0x00000002      /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
1117 #define AMBEN_P2                0x00000003      /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
1118 #define B0_PEN_P                        0x004   /* Enable 16-bit packing Bank 0  */
1119 #define B1_PEN_P                        0x005   /* Enable 16-bit packing Bank 1  */
1120 #define B2_PEN_P                        0x006   /* Enable 16-bit packing Bank 2  */
1121 #define B3_PEN_P                        0x007   /* Enable 16-bit packing Bank 3  */
1122 
1123 /* AMBCTL0 Masks */
1124 #define B0RDYEN 0x00000001      /* Bank 0 RDY Enable, 0=disable, 1=enable */
1125 #define B0RDYPOL 0x00000002     /* Bank 0 RDY Active high, 0=active low, 1=active high */
1126 #define B0TT_1  0x00000004      /* Bank 0 Transition Time from Read to Write = 1 cycle */
1127 #define B0TT_2  0x00000008      /* Bank 0 Transition Time from Read to Write = 2 cycles */
1128 #define B0TT_3  0x0000000C      /* Bank 0 Transition Time from Read to Write = 3 cycles */
1129 #define B0TT_4  0x00000000      /* Bank 0 Transition Time from Read to Write = 4 cycles */
1130 #define B0ST_1  0x00000010      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
1131 #define B0ST_2  0x00000020      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
1132 #define B0ST_3  0x00000030      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
1133 #define B0ST_4  0x00000000      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
1134 #define B0HT_1  0x00000040      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
1135 #define B0HT_2  0x00000080      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1136 #define B0HT_3  0x000000C0      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1137 #define B0HT_0  0x00000000      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1138 #define B0RAT_1                 0x00000100      /* Bank 0 Read Access Time = 1 cycle */
1139 #define B0RAT_2                 0x00000200      /* Bank 0 Read Access Time = 2 cycles */
1140 #define B0RAT_3                 0x00000300      /* Bank 0 Read Access Time = 3 cycles */
1141 #define B0RAT_4                 0x00000400      /* Bank 0 Read Access Time = 4 cycles */
1142 #define B0RAT_5                 0x00000500      /* Bank 0 Read Access Time = 5 cycles */
1143 #define B0RAT_6                 0x00000600      /* Bank 0 Read Access Time = 6 cycles */
1144 #define B0RAT_7                 0x00000700      /* Bank 0 Read Access Time = 7 cycles */
1145 #define B0RAT_8                 0x00000800      /* Bank 0 Read Access Time = 8 cycles */
1146 #define B0RAT_9                 0x00000900      /* Bank 0 Read Access Time = 9 cycles */
1147 #define B0RAT_10                0x00000A00      /* Bank 0 Read Access Time = 10 cycles */
1148 #define B0RAT_11                0x00000B00      /* Bank 0 Read Access Time = 11 cycles */
1149 #define B0RAT_12                0x00000C00      /* Bank 0 Read Access Time = 12 cycles */
1150 #define B0RAT_13                0x00000D00      /* Bank 0 Read Access Time = 13 cycles */
1151 #define B0RAT_14                0x00000E00      /* Bank 0 Read Access Time = 14 cycles */
1152 #define B0RAT_15                0x00000F00      /* Bank 0 Read Access Time = 15 cycles */
1153 #define B0WAT_1                 0x00001000      /* Bank 0 Write Access Time = 1 cycle */
1154 #define B0WAT_2                 0x00002000      /* Bank 0 Write Access Time = 2 cycles */
1155 #define B0WAT_3                 0x00003000      /* Bank 0 Write Access Time = 3 cycles */
1156 #define B0WAT_4                 0x00004000      /* Bank 0 Write Access Time = 4 cycles */
1157 #define B0WAT_5                 0x00005000      /* Bank 0 Write Access Time = 5 cycles */
1158 #define B0WAT_6                 0x00006000      /* Bank 0 Write Access Time = 6 cycles */
1159 #define B0WAT_7                 0x00007000      /* Bank 0 Write Access Time = 7 cycles */
1160 #define B0WAT_8                 0x00008000      /* Bank 0 Write Access Time = 8 cycles */
1161 #define B0WAT_9                 0x00009000      /* Bank 0 Write Access Time = 9 cycles */
1162 #define B0WAT_10                0x0000A000      /* Bank 0 Write Access Time = 10 cycles */
1163 #define B0WAT_11                0x0000B000      /* Bank 0 Write Access Time = 11 cycles */
1164 #define B0WAT_12                0x0000C000      /* Bank 0 Write Access Time = 12 cycles */
1165 #define B0WAT_13                0x0000D000      /* Bank 0 Write Access Time = 13 cycles */
1166 #define B0WAT_14                0x0000E000      /* Bank 0 Write Access Time = 14 cycles */
1167 #define B0WAT_15                0x0000F000      /* Bank 0 Write Access Time = 15 cycles */
1168 #define B1RDYEN                 0x00010000      /* Bank 1 RDY enable, 0=disable, 1=enable */
1169 #define B1RDYPOL                0x00020000      /* Bank 1 RDY Active high, 0=active low, 1=active high */
1170 #define B1TT_1                  0x00040000      /* Bank 1 Transition Time from Read to Write = 1 cycle */
1171 #define B1TT_2                  0x00080000      /* Bank 1 Transition Time from Read to Write = 2 cycles */
1172 #define B1TT_3                  0x000C0000      /* Bank 1 Transition Time from Read to Write = 3 cycles */
1173 #define B1TT_4                  0x00000000      /* Bank 1 Transition Time from Read to Write = 4 cycles */
1174 #define B1ST_1                  0x00100000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1175 #define B1ST_2                  0x00200000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1176 #define B1ST_3                  0x00300000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1177 #define B1ST_4                  0x00000000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1178 #define B1HT_1                  0x00400000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1179 #define B1HT_2                  0x00800000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1180 #define B1HT_3                  0x00C00000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1181 #define B1HT_0                  0x00000000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1182 #define B1RAT_1                 0x01000000      /* Bank 1 Read Access Time = 1 cycle */
1183 #define B1RAT_2                 0x02000000      /* Bank 1 Read Access Time = 2 cycles */
1184 #define B1RAT_3                 0x03000000      /* Bank 1 Read Access Time = 3 cycles */
1185 #define B1RAT_4                 0x04000000      /* Bank 1 Read Access Time = 4 cycles */
1186 #define B1RAT_5                 0x05000000      /* Bank 1 Read Access Time = 5 cycles */
1187 #define B1RAT_6                 0x06000000      /* Bank 1 Read Access Time = 6 cycles */
1188 #define B1RAT_7                 0x07000000      /* Bank 1 Read Access Time = 7 cycles */
1189 #define B1RAT_8                 0x08000000      /* Bank 1 Read Access Time = 8 cycles */
1190 #define B1RAT_9                 0x09000000      /* Bank 1 Read Access Time = 9 cycles */
1191 #define B1RAT_10                0x0A000000      /* Bank 1 Read Access Time = 10 cycles */
1192 #define B1RAT_11                0x0B000000      /* Bank 1 Read Access Time = 11 cycles */
1193 #define B1RAT_12                0x0C000000      /* Bank 1 Read Access Time = 12 cycles */
1194 #define B1RAT_13                0x0D000000      /* Bank 1 Read Access Time = 13 cycles */
1195 #define B1RAT_14                0x0E000000      /* Bank 1 Read Access Time = 14 cycles */
1196 #define B1RAT_15                0x0F000000      /* Bank 1 Read Access Time = 15 cycles */
1197 #define B1WAT_1                 0x10000000      /* Bank 1 Write Access Time = 1 cycle */
1198 #define B1WAT_2                 0x20000000      /* Bank 1 Write Access Time = 2 cycles */
1199 #define B1WAT_3                 0x30000000      /* Bank 1 Write Access Time = 3 cycles */
1200 #define B1WAT_4                 0x40000000      /* Bank 1 Write Access Time = 4 cycles */
1201 #define B1WAT_5                 0x50000000      /* Bank 1 Write Access Time = 5 cycles */
1202 #define B1WAT_6                 0x60000000      /* Bank 1 Write Access Time = 6 cycles */
1203 #define B1WAT_7                 0x70000000      /* Bank 1 Write Access Time = 7 cycles */
1204 #define B1WAT_8                 0x80000000      /* Bank 1 Write Access Time = 8 cycles */
1205 #define B1WAT_9                 0x90000000      /* Bank 1 Write Access Time = 9 cycles */
1206 #define B1WAT_10                0xA0000000      /* Bank 1 Write Access Time = 10 cycles */
1207 #define B1WAT_11                0xB0000000      /* Bank 1 Write Access Time = 11 cycles */
1208 #define B1WAT_12                0xC0000000      /* Bank 1 Write Access Time = 12 cycles */
1209 #define B1WAT_13                0xD0000000      /* Bank 1 Write Access Time = 13 cycles */
1210 #define B1WAT_14                0xE0000000      /* Bank 1 Write Access Time = 14 cycles */
1211 #define B1WAT_15                0xF0000000      /* Bank 1 Write Access Time = 15 cycles */
1212 
1213 /* AMBCTL1 Masks */
1214 #define B2RDYEN                 0x00000001      /* Bank 2 RDY Enable, 0=disable, 1=enable */
1215 #define B2RDYPOL                0x00000002      /* Bank 2 RDY Active high, 0=active low, 1=active high */
1216 #define B2TT_1                  0x00000004      /* Bank 2 Transition Time from Read to Write = 1 cycle */
1217 #define B2TT_2                  0x00000008      /* Bank 2 Transition Time from Read to Write = 2 cycles */
1218 #define B2TT_3                  0x0000000C      /* Bank 2 Transition Time from Read to Write = 3 cycles */
1219 #define B2TT_4                  0x00000000      /* Bank 2 Transition Time from Read to Write = 4 cycles */
1220 #define B2ST_1                  0x00000010      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1221 #define B2ST_2                  0x00000020      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1222 #define B2ST_3                  0x00000030      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1223 #define B2ST_4                  0x00000000      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1224 #define B2HT_1                  0x00000040      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1225 #define B2HT_2                  0x00000080      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1226 #define B2HT_3                  0x000000C0      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1227 #define B2HT_0                  0x00000000      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1228 #define B2RAT_1                 0x00000100      /* Bank 2 Read Access Time = 1 cycle */
1229 #define B2RAT_2                 0x00000200      /* Bank 2 Read Access Time = 2 cycles */
1230 #define B2RAT_3                 0x00000300      /* Bank 2 Read Access Time = 3 cycles */
1231 #define B2RAT_4                 0x00000400      /* Bank 2 Read Access Time = 4 cycles */
1232 #define B2RAT_5                 0x00000500      /* Bank 2 Read Access Time = 5 cycles */
1233 #define B2RAT_6                 0x00000600      /* Bank 2 Read Access Time = 6 cycles */
1234 #define B2RAT_7                 0x00000700      /* Bank 2 Read Access Time = 7 cycles */
1235 #define B2RAT_8                 0x00000800      /* Bank 2 Read Access Time = 8 cycles */
1236 #define B2RAT_9                 0x00000900      /* Bank 2 Read Access Time = 9 cycles */
1237 #define B2RAT_10                0x00000A00      /* Bank 2 Read Access Time = 10 cycles */
1238 #define B2RAT_11                0x00000B00      /* Bank 2 Read Access Time = 11 cycles */
1239 #define B2RAT_12                0x00000C00      /* Bank 2 Read Access Time = 12 cycles */
1240 #define B2RAT_13                0x00000D00      /* Bank 2 Read Access Time = 13 cycles */
1241 #define B2RAT_14                0x00000E00      /* Bank 2 Read Access Time = 14 cycles */
1242 #define B2RAT_15                0x00000F00      /* Bank 2 Read Access Time = 15 cycles */
1243 #define B2WAT_1                 0x00001000      /* Bank 2 Write Access Time = 1 cycle */
1244 #define B2WAT_2                 0x00002000      /* Bank 2 Write Access Time = 2 cycles */
1245 #define B2WAT_3                 0x00003000      /* Bank 2 Write Access Time = 3 cycles */
1246 #define B2WAT_4                 0x00004000      /* Bank 2 Write Access Time = 4 cycles */
1247 #define B2WAT_5                 0x00005000      /* Bank 2 Write Access Time = 5 cycles */
1248 #define B2WAT_6                 0x00006000      /* Bank 2 Write Access Time = 6 cycles */
1249 #define B2WAT_7                 0x00007000      /* Bank 2 Write Access Time = 7 cycles */
1250 #define B2WAT_8                 0x00008000      /* Bank 2 Write Access Time = 8 cycles */
1251 #define B2WAT_9                 0x00009000      /* Bank 2 Write Access Time = 9 cycles */
1252 #define B2WAT_10                0x0000A000      /* Bank 2 Write Access Time = 10 cycles */
1253 #define B2WAT_11                0x0000B000      /* Bank 2 Write Access Time = 11 cycles */
1254 #define B2WAT_12                0x0000C000      /* Bank 2 Write Access Time = 12 cycles */
1255 #define B2WAT_13                0x0000D000      /* Bank 2 Write Access Time = 13 cycles */
1256 #define B2WAT_14                0x0000E000      /* Bank 2 Write Access Time = 14 cycles */
1257 #define B2WAT_15                0x0000F000      /* Bank 2 Write Access Time = 15 cycles */
1258 #define B3RDYEN                 0x00010000      /* Bank 3 RDY enable, 0=disable, 1=enable */
1259 #define B3RDYPOL                0x00020000      /* Bank 3 RDY Active high, 0=active low, 1=active high */
1260 #define B3TT_1                  0x00040000      /* Bank 3 Transition Time from Read to Write = 1 cycle */
1261 #define B3TT_2                  0x00080000      /* Bank 3 Transition Time from Read to Write = 2 cycles */
1262 #define B3TT_3                  0x000C0000      /* Bank 3 Transition Time from Read to Write = 3 cycles */
1263 #define B3TT_4                  0x00000000      /* Bank 3 Transition Time from Read to Write = 4 cycles */
1264 #define B3ST_1                  0x00100000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1265 #define B3ST_2                  0x00200000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1266 #define B3ST_3                  0x00300000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1267 #define B3ST_4                  0x00000000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1268 #define B3HT_1                  0x00400000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1269 #define B3HT_2                  0x00800000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1270 #define B3HT_3                  0x00C00000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1271 #define B3HT_0                  0x00000000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1272 #define B3RAT_1                 0x01000000      /* Bank 3 Read Access Time = 1 cycle */
1273 #define B3RAT_2                 0x02000000      /* Bank 3 Read Access Time = 2 cycles */
1274 #define B3RAT_3                 0x03000000      /* Bank 3 Read Access Time = 3 cycles */
1275 #define B3RAT_4                 0x04000000      /* Bank 3 Read Access Time = 4 cycles */
1276 #define B3RAT_5                 0x05000000      /* Bank 3 Read Access Time = 5 cycles */
1277 #define B3RAT_6                 0x06000000      /* Bank 3 Read Access Time = 6 cycles */
1278 #define B3RAT_7                 0x07000000      /* Bank 3 Read Access Time = 7 cycles */
1279 #define B3RAT_8                 0x08000000      /* Bank 3 Read Access Time = 8 cycles */
1280 #define B3RAT_9                 0x09000000      /* Bank 3 Read Access Time = 9 cycles */
1281 #define B3RAT_10                0x0A000000      /* Bank 3 Read Access Time = 10 cycles */
1282 #define B3RAT_11                0x0B000000      /* Bank 3 Read Access Time = 11 cycles */
1283 #define B3RAT_12                0x0C000000      /* Bank 3 Read Access Time = 12 cycles */
1284 #define B3RAT_13                0x0D000000      /* Bank 3 Read Access Time = 13 cycles */
1285 #define B3RAT_14                0x0E000000      /* Bank 3 Read Access Time = 14 cycles */
1286 #define B3RAT_15                0x0F000000      /* Bank 3 Read Access Time = 15 cycles */
1287 #define B3WAT_1                 0x10000000      /* Bank 3 Write Access Time = 1 cycle */
1288 #define B3WAT_2                 0x20000000      /* Bank 3 Write Access Time = 2 cycles */
1289 #define B3WAT_3                 0x30000000      /* Bank 3 Write Access Time = 3 cycles */
1290 #define B3WAT_4                 0x40000000      /* Bank 3 Write Access Time = 4 cycles */
1291 #define B3WAT_5                 0x50000000      /* Bank 3 Write Access Time = 5 cycles */
1292 #define B3WAT_6                 0x60000000      /* Bank 3 Write Access Time = 6 cycles */
1293 #define B3WAT_7                 0x70000000      /* Bank 3 Write Access Time = 7 cycles */
1294 #define B3WAT_8                 0x80000000      /* Bank 3 Write Access Time = 8 cycles */
1295 #define B3WAT_9                 0x90000000      /* Bank 3 Write Access Time = 9 cycles */
1296 #define B3WAT_10                0xA0000000      /* Bank 3 Write Access Time = 10 cycles */
1297 #define B3WAT_11                0xB0000000      /* Bank 3 Write Access Time = 11 cycles */
1298 #define B3WAT_12                0xC0000000      /* Bank 3 Write Access Time = 12 cycles */
1299 #define B3WAT_13                0xD0000000      /* Bank 3 Write Access Time = 13 cycles */
1300 #define B3WAT_14                0xE0000000      /* Bank 3 Write Access Time = 14 cycles */
1301 #define B3WAT_15                0xF0000000      /* Bank 3 Write Access Time = 15 cycles */
1302 
1303 /* **********************  SDRAM CONTROLLER MASKS  *************************** */
1304 
1305 /* EBIU_SDGCTL Masks */
1306 #define SCTLE                   0x00000001      /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1307 #define CL_2                    0x00000008      /* SDRAM CAS latency = 2 cycles */
1308 #define CL_3                    0x0000000C      /* SDRAM CAS latency = 3 cycles */
1309 #define PFE                     0x00000010      /* Enable SDRAM prefetch */
1310 #define PFP                     0x00000020      /* Prefetch has priority over AMC requests */
1311 #define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle */
1312 #define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles */
1313 #define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles */
1314 #define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles */
1315 #define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles */
1316 #define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles */
1317 #define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles */
1318 #define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles */
1319 #define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles */
1320 #define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles */
1321 #define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles */
1322 #define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles */
1323 #define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles */
1324 #define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles */
1325 #define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles */
1326 #define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle */
1327 #define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles */
1328 #define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles */
1329 #define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles */
1330 #define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles */
1331 #define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles */
1332 #define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles */
1333 #define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle */
1334 #define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles */
1335 #define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles */
1336 #define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles */
1337 #define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles */
1338 #define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles */
1339 #define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles */
1340 #define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle */
1341 #define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles */
1342 #define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles */
1343 #define PUPSD                   0x00200000      /*Power-up start delay */
1344 #define PSM                     0x00400000      /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1345 #define PSS                             0x00800000      /* enable SDRAM power-up sequence on next SDRAM access */
1346 #define SRFS                    0x01000000      /* Start SDRAM self-refresh mode */
1347 #define EBUFE                   0x02000000      /* Enable external buffering timing */
1348 #define FBBRW                   0x04000000      /* Fast back-to-back read write enable */
1349 #define EMREN                   0x10000000      /* Extended mode register enable */
1350 #define TCSR                    0x20000000      /* Temp compensated self refresh value 85 deg C */
1351 #define CDDBG                   0x40000000      /* Tristate SDRAM controls during bus grant */
1352 
1353 /* EBIU_SDBCTL Masks */
1354 #define EB0_E                           0x00000001      /* Enable SDRAM external bank 0 */
1355 #define EB0_SZ_16                       0x00000000      /* SDRAM external bank size = 16MB */
1356 #define EB0_SZ_32                       0x00000002      /* SDRAM external bank size = 32MB */
1357 #define EB0_SZ_64                       0x00000004      /* SDRAM external bank size = 64MB */
1358 #define EB0_SZ_128                      0x00000006      /* SDRAM external bank size = 128MB */
1359 #define EB0_CAW_8                       0x00000000      /* SDRAM external bank column address width = 8 bits */
1360 #define EB0_CAW_9                       0x00000010      /* SDRAM external bank column address width = 9 bits */
1361 #define EB0_CAW_10                      0x00000020      /* SDRAM external bank column address width = 9 bits */
1362 #define EB0_CAW_11                      0x00000030      /* SDRAM external bank column address width = 9 bits */
1363 
1364 #define EB1_E                           0x00000100      /* Enable SDRAM external bank 1 */
1365 #define EB1__SZ_16                      0x00000000      /* SDRAM external bank size = 16MB */
1366 #define EB1__SZ_32                      0x00000200      /* SDRAM external bank size = 32MB */
1367 #define EB1__SZ_64                      0x00000400      /* SDRAM external bank size = 64MB */
1368 #define EB1__SZ_128                     0x00000600      /* SDRAM external bank size = 128MB */
1369 #define EB1__CAW_8                      0x00000000      /* SDRAM external bank column address width = 8 bits */
1370 #define EB1__CAW_9                      0x00001000      /* SDRAM external bank column address width = 9 bits */
1371 #define EB1__CAW_10                     0x00002000      /* SDRAM external bank column address width = 9 bits */
1372 #define EB1__CAW_11                     0x00003000      /* SDRAM external bank column address width = 9 bits */
1373 
1374 #define EB2__E                          0x00010000      /* Enable SDRAM external bank 2 */
1375 #define EB2__SZ_16                      0x00000000      /* SDRAM external bank size = 16MB */
1376 #define EB2__SZ_32                      0x00020000      /* SDRAM external bank size = 32MB */
1377 #define EB2__SZ_64                      0x00040000      /* SDRAM external bank size = 64MB */
1378 #define EB2__SZ_128                     0x00060000      /* SDRAM external bank size = 128MB */
1379 #define EB2__CAW_8                      0x00000000      /* SDRAM external bank column address width = 8 bits */
1380 #define EB2__CAW_9                      0x00100000      /* SDRAM external bank column address width = 9 bits */
1381 #define EB2__CAW_10                     0x00200000      /* SDRAM external bank column address width = 9 bits */
1382 #define EB2__CAW_11                     0x00300000      /* SDRAM external bank column address width = 9 bits */
1383 
1384 #define EB3__E                          0x01000000      /* Enable SDRAM external bank 3 */
1385 #define EB3__SZ_16                      0x00000000      /* SDRAM external bank size = 16MB */
1386 #define EB3__SZ_32                      0x02000000      /* SDRAM external bank size = 32MB */
1387 #define EB3__SZ_64                      0x04000000      /* SDRAM external bank size = 64MB */
1388 #define EB3__SZ_128                     0x06000000      /* SDRAM external bank size = 128MB */
1389 #define EB3__CAW_8                      0x00000000      /* SDRAM external bank column address width = 8 bits */
1390 #define EB3__CAW_9                      0x10000000      /* SDRAM external bank column address width = 9 bits */
1391 #define EB3__CAW_10                     0x20000000      /* SDRAM external bank column address width = 9 bits */
1392 #define EB3__CAW_11                     0x30000000      /* SDRAM external bank column address width = 9 bits */
1393 
1394 /* EBIU_SDSTAT Masks */
1395 #define SDCI                    0x00000001      /* SDRAM controller is idle  */
1396 #define SDSRA                   0x00000002      /* SDRAM SDRAM self refresh is active */
1397 #define SDPUA                   0x00000004      /* SDRAM power up active  */
1398 #define SDRS                    0x00000008      /* SDRAM is in reset state */
1399 #define SDEASE              0x00000010  /* SDRAM EAB sticky error status - W1C */
1400 #define BGSTAT                  0x00000020      /* Bus granted */
1401 
1402 #endif                          /* _DEF_BF561_H */
1403 

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