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TOMOYO Linux Cross Reference
Linux/arch/blackfin/mach-bf609/boards/ezkit.c

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  1 /*
  2  * Copyright 2004-2009 Analog Devices Inc.
  3  *                2005 National ICT Australia (NICTA)
  4  *                      Aidan Williams <aidan@nicta.com.au>
  5  *
  6  * Licensed under the GPL-2 or later.
  7  */
  8 
  9 #include <linux/device.h>
 10 #include <linux/platform_device.h>
 11 #include <linux/mtd/mtd.h>
 12 #include <linux/mtd/partitions.h>
 13 #include <linux/mtd/physmap.h>
 14 #include <linux/spi/spi.h>
 15 #include <linux/spi/flash.h>
 16 #include <linux/irq.h>
 17 #include <linux/i2c.h>
 18 #include <linux/interrupt.h>
 19 #include <linux/usb/musb.h>
 20 #include <linux/pinctrl/machine.h>
 21 #include <linux/pinctrl/pinconf-generic.h>
 22 #include <linux/platform_data/pinctrl-adi2.h>
 23 #include <linux/spi/adi_spi3.h>
 24 #include <linux/gpio.h>
 25 #include <asm/dma.h>
 26 #include <asm/nand.h>
 27 #include <asm/dpmc.h>
 28 #include <asm/portmux.h>
 29 #include <asm/bfin_sdh.h>
 30 #include <linux/input.h>
 31 #include <linux/spi/ad7877.h>
 32 
 33 /*
 34  * Name the Board for the /proc/cpuinfo
 35  */
 36 const char bfin_board_name[] = "ADI BF609-EZKIT";
 37 
 38 /*
 39  *  Driver needs to know address, irq and flag pin.
 40  */
 41 
 42 #if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
 43 #include <linux/usb/isp1760.h>
 44 static struct resource bfin_isp1760_resources[] = {
 45         [0] = {
 46                 .start  = 0x2C0C0000,
 47                 .end    = 0x2C0C0000 + 0xfffff,
 48                 .flags  = IORESOURCE_MEM,
 49         },
 50         [1] = {
 51                 .start  = IRQ_PG7,
 52                 .end    = IRQ_PG7,
 53                 .flags  = IORESOURCE_IRQ,
 54         },
 55 };
 56 
 57 static struct isp1760_platform_data isp1760_priv = {
 58         .is_isp1761 = 0,
 59         .bus_width_16 = 1,
 60         .port1_otg = 0,
 61         .analog_oc = 0,
 62         .dack_polarity_high = 0,
 63         .dreq_polarity_high = 0,
 64 };
 65 
 66 static struct platform_device bfin_isp1760_device = {
 67         .name           = "isp1760",
 68         .id             = 0,
 69         .dev = {
 70                 .platform_data = &isp1760_priv,
 71         },
 72         .num_resources  = ARRAY_SIZE(bfin_isp1760_resources),
 73         .resource       = bfin_isp1760_resources,
 74 };
 75 #endif
 76 
 77 #if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
 78 #include <linux/platform_data/bfin_rotary.h>
 79 
 80 static struct bfin_rotary_platform_data bfin_rotary_data = {
 81         /*.rotary_up_key     = KEY_UP,*/
 82         /*.rotary_down_key   = KEY_DOWN,*/
 83         .rotary_rel_code   = REL_WHEEL,
 84         .rotary_button_key = KEY_ENTER,
 85         .debounce          = 10,        /* 0..17 */
 86         .mode              = ROT_QUAD_ENC | ROT_DEBE,
 87 };
 88 
 89 static struct resource bfin_rotary_resources[] = {
 90         {
 91                 .start = CNT_CONFIG,
 92                 .end   = CNT_CONFIG + 0xff,
 93                 .flags = IORESOURCE_MEM,
 94         },
 95         {
 96                 .start = IRQ_CNT,
 97                 .end = IRQ_CNT,
 98                 .flags = IORESOURCE_IRQ,
 99         },
100 };
101 
102 static struct platform_device bfin_rotary_device = {
103         .name           = "bfin-rotary",
104         .id             = -1,
105         .num_resources  = ARRAY_SIZE(bfin_rotary_resources),
106         .resource       = bfin_rotary_resources,
107         .dev            = {
108                 .platform_data = &bfin_rotary_data,
109         },
110 };
111 #endif
112 
113 #if IS_ENABLED(CONFIG_STMMAC_ETH)
114 #include <linux/stmmac.h>
115 #include <linux/phy.h>
116 
117 static struct stmmac_mdio_bus_data phy_private_data = {
118         .phy_mask = 1,
119 };
120 
121 static struct stmmac_dma_cfg eth_dma_cfg = {
122         .pbl    = 2,
123 };
124 
125 int stmmac_ptp_clk_init(struct platform_device *pdev, void *priv)
126 {
127         bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
128         return 0;
129 }
130 
131 static struct plat_stmmacenet_data eth_private_data = {
132         .has_gmac = 1,
133         .bus_id   = 0,
134         .enh_desc = 1,
135         .phy_addr = 1,
136         .mdio_bus_data = &phy_private_data,
137         .dma_cfg  = &eth_dma_cfg,
138         .force_thresh_dma_mode = 1,
139         .interface = PHY_INTERFACE_MODE_RMII,
140         .init = stmmac_ptp_clk_init,
141 };
142 
143 static struct platform_device bfin_eth_device = {
144         .name           = "stmmaceth",
145         .id             = 0,
146         .num_resources  = 2,
147         .resource       = (struct resource[]) {
148                 {
149                         .start  = EMAC0_MACCFG,
150                         .end    = EMAC0_MACCFG + 0x1274,
151                         .flags  = IORESOURCE_MEM,
152                 },
153                 {
154                         .name   = "macirq",
155                         .start  = IRQ_EMAC0_STAT,
156                         .end    = IRQ_EMAC0_STAT,
157                         .flags  = IORESOURCE_IRQ,
158                 },
159         },
160         .dev = {
161                 .power.can_wakeup = 1,
162                 .platform_data = &eth_private_data,
163         }
164 };
165 #endif
166 
167 #if IS_ENABLED(CONFIG_INPUT_ADXL34X)
168 #include <linux/input/adxl34x.h>
169 static const struct adxl34x_platform_data adxl34x_info = {
170         .x_axis_offset = 0,
171         .y_axis_offset = 0,
172         .z_axis_offset = 0,
173         .tap_threshold = 0x31,
174         .tap_duration = 0x10,
175         .tap_latency = 0x60,
176         .tap_window = 0xF0,
177         .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
178         .act_axis_control = 0xFF,
179         .activity_threshold = 5,
180         .inactivity_threshold = 3,
181         .inactivity_time = 4,
182         .free_fall_threshold = 0x7,
183         .free_fall_time = 0x20,
184         .data_rate = 0x8,
185         .data_range = ADXL_FULL_RES,
186 
187         .ev_type = EV_ABS,
188         .ev_code_x = ABS_X,             /* EV_REL */
189         .ev_code_y = ABS_Y,             /* EV_REL */
190         .ev_code_z = ABS_Z,             /* EV_REL */
191 
192         .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
193 
194 /*      .ev_code_ff = KEY_F,*/          /* EV_KEY */
195 /*      .ev_code_act_inactivity = KEY_A,*/      /* EV_KEY */
196         .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
197         .fifo_mode = ADXL_FIFO_STREAM,
198         .orientation_enable = ADXL_EN_ORIENTATION_3D,
199         .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
200         .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
201         /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
202         .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
203 };
204 #endif
205 
206 #if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
207 static struct platform_device rtc_device = {
208         .name = "rtc-bfin",
209         .id   = -1,
210 };
211 #endif
212 
213 #if IS_ENABLED(CONFIG_SERIAL_BFIN)
214 #ifdef CONFIG_SERIAL_BFIN_UART0
215 static struct resource bfin_uart0_resources[] = {
216         {
217                 .start = UART0_REVID,
218                 .end = UART0_RXDIV+4,
219                 .flags = IORESOURCE_MEM,
220         },
221 #ifdef CONFIG_EARLY_PRINTK
222         {
223                 .start = PORTD_FER,
224                 .end = PORTD_FER+2,
225                 .flags = IORESOURCE_REG,
226         },
227         {
228                 .start = PORTD_MUX,
229                 .end = PORTD_MUX+3,
230                 .flags = IORESOURCE_REG,
231         },
232 #endif
233         {
234                 .start = IRQ_UART0_TX,
235                 .end = IRQ_UART0_TX,
236                 .flags = IORESOURCE_IRQ,
237         },
238         {
239                 .start = IRQ_UART0_RX,
240                 .end = IRQ_UART0_RX,
241                 .flags = IORESOURCE_IRQ,
242         },
243         {
244                 .start = IRQ_UART0_STAT,
245                 .end = IRQ_UART0_STAT,
246                 .flags = IORESOURCE_IRQ,
247         },
248         {
249                 .start = CH_UART0_TX,
250                 .end = CH_UART0_TX,
251                 .flags = IORESOURCE_DMA,
252         },
253         {
254                 .start = CH_UART0_RX,
255                 .end = CH_UART0_RX,
256                 .flags = IORESOURCE_DMA,
257         },
258 #ifdef CONFIG_BFIN_UART0_CTSRTS
259         {       /* CTS pin -- 0 means not supported */
260                 .start = GPIO_PD10,
261                 .end = GPIO_PD10,
262                 .flags = IORESOURCE_IO,
263         },
264         {       /* RTS pin -- 0 means not supported */
265                 .start = GPIO_PD9,
266                 .end = GPIO_PD9,
267                 .flags = IORESOURCE_IO,
268         },
269 #endif
270 };
271 
272 static unsigned short bfin_uart0_peripherals[] = {
273         P_UART0_TX, P_UART0_RX,
274 #ifdef CONFIG_BFIN_UART0_CTSRTS
275         P_UART0_RTS, P_UART0_CTS,
276 #endif
277         0
278 };
279 
280 static struct platform_device bfin_uart0_device = {
281         .name = "bfin-uart",
282         .id = 0,
283         .num_resources = ARRAY_SIZE(bfin_uart0_resources),
284         .resource = bfin_uart0_resources,
285         .dev = {
286                 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
287         },
288 };
289 #endif
290 #ifdef CONFIG_SERIAL_BFIN_UART1
291 static struct resource bfin_uart1_resources[] = {
292         {
293                 .start = UART1_REVID,
294                 .end = UART1_RXDIV+4,
295                 .flags = IORESOURCE_MEM,
296         },
297 #ifdef CONFIG_EARLY_PRINTK
298         {
299                 .start = PORTG_FER_SET,
300                 .end = PORTG_FER_SET+2,
301                 .flags = IORESOURCE_REG,
302         },
303 #endif
304         {
305                 .start = IRQ_UART1_TX,
306                 .end = IRQ_UART1_TX,
307                 .flags = IORESOURCE_IRQ,
308         },
309         {
310                 .start = IRQ_UART1_RX,
311                 .end = IRQ_UART1_RX,
312                 .flags = IORESOURCE_IRQ,
313         },
314         {
315                 .start = IRQ_UART1_STAT,
316                 .end = IRQ_UART1_STAT,
317                 .flags = IORESOURCE_IRQ,
318         },
319         {
320                 .start = CH_UART1_TX,
321                 .end = CH_UART1_TX,
322                 .flags = IORESOURCE_DMA,
323         },
324         {
325                 .start = CH_UART1_RX,
326                 .end = CH_UART1_RX,
327                 .flags = IORESOURCE_DMA,
328         },
329 #ifdef CONFIG_BFIN_UART1_CTSRTS
330         {       /* CTS pin -- 0 means not supported */
331                 .start = GPIO_PG13,
332                 .end = GPIO_PG13,
333                 .flags = IORESOURCE_IO,
334         },
335         {       /* RTS pin -- 0 means not supported */
336                 .start = GPIO_PG10,
337                 .end = GPIO_PG10,
338                 .flags = IORESOURCE_IO,
339         },
340 #endif
341 };
342 
343 static unsigned short bfin_uart1_peripherals[] = {
344         P_UART1_TX, P_UART1_RX,
345 #ifdef CONFIG_BFIN_UART1_CTSRTS
346         P_UART1_RTS, P_UART1_CTS,
347 #endif
348         0
349 };
350 
351 static struct platform_device bfin_uart1_device = {
352         .name = "bfin-uart",
353         .id = 1,
354         .num_resources = ARRAY_SIZE(bfin_uart1_resources),
355         .resource = bfin_uart1_resources,
356         .dev = {
357                 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
358         },
359 };
360 #endif
361 #endif
362 
363 #if IS_ENABLED(CONFIG_BFIN_SIR)
364 #ifdef CONFIG_BFIN_SIR0
365 static struct resource bfin_sir0_resources[] = {
366         {
367                 .start = 0xFFC00400,
368                 .end = 0xFFC004FF,
369                 .flags = IORESOURCE_MEM,
370         },
371         {
372                 .start = IRQ_UART0_TX,
373                 .end = IRQ_UART0_TX+1,
374                 .flags = IORESOURCE_IRQ,
375         },
376         {
377                 .start = CH_UART0_TX,
378                 .end = CH_UART0_TX+1,
379                 .flags = IORESOURCE_DMA,
380         },
381 };
382 static struct platform_device bfin_sir0_device = {
383         .name = "bfin_sir",
384         .id = 0,
385         .num_resources = ARRAY_SIZE(bfin_sir0_resources),
386         .resource = bfin_sir0_resources,
387 };
388 #endif
389 #ifdef CONFIG_BFIN_SIR1
390 static struct resource bfin_sir1_resources[] = {
391         {
392                 .start = 0xFFC02000,
393                 .end = 0xFFC020FF,
394                 .flags = IORESOURCE_MEM,
395         },
396         {
397                 .start = IRQ_UART1_TX,
398                 .end = IRQ_UART1_TX+1,
399                 .flags = IORESOURCE_IRQ,
400         },
401         {
402                 .start = CH_UART1_TX,
403                 .end = CH_UART1_TX+1,
404                 .flags = IORESOURCE_DMA,
405         },
406 };
407 static struct platform_device bfin_sir1_device = {
408         .name = "bfin_sir",
409         .id = 1,
410         .num_resources = ARRAY_SIZE(bfin_sir1_resources),
411         .resource = bfin_sir1_resources,
412 };
413 #endif
414 #endif
415 
416 #if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
417 static struct resource musb_resources[] = {
418         [0] = {
419                 .start  = 0xFFCC1000,
420                 .end    = 0xFFCC1398,
421                 .flags  = IORESOURCE_MEM,
422         },
423         [1] = { /* general IRQ */
424                 .start  = IRQ_USB_STAT,
425                 .end    = IRQ_USB_STAT,
426                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
427                 .name   = "mc"
428         },
429         [2] = { /* DMA IRQ */
430                 .start  = IRQ_USB_DMA,
431                 .end    = IRQ_USB_DMA,
432                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
433                 .name   = "dma"
434         },
435 };
436 
437 static struct musb_hdrc_config musb_config = {
438         .multipoint     = 1,
439         .dyn_fifo       = 0,
440         .dma            = 1,
441         .num_eps        = 16,
442         .dma_channels   = 8,
443         .clkin          = 48,           /* musb CLKIN in MHZ */
444 };
445 
446 static struct musb_hdrc_platform_data musb_plat = {
447 #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
448         .mode           = MUSB_OTG,
449 #elif defined(CONFIG_USB_MUSB_HDRC)
450         .mode           = MUSB_HOST,
451 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
452         .mode           = MUSB_PERIPHERAL,
453 #endif
454         .config         = &musb_config,
455 };
456 
457 static u64 musb_dmamask = ~(u32)0;
458 
459 static struct platform_device musb_device = {
460         .name           = "musb-blackfin",
461         .id             = 0,
462         .dev = {
463                 .dma_mask               = &musb_dmamask,
464                 .coherent_dma_mask      = 0xffffffff,
465                 .platform_data          = &musb_plat,
466         },
467         .num_resources  = ARRAY_SIZE(musb_resources),
468         .resource       = musb_resources,
469 };
470 #endif
471 
472 #if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
473 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
474 static struct resource bfin_sport0_uart_resources[] = {
475         {
476                 .start = SPORT0_TCR1,
477                 .end = SPORT0_MRCS3+4,
478                 .flags = IORESOURCE_MEM,
479         },
480         {
481                 .start = IRQ_SPORT0_RX,
482                 .end = IRQ_SPORT0_RX+1,
483                 .flags = IORESOURCE_IRQ,
484         },
485         {
486                 .start = IRQ_SPORT0_ERROR,
487                 .end = IRQ_SPORT0_ERROR,
488                 .flags = IORESOURCE_IRQ,
489         },
490 };
491 
492 static unsigned short bfin_sport0_peripherals[] = {
493         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
494         P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
495 };
496 
497 static struct platform_device bfin_sport0_uart_device = {
498         .name = "bfin-sport-uart",
499         .id = 0,
500         .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
501         .resource = bfin_sport0_uart_resources,
502         .dev = {
503                 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
504         },
505 };
506 #endif
507 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
508 static struct resource bfin_sport1_uart_resources[] = {
509         {
510                 .start = SPORT1_TCR1,
511                 .end = SPORT1_MRCS3+4,
512                 .flags = IORESOURCE_MEM,
513         },
514         {
515                 .start = IRQ_SPORT1_RX,
516                 .end = IRQ_SPORT1_RX+1,
517                 .flags = IORESOURCE_IRQ,
518         },
519         {
520                 .start = IRQ_SPORT1_ERROR,
521                 .end = IRQ_SPORT1_ERROR,
522                 .flags = IORESOURCE_IRQ,
523         },
524 };
525 
526 static unsigned short bfin_sport1_peripherals[] = {
527         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
528         P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
529 };
530 
531 static struct platform_device bfin_sport1_uart_device = {
532         .name = "bfin-sport-uart",
533         .id = 1,
534         .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
535         .resource = bfin_sport1_uart_resources,
536         .dev = {
537                 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
538         },
539 };
540 #endif
541 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
542 static struct resource bfin_sport2_uart_resources[] = {
543         {
544                 .start = SPORT2_TCR1,
545                 .end = SPORT2_MRCS3+4,
546                 .flags = IORESOURCE_MEM,
547         },
548         {
549                 .start = IRQ_SPORT2_RX,
550                 .end = IRQ_SPORT2_RX+1,
551                 .flags = IORESOURCE_IRQ,
552         },
553         {
554                 .start = IRQ_SPORT2_ERROR,
555                 .end = IRQ_SPORT2_ERROR,
556                 .flags = IORESOURCE_IRQ,
557         },
558 };
559 
560 static unsigned short bfin_sport2_peripherals[] = {
561         P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
562         P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
563 };
564 
565 static struct platform_device bfin_sport2_uart_device = {
566         .name = "bfin-sport-uart",
567         .id = 2,
568         .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
569         .resource = bfin_sport2_uart_resources,
570         .dev = {
571                 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
572         },
573 };
574 #endif
575 #endif
576 
577 #if IS_ENABLED(CONFIG_CAN_BFIN)
578 
579 static unsigned short bfin_can0_peripherals[] = {
580         P_CAN0_RX, P_CAN0_TX, 0
581 };
582 
583 static struct resource bfin_can0_resources[] = {
584         {
585                 .start = 0xFFC00A00,
586                 .end = 0xFFC00FFF,
587                 .flags = IORESOURCE_MEM,
588         },
589         {
590                 .start = IRQ_CAN0_RX,
591                 .end = IRQ_CAN0_RX,
592                 .flags = IORESOURCE_IRQ,
593         },
594         {
595                 .start = IRQ_CAN0_TX,
596                 .end = IRQ_CAN0_TX,
597                 .flags = IORESOURCE_IRQ,
598         },
599         {
600                 .start = IRQ_CAN0_STAT,
601                 .end = IRQ_CAN0_STAT,
602                 .flags = IORESOURCE_IRQ,
603         },
604 };
605 
606 static struct platform_device bfin_can0_device = {
607         .name = "bfin_can",
608         .id = 0,
609         .num_resources = ARRAY_SIZE(bfin_can0_resources),
610         .resource = bfin_can0_resources,
611         .dev = {
612                 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
613         },
614 };
615 
616 #endif
617 
618 #if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
619 static struct mtd_partition partition_info[] = {
620         {
621                 .name = "bootloader(nand)",
622                 .offset = 0,
623                 .size = 0x80000,
624         }, {
625                 .name = "linux kernel(nand)",
626                 .offset = MTDPART_OFS_APPEND,
627                 .size = 4 * 1024 * 1024,
628         },
629         {
630                 .name = "file system(nand)",
631                 .offset = MTDPART_OFS_APPEND,
632                 .size = MTDPART_SIZ_FULL,
633         },
634 };
635 
636 static struct bf5xx_nand_platform bfin_nand_platform = {
637         .data_width = NFC_NWIDTH_8,
638         .partitions = partition_info,
639         .nr_partitions = ARRAY_SIZE(partition_info),
640         .rd_dly = 3,
641         .wr_dly = 3,
642 };
643 
644 static struct resource bfin_nand_resources[] = {
645         {
646                 .start = 0xFFC03B00,
647                 .end = 0xFFC03B4F,
648                 .flags = IORESOURCE_MEM,
649         },
650         {
651                 .start = CH_NFC,
652                 .end = CH_NFC,
653                 .flags = IORESOURCE_IRQ,
654         },
655 };
656 
657 static struct platform_device bfin_nand_device = {
658         .name = "bfin-nand",
659         .id = 0,
660         .num_resources = ARRAY_SIZE(bfin_nand_resources),
661         .resource = bfin_nand_resources,
662         .dev = {
663                 .platform_data = &bfin_nand_platform,
664         },
665 };
666 #endif
667 
668 #if IS_ENABLED(CONFIG_SDH_BFIN)
669 
670 static struct bfin_sd_host bfin_sdh_data = {
671         .dma_chan = CH_RSI,
672         .irq_int0 = IRQ_RSI_INT0,
673         .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
674 };
675 
676 static struct platform_device bfin_sdh_device = {
677         .name = "bfin-sdh",
678         .id = 0,
679         .dev = {
680                 .platform_data = &bfin_sdh_data,
681         },
682 };
683 #endif
684 
685 #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
686 static struct mtd_partition ezkit_partitions[] = {
687         {
688                 .name       = "bootloader(nor)",
689                 .size       = 0x80000,
690                 .offset     = 0,
691         }, {
692                 .name       = "linux kernel(nor)",
693                 .size       = 0x400000,
694                 .offset     = MTDPART_OFS_APPEND,
695         }, {
696                 .name       = "file system(nor)",
697                 .size       = 0x1000000 - 0x80000 - 0x400000,
698                 .offset     = MTDPART_OFS_APPEND,
699         },
700 };
701 
702 int bf609_nor_flash_init(struct platform_device *pdev)
703 {
704 #define CONFIG_SMC_GCTL_VAL     0x00000010
705 
706         bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
707         bfin_write32(SMC_B0CTL, 0x01002011);
708         bfin_write32(SMC_B0TIM, 0x08170977);
709         bfin_write32(SMC_B0ETIM, 0x00092231);
710         return 0;
711 }
712 
713 void bf609_nor_flash_exit(struct platform_device *pdev)
714 {
715         bfin_write32(SMC_GCTL, 0);
716 }
717 
718 static struct physmap_flash_data ezkit_flash_data = {
719         .width      = 2,
720         .parts      = ezkit_partitions,
721         .init       = bf609_nor_flash_init,
722         .exit       = bf609_nor_flash_exit,
723         .nr_parts   = ARRAY_SIZE(ezkit_partitions),
724 #ifdef CONFIG_ROMKERNEL
725         .probe_type = "map_rom",
726 #endif
727 };
728 
729 static struct resource ezkit_flash_resource = {
730         .start = 0xb0000000,
731         .end   = 0xb0ffffff,
732         .flags = IORESOURCE_MEM,
733 };
734 
735 static struct platform_device ezkit_flash_device = {
736         .name          = "physmap-flash",
737         .id            = 0,
738         .dev = {
739                 .platform_data = &ezkit_flash_data,
740         },
741         .num_resources = 1,
742         .resource      = &ezkit_flash_resource,
743 };
744 #endif
745 
746 #if IS_ENABLED(CONFIG_MTD_M25P80)
747 /* SPI flash chip (w25q32) */
748 static struct mtd_partition bfin_spi_flash_partitions[] = {
749         {
750                 .name = "bootloader(spi)",
751                 .size = 0x00080000,
752                 .offset = 0,
753                 .mask_flags = MTD_CAP_ROM
754         }, {
755                 .name = "linux kernel(spi)",
756                 .size = 0x00180000,
757                 .offset = MTDPART_OFS_APPEND,
758         }, {
759                 .name = "file system(spi)",
760                 .size = MTDPART_SIZ_FULL,
761                 .offset = MTDPART_OFS_APPEND,
762         }
763 };
764 
765 static struct flash_platform_data bfin_spi_flash_data = {
766         .name = "m25p80",
767         .parts = bfin_spi_flash_partitions,
768         .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
769         .type = "w25q32",
770 };
771 
772 static struct adi_spi3_chip spi_flash_chip_info = {
773         .enable_dma = true,         /* use dma transfer with this chip*/
774 };
775 #endif
776 
777 #if IS_ENABLED(CONFIG_SPI_SPIDEV)
778 static struct adi_spi3_chip spidev_chip_info = {
779         .enable_dma = true,
780 };
781 #endif
782 
783 #if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
784 static struct platform_device bfin_pcm = {
785         .name = "bfin-i2s-pcm-audio",
786         .id = -1,
787 };
788 #endif
789 
790 #if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
791 #include <asm/bfin_sport3.h>
792 static struct resource bfin_snd_resources[] = {
793         {
794                 .start = SPORT0_CTL_A,
795                 .end = SPORT0_CTL_A,
796                 .flags = IORESOURCE_MEM,
797         },
798         {
799                 .start = SPORT0_CTL_B,
800                 .end = SPORT0_CTL_B,
801                 .flags = IORESOURCE_MEM,
802         },
803         {
804                 .start = CH_SPORT0_TX,
805                 .end = CH_SPORT0_TX,
806                 .flags = IORESOURCE_DMA,
807         },
808         {
809                 .start = CH_SPORT0_RX,
810                 .end = CH_SPORT0_RX,
811                 .flags = IORESOURCE_DMA,
812         },
813         {
814                 .start = IRQ_SPORT0_TX_STAT,
815                 .end = IRQ_SPORT0_TX_STAT,
816                 .flags = IORESOURCE_IRQ,
817         },
818         {
819                 .start = IRQ_SPORT0_RX_STAT,
820                 .end = IRQ_SPORT0_RX_STAT,
821                 .flags = IORESOURCE_IRQ,
822         },
823 };
824 
825 static const unsigned short bfin_snd_pin[] = {
826         P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
827         P_SPORT0_BFS, P_SPORT0_BD0, 0,
828 };
829 
830 static struct bfin_snd_platform_data bfin_snd_data = {
831         .pin_req = bfin_snd_pin,
832 };
833 
834 static struct platform_device bfin_i2s = {
835         .name = "bfin-i2s",
836         .num_resources = ARRAY_SIZE(bfin_snd_resources),
837         .resource = bfin_snd_resources,
838         .dev = {
839                 .platform_data = &bfin_snd_data,
840         },
841 };
842 #endif
843 
844 #if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
845 static const char * const ad1836_link[] = {
846         "bfin-i2s.0",
847         "spi0.76",
848 };
849 static struct platform_device bfin_ad1836_machine = {
850         .name = "bfin-snd-ad1836",
851         .id = -1,
852         .dev = {
853                 .platform_data = (void *)ad1836_link,
854         },
855 };
856 #endif
857 
858 #if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
859 static struct platform_device adau1761_device = {
860         .name = "bfin-eval-adau1x61",
861 };
862 #endif
863 
864 #if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
865 #include <sound/adau17x1.h>
866 static struct adau1761_platform_data adau1761_info = {
867         .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
868         .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
869 };
870 #endif
871 
872 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
873 #include <linux/videodev2.h>
874 #include <media/blackfin/bfin_capture.h>
875 #include <media/blackfin/ppi.h>
876 
877 static const unsigned short ppi_req[] = {
878         P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
879         P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
880         P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
881         P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
882 #if !IS_ENABLED(CONFIG_VIDEO_VS6624)
883         P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
884         P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
885 #endif
886         P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
887         0,
888 };
889 
890 static const struct ppi_info ppi_info = {
891         .type = PPI_TYPE_EPPI3,
892         .dma_ch = CH_EPPI0_CH0,
893         .irq_err = IRQ_EPPI0_STAT,
894         .base = (void __iomem *)EPPI0_STAT,
895         .pin_req = ppi_req,
896 };
897 
898 #if IS_ENABLED(CONFIG_VIDEO_VS6624)
899 static struct v4l2_input vs6624_inputs[] = {
900         {
901                 .index = 0,
902                 .name = "Camera",
903                 .type = V4L2_INPUT_TYPE_CAMERA,
904                 .std = V4L2_STD_UNKNOWN,
905         },
906 };
907 
908 static struct bcap_route vs6624_routes[] = {
909         {
910                 .input = 0,
911                 .output = 0,
912         },
913 };
914 
915 static const unsigned vs6624_ce_pin = GPIO_PE4;
916 
917 static struct bfin_capture_config bfin_capture_data = {
918         .card_name = "BF609",
919         .inputs = vs6624_inputs,
920         .num_inputs = ARRAY_SIZE(vs6624_inputs),
921         .routes = vs6624_routes,
922         .i2c_adapter_id = 0,
923         .board_info = {
924                 .type = "vs6624",
925                 .addr = 0x10,
926                 .platform_data = (void *)&vs6624_ce_pin,
927         },
928         .ppi_info = &ppi_info,
929         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
930                         | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
931         .blank_pixels = 4,
932 };
933 #endif
934 
935 #if IS_ENABLED(CONFIG_VIDEO_ADV7842)
936 #include <media/i2c/adv7842.h>
937 
938 static struct v4l2_input adv7842_inputs[] = {
939         {
940                 .index = 0,
941                 .name = "Composite",
942                 .type = V4L2_INPUT_TYPE_CAMERA,
943                 .std = V4L2_STD_ALL,
944                 .capabilities = V4L2_IN_CAP_STD,
945         },
946         {
947                 .index = 1,
948                 .name = "S-Video",
949                 .type = V4L2_INPUT_TYPE_CAMERA,
950                 .std = V4L2_STD_ALL,
951                 .capabilities = V4L2_IN_CAP_STD,
952         },
953         {
954                 .index = 2,
955                 .name = "Component",
956                 .type = V4L2_INPUT_TYPE_CAMERA,
957                 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
958         },
959         {
960                 .index = 3,
961                 .name = "VGA",
962                 .type = V4L2_INPUT_TYPE_CAMERA,
963                 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
964         },
965         {
966                 .index = 4,
967                 .name = "HDMI",
968                 .type = V4L2_INPUT_TYPE_CAMERA,
969                 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
970         },
971 };
972 
973 static struct bcap_route adv7842_routes[] = {
974         {
975                 .input = 3,
976                 .output = 0,
977                 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
978                                 | EPPI_CTL_ACTIVE656),
979         },
980         {
981                 .input = 4,
982                 .output = 0,
983         },
984         {
985                 .input = 2,
986                 .output = 0,
987         },
988         {
989                 .input = 1,
990                 .output = 0,
991         },
992         {
993                 .input = 0,
994                 .output = 1,
995                 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
996                                 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
997                                 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
998         },
999 };
1000 
1001 static struct adv7842_output_format adv7842_opf[] = {
1002         {
1003                 .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
1004                 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
1005                 .op_656_range = 1,
1006                 .blank_data = 1,
1007                 .insert_av_codes = 1,
1008         },
1009         {
1010                 .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
1011                 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
1012                 .op_656_range = 1,
1013                 .blank_data = 1,
1014         },
1015 };
1016 
1017 static struct adv7842_platform_data adv7842_data = {
1018         .opf = adv7842_opf,
1019         .num_opf = ARRAY_SIZE(adv7842_opf),
1020         .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
1021         .prim_mode = ADV7842_PRIM_MODE_SDP,
1022         .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
1023         .hdmi_free_run_enable = 1,
1024         .sdp_free_run_auto = 1,
1025         .llc_dll_phase = 0x10,
1026         .i2c_sdp_io = 0x40,
1027         .i2c_sdp = 0x41,
1028         .i2c_cp = 0x42,
1029         .i2c_vdp = 0x43,
1030         .i2c_afe = 0x44,
1031         .i2c_hdmi = 0x45,
1032         .i2c_repeater = 0x46,
1033         .i2c_edid = 0x47,
1034         .i2c_infoframe = 0x48,
1035         .i2c_cec = 0x49,
1036         .i2c_avlink = 0x4a,
1037 };
1038 
1039 static struct bfin_capture_config bfin_capture_data = {
1040         .card_name = "BF609",
1041         .inputs = adv7842_inputs,
1042         .num_inputs = ARRAY_SIZE(adv7842_inputs),
1043         .routes = adv7842_routes,
1044         .i2c_adapter_id = 0,
1045         .board_info = {
1046                 .type = "adv7842",
1047                 .addr = 0x20,
1048                 .platform_data = (void *)&adv7842_data,
1049         },
1050         .ppi_info = &ppi_info,
1051         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
1052                         | EPPI_CTL_ACTIVE656),
1053 };
1054 #endif
1055 
1056 static struct platform_device bfin_capture_device = {
1057         .name = "bfin_capture",
1058         .dev = {
1059                 .platform_data = &bfin_capture_data,
1060         },
1061 };
1062 #endif
1063 
1064 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
1065 #include <linux/videodev2.h>
1066 #include <media/blackfin/bfin_display.h>
1067 #include <media/blackfin/ppi.h>
1068 
1069 static const unsigned short ppi_req_disp[] = {
1070         P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
1071         P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
1072         P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
1073         P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
1074         P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
1075         0,
1076 };
1077 
1078 static const struct ppi_info ppi_info = {
1079         .type = PPI_TYPE_EPPI3,
1080         .dma_ch = CH_EPPI0_CH0,
1081         .irq_err = IRQ_EPPI0_STAT,
1082         .base = (void __iomem *)EPPI0_STAT,
1083         .pin_req = ppi_req_disp,
1084 };
1085 
1086 #if IS_ENABLED(CONFIG_VIDEO_ADV7511)
1087 #include <media/i2c/adv7511.h>
1088 
1089 static struct v4l2_output adv7511_outputs[] = {
1090         {
1091                 .index = 0,
1092                 .name = "HDMI",
1093                 .type = V4L2_INPUT_TYPE_CAMERA,
1094                 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
1095         },
1096 };
1097 
1098 static struct disp_route adv7511_routes[] = {
1099         {
1100                 .output = 0,
1101         },
1102 };
1103 
1104 static struct adv7511_platform_data adv7511_data = {
1105         .edid_addr = 0x7e,
1106 };
1107 
1108 static struct bfin_display_config bfin_display_data = {
1109         .card_name = "BF609",
1110         .outputs = adv7511_outputs,
1111         .num_outputs = ARRAY_SIZE(adv7511_outputs),
1112         .routes = adv7511_routes,
1113         .i2c_adapter_id = 0,
1114         .board_info = {
1115                 .type = "adv7511",
1116                 .addr = 0x39,
1117                 .platform_data = (void *)&adv7511_data,
1118         },
1119         .ppi_info = &ppi_info,
1120         .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
1121                         | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
1122                         | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
1123                         | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1124 };
1125 #endif
1126 
1127 #if IS_ENABLED(CONFIG_VIDEO_ADV7343)
1128 #include <media/i2c/adv7343.h>
1129 
1130 static struct v4l2_output adv7343_outputs[] = {
1131         {
1132                 .index = 0,
1133                 .name = "Composite",
1134                 .type = V4L2_OUTPUT_TYPE_ANALOG,
1135                 .std = V4L2_STD_ALL,
1136                 .capabilities = V4L2_OUT_CAP_STD,
1137         },
1138         {
1139                 .index = 1,
1140                 .name = "S-Video",
1141                 .type = V4L2_OUTPUT_TYPE_ANALOG,
1142                 .std = V4L2_STD_ALL,
1143                 .capabilities = V4L2_OUT_CAP_STD,
1144         },
1145         {
1146                 .index = 2,
1147                 .name = "Component",
1148                 .type = V4L2_OUTPUT_TYPE_ANALOG,
1149                 .std = V4L2_STD_ALL,
1150                 .capabilities = V4L2_OUT_CAP_STD,
1151         },
1152 
1153 };
1154 
1155 static struct disp_route adv7343_routes[] = {
1156         {
1157                 .output = ADV7343_COMPOSITE_ID,
1158         },
1159         {
1160                 .output = ADV7343_SVIDEO_ID,
1161         },
1162         {
1163                 .output = ADV7343_COMPONENT_ID,
1164         },
1165 };
1166 
1167 static struct adv7343_platform_data adv7343_data = {
1168         .mode_config = {
1169                 .sleep_mode = false,
1170                 .pll_control = false,
1171                 .dac_1 = true,
1172                 .dac_2 = true,
1173                 .dac_3 = true,
1174                 .dac_4 = true,
1175                 .dac_5 = true,
1176                 .dac_6 = true,
1177         },
1178         .sd_config = {
1179                 .sd_dac_out1 = false,
1180                 .sd_dac_out2 = false,
1181         },
1182 };
1183 
1184 static struct bfin_display_config bfin_display_data = {
1185         .card_name = "BF609",
1186         .outputs = adv7343_outputs,
1187         .num_outputs = ARRAY_SIZE(adv7343_outputs),
1188         .routes = adv7343_routes,
1189         .i2c_adapter_id = 0,
1190         .board_info = {
1191                 .type = "adv7343",
1192                 .addr = 0x2b,
1193                 .platform_data = (void *)&adv7343_data,
1194         },
1195         .ppi_info = &ppi_info_disp,
1196         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
1197                         | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
1198                         | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1199 };
1200 #endif
1201 
1202 static struct platform_device bfin_display_device = {
1203         .name = "bfin_display",
1204         .dev = {
1205                 .platform_data = &bfin_display_data,
1206         },
1207 };
1208 #endif
1209 
1210 #if defined(CONFIG_FB_BF609_NL8048) \
1211         || defined(CONFIG_FB_BF609_NL8048_MODULE)
1212 static struct resource nl8048_resources[] = {
1213         {
1214                 .start = EPPI2_STAT,
1215                 .end = EPPI2_STAT,
1216                 .flags = IORESOURCE_MEM,
1217         },
1218         {
1219                 .start = CH_EPPI2_CH0,
1220                 .end = CH_EPPI2_CH0,
1221                 .flags = IORESOURCE_DMA,
1222         },
1223         {
1224                 .start = IRQ_EPPI2_STAT,
1225                 .end = IRQ_EPPI2_STAT,
1226                 .flags = IORESOURCE_IRQ,
1227         },
1228 };
1229 static struct platform_device bfin_fb_device = {
1230         .name = "bf609_nl8048",
1231         .num_resources = ARRAY_SIZE(nl8048_resources),
1232         .resource = nl8048_resources,
1233         .dev = {
1234                 .platform_data = (void *)GPIO_PC15,
1235         },
1236 };
1237 #endif
1238 
1239 #if defined(CONFIG_BFIN_CRC)
1240 #define BFIN_CRC_NAME "bfin-crc"
1241 
1242 static struct resource bfin_crc0_resources[] = {
1243         {
1244                 .start = REG_CRC0_CTL,
1245                 .end = REG_CRC0_REVID+4,
1246                 .flags = IORESOURCE_MEM,
1247         },
1248         {
1249                 .start = IRQ_CRC0_DCNTEXP,
1250                 .end = IRQ_CRC0_DCNTEXP,
1251                 .flags = IORESOURCE_IRQ,
1252         },
1253         {
1254                 .start = CH_MEM_STREAM0_SRC_CRC0,
1255                 .end = CH_MEM_STREAM0_SRC_CRC0,
1256                 .flags = IORESOURCE_DMA,
1257         },
1258         {
1259                 .start = CH_MEM_STREAM0_DEST_CRC0,
1260                 .end = CH_MEM_STREAM0_DEST_CRC0,
1261                 .flags = IORESOURCE_DMA,
1262         },
1263 };
1264 
1265 static struct platform_device bfin_crc0_device = {
1266         .name = BFIN_CRC_NAME,
1267         .id = 0,
1268         .num_resources = ARRAY_SIZE(bfin_crc0_resources),
1269         .resource = bfin_crc0_resources,
1270 };
1271 
1272 static struct resource bfin_crc1_resources[] = {
1273         {
1274                 .start = REG_CRC1_CTL,
1275                 .end = REG_CRC1_REVID+4,
1276                 .flags = IORESOURCE_MEM,
1277         },
1278         {
1279                 .start = IRQ_CRC1_DCNTEXP,
1280                 .end = IRQ_CRC1_DCNTEXP,
1281                 .flags = IORESOURCE_IRQ,
1282         },
1283         {
1284                 .start = CH_MEM_STREAM1_SRC_CRC1,
1285                 .end = CH_MEM_STREAM1_SRC_CRC1,
1286                 .flags = IORESOURCE_DMA,
1287         },
1288         {
1289                 .start = CH_MEM_STREAM1_DEST_CRC1,
1290                 .end = CH_MEM_STREAM1_DEST_CRC1,
1291                 .flags = IORESOURCE_DMA,
1292         },
1293 };
1294 
1295 static struct platform_device bfin_crc1_device = {
1296         .name = BFIN_CRC_NAME,
1297         .id = 1,
1298         .num_resources = ARRAY_SIZE(bfin_crc1_resources),
1299         .resource = bfin_crc1_resources,
1300 };
1301 #endif
1302 
1303 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1304 #define BFIN_CRYPTO_CRC_NAME            "bfin-hmac-crc"
1305 #define BFIN_CRYPTO_CRC_POLY_DATA       0x5c5c5c5c
1306 
1307 static struct resource bfin_crypto_crc_resources[] = {
1308         {
1309                 .start = REG_CRC0_CTL,
1310                 .end = REG_CRC0_REVID+4,
1311                 .flags = IORESOURCE_MEM,
1312         },
1313         {
1314                 .start = IRQ_CRC0_DCNTEXP,
1315                 .end = IRQ_CRC0_DCNTEXP,
1316                 .flags = IORESOURCE_IRQ,
1317         },
1318         {
1319                 .start = CH_MEM_STREAM0_SRC_CRC0,
1320                 .end = CH_MEM_STREAM0_SRC_CRC0,
1321                 .flags = IORESOURCE_DMA,
1322         },
1323 };
1324 
1325 static struct platform_device bfin_crypto_crc_device = {
1326         .name = BFIN_CRYPTO_CRC_NAME,
1327         .id = 0,
1328         .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
1329         .resource = bfin_crypto_crc_resources,
1330         .dev = {
1331                 .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
1332         },
1333 };
1334 #endif
1335 
1336 #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1337 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1338         .model                  = 7877,
1339         .vref_delay_usecs       = 50,   /* internal, no capacitor */
1340         .x_plate_ohms           = 419,
1341         .y_plate_ohms           = 486,
1342         .pressure_max           = 1000,
1343         .pressure_min           = 0,
1344         .stopacq_polarity       = 1,
1345         .first_conversion_delay = 3,
1346         .acquisition_time       = 1,
1347         .averaging              = 1,
1348         .pen_down_acc_interval  = 1,
1349 };
1350 #endif
1351 
1352 #ifdef CONFIG_PINCTRL_ADI2
1353 
1354 # define ADI_PINT_DEVNAME "adi-gpio-pint"
1355 # define ADI_GPIO_DEVNAME "adi-gpio"
1356 # define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1357 
1358 static struct platform_device bfin_pinctrl_device = {
1359         .name = ADI_PINCTRL_DEVNAME,
1360         .id = 0,
1361 };
1362 
1363 static struct resource bfin_pint0_resources[] = {
1364         {
1365                 .start = PINT0_MASK_SET,
1366                 .end = PINT0_LATCH + 3,
1367                 .flags = IORESOURCE_MEM,
1368         },
1369         {
1370                 .start = IRQ_PINT0,
1371                 .end = IRQ_PINT0,
1372                 .flags = IORESOURCE_IRQ,
1373         },
1374 };
1375 
1376 static struct platform_device bfin_pint0_device = {
1377         .name = ADI_PINT_DEVNAME,
1378         .id = 0,
1379         .num_resources = ARRAY_SIZE(bfin_pint0_resources),
1380         .resource = bfin_pint0_resources,
1381 };
1382 
1383 static struct resource bfin_pint1_resources[] = {
1384         {
1385                 .start = PINT1_MASK_SET,
1386                 .end = PINT1_LATCH + 3,
1387                 .flags = IORESOURCE_MEM,
1388         },
1389         {
1390                 .start = IRQ_PINT1,
1391                 .end = IRQ_PINT1,
1392                 .flags = IORESOURCE_IRQ,
1393         },
1394 };
1395 
1396 static struct platform_device bfin_pint1_device = {
1397         .name = ADI_PINT_DEVNAME,
1398         .id = 1,
1399         .num_resources = ARRAY_SIZE(bfin_pint1_resources),
1400         .resource = bfin_pint1_resources,
1401 };
1402 
1403 static struct resource bfin_pint2_resources[] = {
1404         {
1405                 .start = PINT2_MASK_SET,
1406                 .end = PINT2_LATCH + 3,
1407                 .flags = IORESOURCE_MEM,
1408         },
1409         {
1410                 .start = IRQ_PINT2,
1411                 .end = IRQ_PINT2,
1412                 .flags = IORESOURCE_IRQ,
1413         },
1414 };
1415 
1416 static struct platform_device bfin_pint2_device = {
1417         .name = ADI_PINT_DEVNAME,
1418         .id = 2,
1419         .num_resources = ARRAY_SIZE(bfin_pint2_resources),
1420         .resource = bfin_pint2_resources,
1421 };
1422 
1423 static struct resource bfin_pint3_resources[] = {
1424         {
1425                 .start = PINT3_MASK_SET,
1426                 .end = PINT3_LATCH + 3,
1427                 .flags = IORESOURCE_MEM,
1428         },
1429         {
1430                 .start = IRQ_PINT3,
1431                 .end = IRQ_PINT3,
1432                 .flags = IORESOURCE_IRQ,
1433         },
1434 };
1435 
1436 static struct platform_device bfin_pint3_device = {
1437         .name = ADI_PINT_DEVNAME,
1438         .id = 3,
1439         .num_resources = ARRAY_SIZE(bfin_pint3_resources),
1440         .resource = bfin_pint3_resources,
1441 };
1442 
1443 static struct resource bfin_pint4_resources[] = {
1444         {
1445                 .start = PINT4_MASK_SET,
1446                 .end = PINT4_LATCH + 3,
1447                 .flags = IORESOURCE_MEM,
1448         },
1449         {
1450                 .start = IRQ_PINT4,
1451                 .end = IRQ_PINT4,
1452                 .flags = IORESOURCE_IRQ,
1453         },
1454 };
1455 
1456 static struct platform_device bfin_pint4_device = {
1457         .name = ADI_PINT_DEVNAME,
1458         .id = 4,
1459         .num_resources = ARRAY_SIZE(bfin_pint4_resources),
1460         .resource = bfin_pint4_resources,
1461 };
1462 
1463 static struct resource bfin_pint5_resources[] = {
1464         {
1465                 .start = PINT5_MASK_SET,
1466                 .end = PINT5_LATCH + 3,
1467                 .flags = IORESOURCE_MEM,
1468         },
1469         {
1470                 .start = IRQ_PINT5,
1471                 .end = IRQ_PINT5,
1472                 .flags = IORESOURCE_IRQ,
1473         },
1474 };
1475 
1476 static struct platform_device bfin_pint5_device = {
1477         .name = ADI_PINT_DEVNAME,
1478         .id = 5,
1479         .num_resources = ARRAY_SIZE(bfin_pint5_resources),
1480         .resource = bfin_pint5_resources,
1481 };
1482 
1483 static struct resource bfin_gpa_resources[] = {
1484         {
1485                 .start = PORTA_FER,
1486                 .end = PORTA_MUX + 3,
1487                 .flags = IORESOURCE_MEM,
1488         },
1489         {       /* optional */
1490                 .start = IRQ_PA0,
1491                 .end = IRQ_PA0,
1492                 .flags = IORESOURCE_IRQ,
1493         },
1494 };
1495 
1496 static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
1497         .port_pin_base  = GPIO_PA0,
1498         .port_width     = GPIO_BANKSIZE,
1499         .pint_id        = 0,            /* PINT0 */
1500         .pint_assign    = true,         /* PINT upper 16 bit */
1501         .pint_map       = 0,            /* mapping mask in PINT */
1502 };
1503 
1504 static struct platform_device bfin_gpa_device = {
1505         .name = ADI_GPIO_DEVNAME,
1506         .id = 0,
1507         .num_resources = ARRAY_SIZE(bfin_gpa_resources),
1508         .resource = bfin_gpa_resources,
1509         .dev = {
1510                 .platform_data = &bfin_gpa_pdata, /* Passed to driver */
1511         },
1512 };
1513 
1514 static struct resource bfin_gpb_resources[] = {
1515         {
1516                 .start = PORTB_FER,
1517                 .end = PORTB_MUX + 3,
1518                 .flags = IORESOURCE_MEM,
1519         },
1520         {
1521                 .start = IRQ_PB0,
1522                 .end = IRQ_PB0,
1523                 .flags = IORESOURCE_IRQ,
1524         },
1525 };
1526 
1527 static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
1528         .port_pin_base  = GPIO_PB0,
1529         .port_width     = GPIO_BANKSIZE,
1530         .pint_id        = 0,
1531         .pint_assign    = false,
1532         .pint_map       = 1,
1533 };
1534 
1535 static struct platform_device bfin_gpb_device = {
1536         .name = ADI_GPIO_DEVNAME,
1537         .id = 1,
1538         .num_resources = ARRAY_SIZE(bfin_gpb_resources),
1539         .resource = bfin_gpb_resources,
1540         .dev = {
1541                 .platform_data = &bfin_gpb_pdata, /* Passed to driver */
1542         },
1543 };
1544 
1545 static struct resource bfin_gpc_resources[] = {
1546         {
1547                 .start = PORTC_FER,
1548                 .end = PORTC_MUX + 3,
1549                 .flags = IORESOURCE_MEM,
1550         },
1551         {
1552                 .start = IRQ_PC0,
1553                 .end = IRQ_PC0,
1554                 .flags = IORESOURCE_IRQ,
1555         },
1556 };
1557 
1558 static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
1559         .port_pin_base  = GPIO_PC0,
1560         .port_width     = GPIO_BANKSIZE,
1561         .pint_id        = 1,
1562         .pint_assign    = false,
1563         .pint_map       = 1,
1564 };
1565 
1566 static struct platform_device bfin_gpc_device = {
1567         .name = ADI_GPIO_DEVNAME,
1568         .id = 2,
1569         .num_resources = ARRAY_SIZE(bfin_gpc_resources),
1570         .resource = bfin_gpc_resources,
1571         .dev = {
1572                 .platform_data = &bfin_gpc_pdata, /* Passed to driver */
1573         },
1574 };
1575 
1576 static struct resource bfin_gpd_resources[] = {
1577         {
1578                 .start = PORTD_FER,
1579                 .end = PORTD_MUX + 3,
1580                 .flags = IORESOURCE_MEM,
1581         },
1582         {
1583                 .start = IRQ_PD0,
1584                 .end = IRQ_PD0,
1585                 .flags = IORESOURCE_IRQ,
1586         },
1587 };
1588 
1589 static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
1590         .port_pin_base  = GPIO_PD0,
1591         .port_width     = GPIO_BANKSIZE,
1592         .pint_id        = 2,
1593         .pint_assign    = false,
1594         .pint_map       = 1,
1595 };
1596 
1597 static struct platform_device bfin_gpd_device = {
1598         .name = ADI_GPIO_DEVNAME,
1599         .id = 3,
1600         .num_resources = ARRAY_SIZE(bfin_gpd_resources),
1601         .resource = bfin_gpd_resources,
1602         .dev = {
1603                 .platform_data = &bfin_gpd_pdata, /* Passed to driver */
1604         },
1605 };
1606 
1607 static struct resource bfin_gpe_resources[] = {
1608         {
1609                 .start = PORTE_FER,
1610                 .end = PORTE_MUX + 3,
1611                 .flags = IORESOURCE_MEM,
1612         },
1613         {
1614                 .start = IRQ_PE0,
1615                 .end = IRQ_PE0,
1616                 .flags = IORESOURCE_IRQ,
1617         },
1618 };
1619 
1620 static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
1621         .port_pin_base  = GPIO_PE0,
1622         .port_width     = GPIO_BANKSIZE,
1623         .pint_id        = 3,
1624         .pint_assign    = false,
1625         .pint_map       = 1,
1626 };
1627 
1628 static struct platform_device bfin_gpe_device = {
1629         .name = ADI_GPIO_DEVNAME,
1630         .id = 4,
1631         .num_resources = ARRAY_SIZE(bfin_gpe_resources),
1632         .resource = bfin_gpe_resources,
1633         .dev = {
1634                 .platform_data = &bfin_gpe_pdata, /* Passed to driver */
1635         },
1636 };
1637 
1638 static struct resource bfin_gpf_resources[] = {
1639         {
1640                 .start = PORTF_FER,
1641                 .end = PORTF_MUX + 3,
1642                 .flags = IORESOURCE_MEM,
1643         },
1644         {
1645                 .start = IRQ_PF0,
1646                 .end = IRQ_PF0,
1647                 .flags = IORESOURCE_IRQ,
1648         },
1649 };
1650 
1651 static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
1652         .port_pin_base  = GPIO_PF0,
1653         .port_width     = GPIO_BANKSIZE,
1654         .pint_id        = 4,
1655         .pint_assign    = false,
1656         .pint_map       = 1,
1657 };
1658 
1659 static struct platform_device bfin_gpf_device = {
1660         .name = ADI_GPIO_DEVNAME,
1661         .id = 5,
1662         .num_resources = ARRAY_SIZE(bfin_gpf_resources),
1663         .resource = bfin_gpf_resources,
1664         .dev = {
1665                 .platform_data = &bfin_gpf_pdata, /* Passed to driver */
1666         },
1667 };
1668 
1669 static struct resource bfin_gpg_resources[] = {
1670         {
1671                 .start = PORTG_FER,
1672                 .end = PORTG_MUX + 3,
1673                 .flags = IORESOURCE_MEM,
1674         },
1675         {
1676                 .start = IRQ_PG0,
1677                 .end = IRQ_PG0,
1678                 .flags = IORESOURCE_IRQ,
1679         },
1680 };
1681 
1682 static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
1683         .port_pin_base  = GPIO_PG0,
1684         .port_width     = GPIO_BANKSIZE,
1685         .pint_id        = 5,
1686         .pint_assign    = false,
1687         .pint_map       = 1,
1688 };
1689 
1690 static struct platform_device bfin_gpg_device = {
1691         .name = ADI_GPIO_DEVNAME,
1692         .id = 6,
1693         .num_resources = ARRAY_SIZE(bfin_gpg_resources),
1694         .resource = bfin_gpg_resources,
1695         .dev = {
1696                 .platform_data = &bfin_gpg_pdata, /* Passed to driver */
1697         },
1698 };
1699 
1700 #endif
1701 
1702 #if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
1703 #include <linux/input.h>
1704 #include <linux/gpio_keys.h>
1705 
1706 static struct gpio_keys_button bfin_gpio_keys_table[] = {
1707         {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
1708         {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
1709 };
1710 
1711 static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1712         .buttons        = bfin_gpio_keys_table,
1713         .nbuttons       = ARRAY_SIZE(bfin_gpio_keys_table),
1714 };
1715 
1716 static struct platform_device bfin_device_gpiokeys = {
1717         .name      = "gpio-keys",
1718         .dev = {
1719                 .platform_data = &bfin_gpio_keys_data,
1720         },
1721 };
1722 #endif
1723 
1724 static struct spi_board_info bfin_spi_board_info[] __initdata = {
1725 #if IS_ENABLED(CONFIG_MTD_M25P80)
1726         {
1727                 /* the modalias must be the same as spi device driver name */
1728                 .modalias = "m25p80", /* Name of spi_driver for this device */
1729                 .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
1730                 .bus_num = 0, /* Framework bus number */
1731                 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
1732                 .platform_data = &bfin_spi_flash_data,
1733                 .controller_data = &spi_flash_chip_info,
1734                 .mode = SPI_MODE_3,
1735         },
1736 #endif
1737 #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1738         {
1739                 .modalias               = "ad7877",
1740                 .platform_data          = &bfin_ad7877_ts_info,
1741                 .irq                    = IRQ_PD9,
1742                 .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
1743                 .bus_num                = 0,
1744                 .chip_select            = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
1745         },
1746 #endif
1747 #if IS_ENABLED(CONFIG_SPI_SPIDEV)
1748         {
1749                 .modalias = "spidev",
1750                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
1751                 .bus_num = 0,
1752                 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
1753                 .controller_data = &spidev_chip_info,
1754         },
1755 #endif
1756 #if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
1757         {
1758                 .modalias               = "adxl34x",
1759                 .platform_data          = &adxl34x_info,
1760                 .irq                    = IRQ_PC5,
1761                 .max_speed_hz           = 5000000,     /* max spi clock (SCK) speed in HZ */
1762                 .bus_num                = 1,
1763                 .chip_select            = 2,
1764                 .mode = SPI_MODE_3,
1765         },
1766 #endif
1767 };
1768 #if IS_ENABLED(CONFIG_SPI_ADI_V3)
1769 /* SPI (0) */
1770 static struct resource bfin_spi0_resource[] = {
1771         {
1772                 .start = SPI0_REGBASE,
1773                 .end   = SPI0_REGBASE + 0xFF,
1774                 .flags = IORESOURCE_MEM,
1775         },
1776         {
1777                 .start = CH_SPI0_TX,
1778                 .end   = CH_SPI0_TX,
1779                 .flags = IORESOURCE_DMA,
1780         },
1781         {
1782                 .start = CH_SPI0_RX,
1783                 .end   = CH_SPI0_RX,
1784                 .flags = IORESOURCE_DMA,
1785         },
1786 };
1787 
1788 /* SPI (1) */
1789 static struct resource bfin_spi1_resource[] = {
1790         {
1791                 .start = SPI1_REGBASE,
1792                 .end   = SPI1_REGBASE + 0xFF,
1793                 .flags = IORESOURCE_MEM,
1794         },
1795         {
1796                 .start = CH_SPI1_TX,
1797                 .end   = CH_SPI1_TX,
1798                 .flags = IORESOURCE_DMA,
1799         },
1800         {
1801                 .start = CH_SPI1_RX,
1802                 .end   = CH_SPI1_RX,
1803                 .flags = IORESOURCE_DMA,
1804         },
1805 
1806 };
1807 
1808 /* SPI controller data */
1809 static struct adi_spi3_master bf60x_spi_master_info0 = {
1810         .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1811         .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1812 };
1813 
1814 static struct platform_device bf60x_spi_master0 = {
1815         .name = "adi-spi3",
1816         .id = 0, /* Bus number */
1817         .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1818         .resource = bfin_spi0_resource,
1819         .dev = {
1820                 .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
1821         },
1822 };
1823 
1824 static struct adi_spi3_master bf60x_spi_master_info1 = {
1825         .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1826         .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1827 };
1828 
1829 static struct platform_device bf60x_spi_master1 = {
1830         .name = "adi-spi3",
1831         .id = 1, /* Bus number */
1832         .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1833         .resource = bfin_spi1_resource,
1834         .dev = {
1835                 .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
1836         },
1837 };
1838 #endif  /* spi master and devices */
1839 
1840 #if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
1841 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1842 
1843 static struct resource bfin_twi0_resource[] = {
1844         [0] = {
1845                 .start = TWI0_CLKDIV,
1846                 .end   = TWI0_CLKDIV + 0xFF,
1847                 .flags = IORESOURCE_MEM,
1848         },
1849         [1] = {
1850                 .start = IRQ_TWI0,
1851                 .end   = IRQ_TWI0,
1852                 .flags = IORESOURCE_IRQ,
1853         },
1854 };
1855 
1856 static struct platform_device i2c_bfin_twi0_device = {
1857         .name = "i2c-bfin-twi",
1858         .id = 0,
1859         .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1860         .resource = bfin_twi0_resource,
1861         .dev = {
1862                 .platform_data = &bfin_twi0_pins,
1863         },
1864 };
1865 
1866 static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1867 
1868 static struct resource bfin_twi1_resource[] = {
1869         [0] = {
1870                 .start = TWI1_CLKDIV,
1871                 .end   = TWI1_CLKDIV + 0xFF,
1872                 .flags = IORESOURCE_MEM,
1873         },
1874         [1] = {
1875                 .start = IRQ_TWI1,
1876                 .end   = IRQ_TWI1,
1877                 .flags = IORESOURCE_IRQ,
1878         },
1879 };
1880 
1881 static struct platform_device i2c_bfin_twi1_device = {
1882         .name = "i2c-bfin-twi",
1883         .id = 1,
1884         .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1885         .resource = bfin_twi1_resource,
1886         .dev = {
1887                 .platform_data = &bfin_twi1_pins,
1888         },
1889 };
1890 #endif
1891 
1892 #if IS_ENABLED(CONFIG_GPIO_MCP23S08)
1893 #include <linux/spi/mcp23s08.h>
1894 static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch0 = {
1895         .base = 120,
1896 };
1897 static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch1 = {
1898         .base = 130,
1899 };
1900 static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch2 = {
1901         .base = 140,
1902 };
1903 # if IS_ENABLED(CONFIG_VIDEO_ADV7842)
1904 static const struct mcp23s08_platform_data bfin_adv7842_soft_switch = {
1905         .base = 150,
1906 };
1907 # endif
1908 # if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
1909 static const struct mcp23s08_platform_data bfin_adv7511_soft_switch = {
1910         .base = 160,
1911 };
1912 # endif
1913 #endif
1914 
1915 static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1916 #if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
1917         {
1918                 I2C_BOARD_INFO("adxl34x", 0x53),
1919                 .irq = IRQ_PC5,
1920                 .platform_data = (void *)&adxl34x_info,
1921         },
1922 #endif
1923 #if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
1924         {
1925                 I2C_BOARD_INFO("adau1761", 0x38),
1926                 .platform_data = (void *)&adau1761_info
1927         },
1928 #endif
1929 #if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
1930         {
1931                 I2C_BOARD_INFO("ssm2602", 0x1b),
1932         },
1933 #endif
1934 #if IS_ENABLED(CONFIG_GPIO_MCP23S08)
1935         {
1936                 I2C_BOARD_INFO("mcp23017", 0x21),
1937                 .platform_data = (void *)&bfin_mcp23s08_soft_switch0
1938         },
1939         {
1940                 I2C_BOARD_INFO("mcp23017", 0x22),
1941                 .platform_data = (void *)&bfin_mcp23s08_soft_switch1
1942         },
1943         {
1944                 I2C_BOARD_INFO("mcp23017", 0x23),
1945                 .platform_data = (void *)&bfin_mcp23s08_soft_switch2
1946         },
1947 # if IS_ENABLED(CONFIG_VIDEO_ADV7842)
1948         {
1949                 I2C_BOARD_INFO("mcp23017", 0x26),
1950                 .platform_data = (void *)&bfin_adv7842_soft_switch
1951         },
1952 # endif
1953 # if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
1954         {
1955                 I2C_BOARD_INFO("mcp23017", 0x25),
1956                 .platform_data = (void *)&bfin_adv7511_soft_switch
1957         },
1958 # endif
1959 #endif
1960 };
1961 
1962 static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1963 };
1964 
1965 static const unsigned int cclk_vlev_datasheet[] =
1966 {
1967 /*
1968  * Internal VLEV BF54XSBBC1533
1969  ****temporarily using these values until data sheet is updated
1970  */
1971         VRPAIR(VLEV_085, 150000000),
1972         VRPAIR(VLEV_090, 250000000),
1973         VRPAIR(VLEV_110, 276000000),
1974         VRPAIR(VLEV_115, 301000000),
1975         VRPAIR(VLEV_120, 525000000),
1976         VRPAIR(VLEV_125, 550000000),
1977         VRPAIR(VLEV_130, 600000000),
1978 };
1979 
1980 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1981         .tuple_tab = cclk_vlev_datasheet,
1982         .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1983         .vr_settling_time = 25 /* us */,
1984 };
1985 
1986 static struct platform_device bfin_dpmc = {
1987         .name = "bfin dpmc",
1988         .dev = {
1989                 .platform_data = &bfin_dmpc_vreg_data,
1990         },
1991 };
1992 
1993 static struct platform_device *ezkit_devices[] __initdata = {
1994 
1995         &bfin_dpmc,
1996 #if defined(CONFIG_PINCTRL_ADI2)
1997         &bfin_pinctrl_device,
1998         &bfin_pint0_device,
1999         &bfin_pint1_device,
2000         &bfin_pint2_device,
2001         &bfin_pint3_device,
2002         &bfin_pint4_device,
2003         &bfin_pint5_device,
2004         &bfin_gpa_device,
2005         &bfin_gpb_device,
2006         &bfin_gpc_device,
2007         &bfin_gpd_device,
2008         &bfin_gpe_device,
2009         &bfin_gpf_device,
2010         &bfin_gpg_device,
2011 #endif
2012 
2013 #if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
2014         &rtc_device,
2015 #endif
2016 
2017 #if IS_ENABLED(CONFIG_SERIAL_BFIN)
2018 #ifdef CONFIG_SERIAL_BFIN_UART0
2019         &bfin_uart0_device,
2020 #endif
2021 #ifdef CONFIG_SERIAL_BFIN_UART1
2022         &bfin_uart1_device,
2023 #endif
2024 #endif
2025 
2026 #if IS_ENABLED(CONFIG_BFIN_SIR)
2027 #ifdef CONFIG_BFIN_SIR0
2028         &bfin_sir0_device,
2029 #endif
2030 #ifdef CONFIG_BFIN_SIR1
2031         &bfin_sir1_device,
2032 #endif
2033 #endif
2034 
2035 #if IS_ENABLED(CONFIG_STMMAC_ETH)
2036         &bfin_eth_device,
2037 #endif
2038 
2039 #if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
2040         &musb_device,
2041 #endif
2042 
2043 #if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
2044         &bfin_isp1760_device,
2045 #endif
2046 
2047 #if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
2048 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2049         &bfin_sport0_uart_device,
2050 #endif
2051 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2052         &bfin_sport1_uart_device,
2053 #endif
2054 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
2055         &bfin_sport2_uart_device,
2056 #endif
2057 #endif
2058 
2059 #if IS_ENABLED(CONFIG_CAN_BFIN)
2060         &bfin_can0_device,
2061 #endif
2062 
2063 #if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
2064         &bfin_nand_device,
2065 #endif
2066 
2067 #if IS_ENABLED(CONFIG_SDH_BFIN)
2068         &bfin_sdh_device,
2069 #endif
2070 
2071 #if IS_ENABLED(CONFIG_SPI_ADI_V3)
2072         &bf60x_spi_master0,
2073         &bf60x_spi_master1,
2074 #endif
2075 
2076 #if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
2077         &bfin_rotary_device,
2078 #endif
2079 
2080 #if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
2081         &i2c_bfin_twi0_device,
2082 #if !defined(CONFIG_BF542)
2083         &i2c_bfin_twi1_device,
2084 #endif
2085 #endif
2086 
2087 #if defined(CONFIG_BFIN_CRC)
2088         &bfin_crc0_device,
2089         &bfin_crc1_device,
2090 #endif
2091 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
2092         &bfin_crypto_crc_device,
2093 #endif
2094 
2095 #if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
2096         &bfin_device_gpiokeys,
2097 #endif
2098 
2099 #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
2100         &ezkit_flash_device,
2101 #endif
2102 #if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
2103         &bfin_pcm,
2104 #endif
2105 #if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
2106         &bfin_i2s,
2107 #endif
2108 #if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
2109         &bfin_ad1836_machine,
2110 #endif
2111 #if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
2112         &adau1761_device,
2113 #endif
2114 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
2115         &bfin_capture_device,
2116 #endif
2117 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
2118         &bfin_display_device,
2119 #endif
2120 
2121 };
2122 
2123 /* Pin control settings */
2124 static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2125         /* per-device maps */
2126         PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0",  "pinctrl-adi2.0", NULL, "uart0"),
2127         PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1",  "pinctrl-adi2.0", NULL, "uart1"),
2128         PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0",  "pinctrl-adi2.0", NULL, "uart0"),
2129         PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1",  "pinctrl-adi2.0", NULL, "uart1"),
2130         PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0",  "pinctrl-adi2.0", NULL, "rsi0"),
2131         PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0",  "pinctrl-adi2.0", NULL, "eth0"),
2132         PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0",  "pinctrl-adi2.0", NULL, "spi0"),
2133         PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1",  "pinctrl-adi2.0", NULL, "spi1"),
2134         PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0",  "pinctrl-adi2.0", NULL, "twi0"),
2135         PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1",  "pinctrl-adi2.0", NULL, "twi1"),
2136         PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary",  "pinctrl-adi2.0", NULL, "rotary"),
2137         PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0",  "pinctrl-adi2.0", NULL, "can0"),
2138         PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0",  "pinctrl-adi2.0", NULL, "smc0"),
2139         PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.0",  "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
2140         PIN_MAP_MUX_GROUP("bfin_display.0", "8bit",  "pinctrl-adi2.0", "ppi2_8bgrp", "ppi2"),
2141         PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0",  "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
2142         PIN_MAP_MUX_GROUP("bfin_display.0", "16bit",  "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
2143         PIN_MAP_MUX_GROUP("bfin_capture.0", "8bit",  "pinctrl-adi2.0", "ppi0_8bgrp", "ppi0"),
2144         PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0",  "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
2145         PIN_MAP_MUX_GROUP("bfin_capture.0", "16bit",  "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
2146         PIN_MAP_MUX_GROUP("bfin_capture.0", "24bit",  "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"),
2147         PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0",  "pinctrl-adi2.0", NULL, "sport0"),
2148         PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0",  "pinctrl-adi2.0", NULL, "sport0"),
2149         PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1",  "pinctrl-adi2.0", NULL, "sport1"),
2150         PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1",  "pinctrl-adi2.0", NULL, "sport1"),
2151         PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2",  "pinctrl-adi2.0", NULL, "sport2"),
2152         PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2",  "pinctrl-adi2.0", NULL, "sport2"),
2153 };
2154 
2155 static int __init ezkit_init(void)
2156 {
2157         printk(KERN_INFO "%s(): registering device resources\n", __func__);
2158 
2159         /* Initialize pinmuxing */
2160         pinctrl_register_mappings(bfin_pinmux_map,
2161                                 ARRAY_SIZE(bfin_pinmux_map));
2162 
2163         i2c_register_board_info(0, bfin_i2c_board_info0,
2164                                 ARRAY_SIZE(bfin_i2c_board_info0));
2165         i2c_register_board_info(1, bfin_i2c_board_info1,
2166                                 ARRAY_SIZE(bfin_i2c_board_info1));
2167 
2168         platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
2169 
2170         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
2171 
2172         return 0;
2173 }
2174 
2175 arch_initcall(ezkit_init);
2176 
2177 static struct platform_device *ezkit_early_devices[] __initdata = {
2178 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
2179 #ifdef CONFIG_SERIAL_BFIN_UART0
2180         &bfin_uart0_device,
2181 #endif
2182 #ifdef CONFIG_SERIAL_BFIN_UART1
2183         &bfin_uart1_device,
2184 #endif
2185 #endif
2186 };
2187 
2188 void __init native_machine_early_platform_add_devices(void)
2189 {
2190         printk(KERN_INFO "register early platform devices\n");
2191         early_platform_add_devices(ezkit_early_devices,
2192                 ARRAY_SIZE(ezkit_early_devices));
2193 }
2194 

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