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TOMOYO Linux Cross Reference
Linux/arch/blackfin/mach-common/ints-priority.c

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  1 /*
  2  * Set up the interrupt priorities
  3  *
  4  * Copyright  2004-2009 Analog Devices Inc.
  5  *                 2003 Bas Vermeulen <bas@buyways.nl>
  6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
  7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
  8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
  9  *                 1996 Roman Zippel
 10  *
 11  * Licensed under the GPL-2
 12  */
 13 
 14 #include <linux/module.h>
 15 #include <linux/kernel_stat.h>
 16 #include <linux/seq_file.h>
 17 #include <linux/irq.h>
 18 #include <linux/sched.h>
 19 #include <linux/syscore_ops.h>
 20 #include <asm/delay.h>
 21 #ifdef CONFIG_IPIPE
 22 #include <linux/ipipe.h>
 23 #endif
 24 #include <asm/traps.h>
 25 #include <asm/blackfin.h>
 26 #include <asm/gpio.h>
 27 #include <asm/irq_handler.h>
 28 #include <asm/dpmc.h>
 29 
 30 #ifndef CONFIG_BF60x
 31 # define SIC_SYSIRQ(irq)        (irq - (IRQ_CORETMR + 1))
 32 #else
 33 # define SIC_SYSIRQ(irq)        ((irq) - IVG15)
 34 #endif
 35 
 36 /*
 37  * NOTES:
 38  * - we have separated the physical Hardware interrupt from the
 39  * levels that the LINUX kernel sees (see the description in irq.h)
 40  * -
 41  */
 42 
 43 #ifndef CONFIG_SMP
 44 /* Initialize this to an actual value to force it into the .data
 45  * section so that we know it is properly initialized at entry into
 46  * the kernel but before bss is initialized to zero (which is where
 47  * it would live otherwise).  The 0x1f magic represents the IRQs we
 48  * cannot actually mask out in hardware.
 49  */
 50 unsigned long bfin_irq_flags = 0x1f;
 51 EXPORT_SYMBOL(bfin_irq_flags);
 52 #endif
 53 
 54 #ifdef CONFIG_PM
 55 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
 56 unsigned vr_wakeup;
 57 #endif
 58 
 59 #ifndef CONFIG_BF60x
 60 static struct ivgx {
 61         /* irq number for request_irq, available in mach-bf5xx/irq.h */
 62         unsigned int irqno;
 63         /* corresponding bit in the SIC_ISR register */
 64         unsigned int isrflag;
 65 } ivg_table[NR_PERI_INTS];
 66 
 67 static struct ivg_slice {
 68         /* position of first irq in ivg_table for given ivg */
 69         struct ivgx *ifirst;
 70         struct ivgx *istop;
 71 } ivg7_13[IVG13 - IVG7 + 1];
 72 
 73 
 74 /*
 75  * Search SIC_IAR and fill tables with the irqvalues
 76  * and their positions in the SIC_ISR register.
 77  */
 78 static void __init search_IAR(void)
 79 {
 80         unsigned ivg, irq_pos = 0;
 81         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
 82                 int irqN;
 83 
 84                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
 85 
 86                 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
 87                         int irqn;
 88                         u32 iar =
 89                                 bfin_read32((unsigned long *)SIC_IAR0 +
 90 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
 91         defined(CONFIG_BF538) || defined(CONFIG_BF539)
 92                                 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
 93 #else
 94                                 (irqN >> 3)
 95 #endif
 96                                 );
 97                         for (irqn = irqN; irqn < irqN + 4; ++irqn) {
 98                                 int iar_shift = (irqn & 7) * 4;
 99                                 if (ivg == (0xf & (iar >> iar_shift))) {
100                                         ivg_table[irq_pos].irqno = IVG7 + irqn;
101                                         ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
102                                         ivg7_13[ivg].istop++;
103                                         irq_pos++;
104                                 }
105                         }
106                 }
107         }
108 }
109 #endif
110 
111 /*
112  * This is for core internal IRQs
113  */
114 void bfin_ack_noop(struct irq_data *d)
115 {
116         /* Dummy function.  */
117 }
118 
119 static void bfin_core_mask_irq(struct irq_data *d)
120 {
121         bfin_irq_flags &= ~(1 << d->irq);
122         if (!hard_irqs_disabled())
123                 hard_local_irq_enable();
124 }
125 
126 static void bfin_core_unmask_irq(struct irq_data *d)
127 {
128         bfin_irq_flags |= 1 << d->irq;
129         /*
130          * If interrupts are enabled, IMASK must contain the same value
131          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
132          * are currently disabled we need not do anything; one of the
133          * callers will take care of setting IMASK to the proper value
134          * when reenabling interrupts.
135          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
136          * what we need.
137          */
138         if (!hard_irqs_disabled())
139                 hard_local_irq_enable();
140         return;
141 }
142 
143 void bfin_internal_mask_irq(unsigned int irq)
144 {
145         unsigned long flags = hard_local_irq_save();
146 #ifndef CONFIG_BF60x
147 #ifdef SIC_IMASK0
148         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
149         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
150         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
151                         ~(1 << mask_bit));
152 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
153         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
154                         ~(1 << mask_bit));
155 # endif
156 #else
157         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
158                         ~(1 << SIC_SYSIRQ(irq)));
159 #endif /* end of SIC_IMASK0 */
160 #endif
161         hard_local_irq_restore(flags);
162 }
163 
164 static void bfin_internal_mask_irq_chip(struct irq_data *d)
165 {
166         bfin_internal_mask_irq(d->irq);
167 }
168 
169 #ifdef CONFIG_SMP
170 void bfin_internal_unmask_irq_affinity(unsigned int irq,
171                 const struct cpumask *affinity)
172 #else
173 void bfin_internal_unmask_irq(unsigned int irq)
174 #endif
175 {
176         unsigned long flags = hard_local_irq_save();
177 
178 #ifndef CONFIG_BF60x
179 #ifdef SIC_IMASK0
180         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
181         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
182 # ifdef CONFIG_SMP
183         if (cpumask_test_cpu(0, affinity))
184 # endif
185                 bfin_write_SIC_IMASK(mask_bank,
186                                 bfin_read_SIC_IMASK(mask_bank) |
187                                 (1 << mask_bit));
188 # ifdef CONFIG_SMP
189         if (cpumask_test_cpu(1, affinity))
190                 bfin_write_SICB_IMASK(mask_bank,
191                                 bfin_read_SICB_IMASK(mask_bank) |
192                                 (1 << mask_bit));
193 # endif
194 #else
195         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
196                         (1 << SIC_SYSIRQ(irq)));
197 #endif
198 #endif
199         hard_local_irq_restore(flags);
200 }
201 
202 #ifdef CONFIG_BF60x
203 static void bfin_sec_preflow_handler(struct irq_data *d)
204 {
205         unsigned long flags = hard_local_irq_save();
206         unsigned int sid = SIC_SYSIRQ(d->irq);
207 
208         bfin_write_SEC_SCI(0, SEC_CSID, sid);
209 
210         hard_local_irq_restore(flags);
211 }
212 
213 static void bfin_sec_mask_ack_irq(struct irq_data *d)
214 {
215         unsigned long flags = hard_local_irq_save();
216         unsigned int sid = SIC_SYSIRQ(d->irq);
217 
218         bfin_write_SEC_SCI(0, SEC_CSID, sid);
219 
220         hard_local_irq_restore(flags);
221 }
222 
223 static void bfin_sec_unmask_irq(struct irq_data *d)
224 {
225         unsigned long flags = hard_local_irq_save();
226         unsigned int sid = SIC_SYSIRQ(d->irq);
227 
228         bfin_write32(SEC_END, sid);
229 
230         hard_local_irq_restore(flags);
231 }
232 
233 static void bfin_sec_enable_ssi(unsigned int sid)
234 {
235         unsigned long flags = hard_local_irq_save();
236         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
237 
238         reg_sctl |= SEC_SCTL_SRC_EN;
239         bfin_write_SEC_SCTL(sid, reg_sctl);
240 
241         hard_local_irq_restore(flags);
242 }
243 
244 static void bfin_sec_disable_ssi(unsigned int sid)
245 {
246         unsigned long flags = hard_local_irq_save();
247         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
248 
249         reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
250         bfin_write_SEC_SCTL(sid, reg_sctl);
251 
252         hard_local_irq_restore(flags);
253 }
254 
255 static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
256 {
257         unsigned long flags = hard_local_irq_save();
258         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
259 
260         reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
261         bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
262 
263         hard_local_irq_restore(flags);
264 }
265 
266 static void bfin_sec_enable_sci(unsigned int sid)
267 {
268         unsigned long flags = hard_local_irq_save();
269         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
270 
271         if (sid == SIC_SYSIRQ(IRQ_WATCH0))
272                 reg_sctl |= SEC_SCTL_FAULT_EN;
273         else
274                 reg_sctl |= SEC_SCTL_INT_EN;
275         bfin_write_SEC_SCTL(sid, reg_sctl);
276 
277         hard_local_irq_restore(flags);
278 }
279 
280 static void bfin_sec_disable_sci(unsigned int sid)
281 {
282         unsigned long flags = hard_local_irq_save();
283         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
284 
285         reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
286         bfin_write_SEC_SCTL(sid, reg_sctl);
287 
288         hard_local_irq_restore(flags);
289 }
290 
291 static void bfin_sec_enable(struct irq_data *d)
292 {
293         unsigned long flags = hard_local_irq_save();
294         unsigned int sid = SIC_SYSIRQ(d->irq);
295 
296         bfin_sec_enable_sci(sid);
297         bfin_sec_enable_ssi(sid);
298 
299         hard_local_irq_restore(flags);
300 }
301 
302 static void bfin_sec_disable(struct irq_data *d)
303 {
304         unsigned long flags = hard_local_irq_save();
305         unsigned int sid = SIC_SYSIRQ(d->irq);
306 
307         bfin_sec_disable_sci(sid);
308         bfin_sec_disable_ssi(sid);
309 
310         hard_local_irq_restore(flags);
311 }
312 
313 static void bfin_sec_raise_irq(unsigned int sid)
314 {
315         unsigned long flags = hard_local_irq_save();
316 
317         bfin_write32(SEC_RAISE, sid);
318 
319         hard_local_irq_restore(flags);
320 }
321 
322 static void init_software_driven_irq(void)
323 {
324         bfin_sec_set_ssi_coreid(34, 0);
325         bfin_sec_set_ssi_coreid(35, 1);
326         bfin_sec_set_ssi_coreid(36, 0);
327         bfin_sec_set_ssi_coreid(37, 1);
328 }
329 
330 void bfin_sec_resume(void)
331 {
332         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
333         udelay(100);
334         bfin_write_SEC_GCTL(SEC_GCTL_EN);
335         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
336 }
337 
338 void handle_sec_sfi_fault(uint32_t gstat)
339 {
340 
341 }
342 
343 void handle_sec_sci_fault(uint32_t gstat)
344 {
345         uint32_t core_id;
346         uint32_t cstat;
347 
348         core_id = gstat & SEC_GSTAT_SCI;
349         cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
350         if (cstat & SEC_CSTAT_ERR) {
351                 switch (cstat & SEC_CSTAT_ERRC) {
352                 case SEC_CSTAT_ACKERR:
353                         printk(KERN_DEBUG "sec ack err\n");
354                         break;
355                 default:
356                         printk(KERN_DEBUG "sec sci unknow err\n");
357                 }
358         }
359 
360 }
361 
362 void handle_sec_ssi_fault(uint32_t gstat)
363 {
364         uint32_t sid;
365         uint32_t sstat;
366 
367         sid = gstat & SEC_GSTAT_SID;
368         sstat = bfin_read_SEC_SSTAT(sid);
369 
370 }
371 
372 void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
373 {
374         uint32_t sec_gstat;
375 
376         raw_spin_lock(&desc->lock);
377 
378         sec_gstat = bfin_read32(SEC_GSTAT);
379         if (sec_gstat & SEC_GSTAT_ERR) {
380 
381                 switch (sec_gstat & SEC_GSTAT_ERRC) {
382                 case 0:
383                         handle_sec_sfi_fault(sec_gstat);
384                         break;
385                 case SEC_GSTAT_SCIERR:
386                         handle_sec_sci_fault(sec_gstat);
387                         break;
388                 case SEC_GSTAT_SSIERR:
389                         handle_sec_ssi_fault(sec_gstat);
390                         break;
391                 }
392 
393 
394         }
395 
396         raw_spin_unlock(&desc->lock);
397 }
398 
399 static int sec_suspend(void)
400 {
401         return 0;
402 }
403 
404 static void sec_resume(void)
405 {
406         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
407         udelay(100);
408         bfin_write_SEC_GCTL(SEC_GCTL_EN);
409         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
410 }
411 
412 static struct syscore_ops sec_pm_syscore_ops = {
413         .suspend = sec_suspend,
414         .resume = sec_resume,
415 };
416 
417 #endif
418 
419 #ifdef CONFIG_SMP
420 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
421 {
422         bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
423 }
424 
425 static int bfin_internal_set_affinity(struct irq_data *d,
426                                       const struct cpumask *mask, bool force)
427 {
428         bfin_internal_mask_irq(d->irq);
429         bfin_internal_unmask_irq_affinity(d->irq, mask);
430 
431         return 0;
432 }
433 #else
434 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
435 {
436         bfin_internal_unmask_irq(d->irq);
437 }
438 #endif
439 
440 #if defined(CONFIG_PM) && !defined(CONFIG_BF60x)
441 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
442 {
443         u32 bank, bit, wakeup = 0;
444         unsigned long flags;
445         bank = SIC_SYSIRQ(irq) / 32;
446         bit = SIC_SYSIRQ(irq) % 32;
447 
448         switch (irq) {
449 #ifdef IRQ_RTC
450         case IRQ_RTC:
451         wakeup |= WAKE;
452         break;
453 #endif
454 #ifdef IRQ_CAN0_RX
455         case IRQ_CAN0_RX:
456         wakeup |= CANWE;
457         break;
458 #endif
459 #ifdef IRQ_CAN1_RX
460         case IRQ_CAN1_RX:
461         wakeup |= CANWE;
462         break;
463 #endif
464 #ifdef IRQ_USB_INT0
465         case IRQ_USB_INT0:
466         wakeup |= USBWE;
467         break;
468 #endif
469 #ifdef CONFIG_BF54x
470         case IRQ_CNT:
471         wakeup |= ROTWE;
472         break;
473 #endif
474         default:
475         break;
476         }
477 
478         flags = hard_local_irq_save();
479 
480         if (state) {
481                 bfin_sic_iwr[bank] |= (1 << bit);
482                 vr_wakeup  |= wakeup;
483 
484         } else {
485                 bfin_sic_iwr[bank] &= ~(1 << bit);
486                 vr_wakeup  &= ~wakeup;
487         }
488 
489         hard_local_irq_restore(flags);
490 
491         return 0;
492 }
493 
494 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
495 {
496         return bfin_internal_set_wake(d->irq, state);
497 }
498 #else
499 # define bfin_internal_set_wake(irq, state)
500 # define bfin_internal_set_wake_chip NULL
501 #endif
502 
503 static struct irq_chip bfin_core_irqchip = {
504         .name = "CORE",
505         .irq_mask = bfin_core_mask_irq,
506         .irq_unmask = bfin_core_unmask_irq,
507 };
508 
509 static struct irq_chip bfin_internal_irqchip = {
510         .name = "INTN",
511         .irq_mask = bfin_internal_mask_irq_chip,
512         .irq_unmask = bfin_internal_unmask_irq_chip,
513         .irq_disable = bfin_internal_mask_irq_chip,
514         .irq_enable = bfin_internal_unmask_irq_chip,
515 #ifdef CONFIG_SMP
516         .irq_set_affinity = bfin_internal_set_affinity,
517 #endif
518         .irq_set_wake = bfin_internal_set_wake_chip,
519 };
520 
521 #ifdef CONFIG_BF60x
522 static struct irq_chip bfin_sec_irqchip = {
523         .name = "SEC",
524         .irq_mask_ack = bfin_sec_mask_ack_irq,
525         .irq_mask = bfin_sec_mask_ack_irq,
526         .irq_unmask = bfin_sec_unmask_irq,
527         .irq_eoi = bfin_sec_unmask_irq,
528         .irq_disable = bfin_sec_disable,
529         .irq_enable = bfin_sec_enable,
530 };
531 #endif
532 
533 void bfin_handle_irq(unsigned irq)
534 {
535 #ifdef CONFIG_IPIPE
536         struct pt_regs regs;    /* Contents not used. */
537         ipipe_trace_irq_entry(irq);
538         __ipipe_handle_irq(irq, &regs);
539         ipipe_trace_irq_exit(irq);
540 #else /* !CONFIG_IPIPE */
541         generic_handle_irq(irq);
542 #endif  /* !CONFIG_IPIPE */
543 }
544 
545 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
546 static int mac_stat_int_mask;
547 
548 static void bfin_mac_status_ack_irq(unsigned int irq)
549 {
550         switch (irq) {
551         case IRQ_MAC_MMCINT:
552                 bfin_write_EMAC_MMC_TIRQS(
553                         bfin_read_EMAC_MMC_TIRQE() &
554                         bfin_read_EMAC_MMC_TIRQS());
555                 bfin_write_EMAC_MMC_RIRQS(
556                         bfin_read_EMAC_MMC_RIRQE() &
557                         bfin_read_EMAC_MMC_RIRQS());
558                 break;
559         case IRQ_MAC_RXFSINT:
560                 bfin_write_EMAC_RX_STKY(
561                         bfin_read_EMAC_RX_IRQE() &
562                         bfin_read_EMAC_RX_STKY());
563                 break;
564         case IRQ_MAC_TXFSINT:
565                 bfin_write_EMAC_TX_STKY(
566                         bfin_read_EMAC_TX_IRQE() &
567                         bfin_read_EMAC_TX_STKY());
568                 break;
569         case IRQ_MAC_WAKEDET:
570                  bfin_write_EMAC_WKUP_CTL(
571                         bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
572                 break;
573         default:
574                 /* These bits are W1C */
575                 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
576                 break;
577         }
578 }
579 
580 static void bfin_mac_status_mask_irq(struct irq_data *d)
581 {
582         unsigned int irq = d->irq;
583 
584         mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
585 #ifdef BF537_FAMILY
586         switch (irq) {
587         case IRQ_MAC_PHYINT:
588                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
589                 break;
590         default:
591                 break;
592         }
593 #else
594         if (!mac_stat_int_mask)
595                 bfin_internal_mask_irq(IRQ_MAC_ERROR);
596 #endif
597         bfin_mac_status_ack_irq(irq);
598 }
599 
600 static void bfin_mac_status_unmask_irq(struct irq_data *d)
601 {
602         unsigned int irq = d->irq;
603 
604 #ifdef BF537_FAMILY
605         switch (irq) {
606         case IRQ_MAC_PHYINT:
607                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
608                 break;
609         default:
610                 break;
611         }
612 #else
613         if (!mac_stat_int_mask)
614                 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
615 #endif
616         mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
617 }
618 
619 #ifdef CONFIG_PM
620 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
621 {
622 #ifdef BF537_FAMILY
623         return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
624 #else
625         return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
626 #endif
627 }
628 #else
629 # define bfin_mac_status_set_wake NULL
630 #endif
631 
632 static struct irq_chip bfin_mac_status_irqchip = {
633         .name = "MACST",
634         .irq_mask = bfin_mac_status_mask_irq,
635         .irq_unmask = bfin_mac_status_unmask_irq,
636         .irq_set_wake = bfin_mac_status_set_wake,
637 };
638 
639 void bfin_demux_mac_status_irq(unsigned int int_err_irq,
640                                struct irq_desc *inta_desc)
641 {
642         int i, irq = 0;
643         u32 status = bfin_read_EMAC_SYSTAT();
644 
645         for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
646                 if (status & (1L << i)) {
647                         irq = IRQ_MAC_PHYINT + i;
648                         break;
649                 }
650 
651         if (irq) {
652                 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
653                         bfin_handle_irq(irq);
654                 } else {
655                         bfin_mac_status_ack_irq(irq);
656                         pr_debug("IRQ %d:"
657                                         " MASKED MAC ERROR INTERRUPT ASSERTED\n",
658                                         irq);
659                 }
660         } else
661                 printk(KERN_ERR
662                                 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
663                                 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
664                                 "(EMAC_SYSTAT=0x%X)\n",
665                                 __func__, __FILE__, __LINE__, status);
666 }
667 #endif
668 
669 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
670 {
671 #ifdef CONFIG_IPIPE
672         handle = handle_level_irq;
673 #endif
674         __irq_set_handler_locked(irq, handle);
675 }
676 
677 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
678 extern void bfin_gpio_irq_prepare(unsigned gpio);
679 
680 #if !BFIN_GPIO_PINT
681 
682 static void bfin_gpio_ack_irq(struct irq_data *d)
683 {
684         /* AFAIK ack_irq in case mask_ack is provided
685          * get's only called for edge sense irqs
686          */
687         set_gpio_data(irq_to_gpio(d->irq), 0);
688 }
689 
690 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
691 {
692         unsigned int irq = d->irq;
693         u32 gpionr = irq_to_gpio(irq);
694 
695         if (!irqd_is_level_type(d))
696                 set_gpio_data(gpionr, 0);
697 
698         set_gpio_maska(gpionr, 0);
699 }
700 
701 static void bfin_gpio_mask_irq(struct irq_data *d)
702 {
703         set_gpio_maska(irq_to_gpio(d->irq), 0);
704 }
705 
706 static void bfin_gpio_unmask_irq(struct irq_data *d)
707 {
708         set_gpio_maska(irq_to_gpio(d->irq), 1);
709 }
710 
711 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
712 {
713         u32 gpionr = irq_to_gpio(d->irq);
714 
715         if (__test_and_set_bit(gpionr, gpio_enabled))
716                 bfin_gpio_irq_prepare(gpionr);
717 
718         bfin_gpio_unmask_irq(d);
719 
720         return 0;
721 }
722 
723 static void bfin_gpio_irq_shutdown(struct irq_data *d)
724 {
725         u32 gpionr = irq_to_gpio(d->irq);
726 
727         bfin_gpio_mask_irq(d);
728         __clear_bit(gpionr, gpio_enabled);
729         bfin_gpio_irq_free(gpionr);
730 }
731 
732 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
733 {
734         unsigned int irq = d->irq;
735         int ret;
736         char buf[16];
737         u32 gpionr = irq_to_gpio(irq);
738 
739         if (type == IRQ_TYPE_PROBE) {
740                 /* only probe unenabled GPIO interrupt lines */
741                 if (test_bit(gpionr, gpio_enabled))
742                         return 0;
743                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
744         }
745 
746         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
747                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
748 
749                 snprintf(buf, 16, "gpio-irq%d", irq);
750                 ret = bfin_gpio_irq_request(gpionr, buf);
751                 if (ret)
752                         return ret;
753 
754                 if (__test_and_set_bit(gpionr, gpio_enabled))
755                         bfin_gpio_irq_prepare(gpionr);
756 
757         } else {
758                 __clear_bit(gpionr, gpio_enabled);
759                 return 0;
760         }
761 
762         set_gpio_inen(gpionr, 0);
763         set_gpio_dir(gpionr, 0);
764 
765         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
766             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
767                 set_gpio_both(gpionr, 1);
768         else
769                 set_gpio_both(gpionr, 0);
770 
771         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
772                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
773         else
774                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
775 
776         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
777                 set_gpio_edge(gpionr, 1);
778                 set_gpio_inen(gpionr, 1);
779                 set_gpio_data(gpionr, 0);
780 
781         } else {
782                 set_gpio_edge(gpionr, 0);
783                 set_gpio_inen(gpionr, 1);
784         }
785 
786         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
787                 bfin_set_irq_handler(irq, handle_edge_irq);
788         else
789                 bfin_set_irq_handler(irq, handle_level_irq);
790 
791         return 0;
792 }
793 
794 #ifdef CONFIG_PM
795 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
796 {
797         return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
798 }
799 #else
800 # define bfin_gpio_set_wake NULL
801 #endif
802 
803 static void bfin_demux_gpio_block(unsigned int irq)
804 {
805         unsigned int gpio, mask;
806 
807         gpio = irq_to_gpio(irq);
808         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
809 
810         while (mask) {
811                 if (mask & 1)
812                         bfin_handle_irq(irq);
813                 irq++;
814                 mask >>= 1;
815         }
816 }
817 
818 void bfin_demux_gpio_irq(unsigned int inta_irq,
819                         struct irq_desc *desc)
820 {
821         unsigned int irq;
822 
823         switch (inta_irq) {
824 #if defined(BF537_FAMILY)
825         case IRQ_PF_INTA_PG_INTA:
826                 bfin_demux_gpio_block(IRQ_PF0);
827                 irq = IRQ_PG0;
828                 break;
829         case IRQ_PH_INTA_MAC_RX:
830                 irq = IRQ_PH0;
831                 break;
832 #elif defined(BF533_FAMILY)
833         case IRQ_PROG_INTA:
834                 irq = IRQ_PF0;
835                 break;
836 #elif defined(BF538_FAMILY)
837         case IRQ_PORTF_INTA:
838                 irq = IRQ_PF0;
839                 break;
840 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
841         case IRQ_PORTF_INTA:
842                 irq = IRQ_PF0;
843                 break;
844         case IRQ_PORTG_INTA:
845                 irq = IRQ_PG0;
846                 break;
847         case IRQ_PORTH_INTA:
848                 irq = IRQ_PH0;
849                 break;
850 #elif defined(CONFIG_BF561)
851         case IRQ_PROG0_INTA:
852                 irq = IRQ_PF0;
853                 break;
854         case IRQ_PROG1_INTA:
855                 irq = IRQ_PF16;
856                 break;
857         case IRQ_PROG2_INTA:
858                 irq = IRQ_PF32;
859                 break;
860 #endif
861         default:
862                 BUG();
863                 return;
864         }
865 
866         bfin_demux_gpio_block(irq);
867 }
868 
869 #else
870 
871 # ifndef CONFIG_BF60x
872 #define NR_PINT_SYS_IRQS        4
873 #define NR_PINTS                160
874 # else
875 #define NR_PINT_SYS_IRQS        6
876 #define NR_PINTS                112
877 #endif
878 
879 #define NR_PINT_BITS            32
880 #define IRQ_NOT_AVAIL           0xFF
881 
882 #define PINT_2_BANK(x)          ((x) >> 5)
883 #define PINT_2_BIT(x)           ((x) & 0x1F)
884 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
885 
886 static unsigned char irq2pint_lut[NR_PINTS];
887 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
888 
889 static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
890         (struct bfin_pint_regs *)PINT0_MASK_SET,
891         (struct bfin_pint_regs *)PINT1_MASK_SET,
892         (struct bfin_pint_regs *)PINT2_MASK_SET,
893         (struct bfin_pint_regs *)PINT3_MASK_SET,
894 #ifdef CONFIG_BF60x
895         (struct bfin_pint_regs *)PINT4_MASK_SET,
896         (struct bfin_pint_regs *)PINT5_MASK_SET,
897 #endif
898 };
899 
900 #ifndef CONFIG_BF60x
901 inline unsigned int get_irq_base(u32 bank, u8 bmap)
902 {
903         unsigned int irq_base;
904 
905         if (bank < 2) {         /*PA-PB */
906                 irq_base = IRQ_PA0 + bmap * 16;
907         } else {                /*PC-PJ */
908                 irq_base = IRQ_PC0 + bmap * 16;
909         }
910 
911         return irq_base;
912 }
913 #else
914 inline unsigned int get_irq_base(u32 bank, u8 bmap)
915 {
916         unsigned int irq_base;
917 
918         irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
919 
920         return irq_base;
921 }
922 #endif
923 
924         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
925 void init_pint_lut(void)
926 {
927         u16 bank, bit, irq_base, bit_pos;
928         u32 pint_assign;
929         u8 bmap;
930 
931         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
932 
933         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
934 
935                 pint_assign = pint[bank]->assign;
936 
937                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
938 
939                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
940 
941                         irq_base = get_irq_base(bank, bmap);
942 
943                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
944                         bit_pos = bit + bank * NR_PINT_BITS;
945 
946                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
947                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
948                 }
949         }
950 }
951 
952 static void bfin_gpio_ack_irq(struct irq_data *d)
953 {
954         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
955         u32 pintbit = PINT_BIT(pint_val);
956         u32 bank = PINT_2_BANK(pint_val);
957 
958         if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
959                 if (pint[bank]->invert_set & pintbit)
960                         pint[bank]->invert_clear = pintbit;
961                 else
962                         pint[bank]->invert_set = pintbit;
963         }
964         pint[bank]->request = pintbit;
965 
966 }
967 
968 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
969 {
970         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
971         u32 pintbit = PINT_BIT(pint_val);
972         u32 bank = PINT_2_BANK(pint_val);
973 
974         if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
975                 if (pint[bank]->invert_set & pintbit)
976                         pint[bank]->invert_clear = pintbit;
977                 else
978                         pint[bank]->invert_set = pintbit;
979         }
980 
981         pint[bank]->request = pintbit;
982         pint[bank]->mask_clear = pintbit;
983 }
984 
985 static void bfin_gpio_mask_irq(struct irq_data *d)
986 {
987         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
988 
989         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
990 }
991 
992 static void bfin_gpio_unmask_irq(struct irq_data *d)
993 {
994         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
995         u32 pintbit = PINT_BIT(pint_val);
996         u32 bank = PINT_2_BANK(pint_val);
997 
998         pint[bank]->mask_set = pintbit;
999 }
1000 
1001 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
1002 {
1003         unsigned int irq = d->irq;
1004         u32 gpionr = irq_to_gpio(irq);
1005         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1006 
1007         if (pint_val == IRQ_NOT_AVAIL) {
1008                 printk(KERN_ERR
1009                 "GPIO IRQ %d :Not in PINT Assign table "
1010                 "Reconfigure Interrupt to Port Assignemt\n", irq);
1011                 return -ENODEV;
1012         }
1013 
1014         if (__test_and_set_bit(gpionr, gpio_enabled))
1015                 bfin_gpio_irq_prepare(gpionr);
1016 
1017         bfin_gpio_unmask_irq(d);
1018 
1019         return 0;
1020 }
1021 
1022 static void bfin_gpio_irq_shutdown(struct irq_data *d)
1023 {
1024         u32 gpionr = irq_to_gpio(d->irq);
1025 
1026         bfin_gpio_mask_irq(d);
1027         __clear_bit(gpionr, gpio_enabled);
1028         bfin_gpio_irq_free(gpionr);
1029 }
1030 
1031 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
1032 {
1033         unsigned int irq = d->irq;
1034         int ret;
1035         char buf[16];
1036         u32 gpionr = irq_to_gpio(irq);
1037         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1038         u32 pintbit = PINT_BIT(pint_val);
1039         u32 bank = PINT_2_BANK(pint_val);
1040 
1041         if (pint_val == IRQ_NOT_AVAIL)
1042                 return -ENODEV;
1043 
1044         if (type == IRQ_TYPE_PROBE) {
1045                 /* only probe unenabled GPIO interrupt lines */
1046                 if (test_bit(gpionr, gpio_enabled))
1047                         return 0;
1048                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1049         }
1050 
1051         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
1052                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1053 
1054                 snprintf(buf, 16, "gpio-irq%d", irq);
1055                 ret = bfin_gpio_irq_request(gpionr, buf);
1056                 if (ret)
1057                         return ret;
1058 
1059                 if (__test_and_set_bit(gpionr, gpio_enabled))
1060                         bfin_gpio_irq_prepare(gpionr);
1061 
1062         } else {
1063                 __clear_bit(gpionr, gpio_enabled);
1064                 return 0;
1065         }
1066 
1067         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
1068                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
1069         else
1070                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
1071 
1072         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
1073             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1074                 if (gpio_get_value(gpionr))
1075                         pint[bank]->invert_set = pintbit;
1076                 else
1077                         pint[bank]->invert_clear = pintbit;
1078         }
1079 
1080         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1081                 pint[bank]->edge_set = pintbit;
1082                 bfin_set_irq_handler(irq, handle_edge_irq);
1083         } else {
1084                 pint[bank]->edge_clear = pintbit;
1085                 bfin_set_irq_handler(irq, handle_level_irq);
1086         }
1087 
1088         return 0;
1089 }
1090 
1091 #ifdef CONFIG_PM
1092 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
1093 {
1094         u32 pint_irq;
1095         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1096         u32 bank = PINT_2_BANK(pint_val);
1097 
1098         switch (bank) {
1099         case 0:
1100                 pint_irq = IRQ_PINT0;
1101                 break;
1102         case 2:
1103                 pint_irq = IRQ_PINT2;
1104                 break;
1105         case 3:
1106                 pint_irq = IRQ_PINT3;
1107                 break;
1108         case 1:
1109                 pint_irq = IRQ_PINT1;
1110                 break;
1111 #ifdef CONFIG_BF60x
1112         case 4:
1113                 pint_irq = IRQ_PINT4;
1114                 break;
1115         case 5:
1116                 pint_irq = IRQ_PINT5;
1117                 break;
1118 #endif
1119         default:
1120                 return -EINVAL;
1121         }
1122 
1123         bfin_internal_set_wake(pint_irq, state);
1124 
1125         return 0;
1126 }
1127 #else
1128 # define bfin_gpio_set_wake NULL
1129 #endif
1130 
1131 void bfin_demux_gpio_irq(unsigned int inta_irq,
1132                         struct irq_desc *desc)
1133 {
1134         u32 bank, pint_val;
1135         u32 request, irq;
1136         u32 level_mask;
1137         int umask = 0;
1138         struct irq_chip *chip = irq_desc_get_chip(desc);
1139 
1140         if (chip->irq_mask_ack) {
1141                 chip->irq_mask_ack(&desc->irq_data);
1142         } else {
1143                 chip->irq_mask(&desc->irq_data);
1144                 if (chip->irq_ack)
1145                         chip->irq_ack(&desc->irq_data);
1146         }
1147 
1148         switch (inta_irq) {
1149         case IRQ_PINT0:
1150                 bank = 0;
1151                 break;
1152         case IRQ_PINT2:
1153                 bank = 2;
1154                 break;
1155         case IRQ_PINT3:
1156                 bank = 3;
1157                 break;
1158         case IRQ_PINT1:
1159                 bank = 1;
1160                 break;
1161 #ifdef CONFIG_BF60x
1162         case IRQ_PINT4:
1163                 bank = 4;
1164                 break;
1165         case IRQ_PINT5:
1166                 bank = 5;
1167                 break;
1168 #endif
1169         default:
1170                 return;
1171         }
1172 
1173         pint_val = bank * NR_PINT_BITS;
1174 
1175         request = pint[bank]->request;
1176 
1177         level_mask = pint[bank]->edge_set & request;
1178 
1179         while (request) {
1180                 if (request & 1) {
1181                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
1182                         if (level_mask & PINT_BIT(pint_val)) {
1183                                 umask = 1;
1184                                 chip->irq_unmask(&desc->irq_data);
1185                         }
1186                         bfin_handle_irq(irq);
1187                 }
1188                 pint_val++;
1189                 request >>= 1;
1190         }
1191 
1192         if (!umask)
1193                 chip->irq_unmask(&desc->irq_data);
1194 }
1195 #endif
1196 
1197 static struct irq_chip bfin_gpio_irqchip = {
1198         .name = "GPIO",
1199         .irq_ack = bfin_gpio_ack_irq,
1200         .irq_mask = bfin_gpio_mask_irq,
1201         .irq_mask_ack = bfin_gpio_mask_ack_irq,
1202         .irq_unmask = bfin_gpio_unmask_irq,
1203         .irq_disable = bfin_gpio_mask_irq,
1204         .irq_enable = bfin_gpio_unmask_irq,
1205         .irq_set_type = bfin_gpio_irq_type,
1206         .irq_startup = bfin_gpio_irq_startup,
1207         .irq_shutdown = bfin_gpio_irq_shutdown,
1208         .irq_set_wake = bfin_gpio_set_wake,
1209 };
1210 
1211 void __cpuinit init_exception_vectors(void)
1212 {
1213         /* cannot program in software:
1214          * evt0 - emulation (jtag)
1215          * evt1 - reset
1216          */
1217         bfin_write_EVT2(evt_nmi);
1218         bfin_write_EVT3(trap);
1219         bfin_write_EVT5(evt_ivhw);
1220         bfin_write_EVT6(evt_timer);
1221         bfin_write_EVT7(evt_evt7);
1222         bfin_write_EVT8(evt_evt8);
1223         bfin_write_EVT9(evt_evt9);
1224         bfin_write_EVT10(evt_evt10);
1225         bfin_write_EVT11(evt_evt11);
1226         bfin_write_EVT12(evt_evt12);
1227         bfin_write_EVT13(evt_evt13);
1228         bfin_write_EVT14(evt_evt14);
1229         bfin_write_EVT15(evt_system_call);
1230         CSYNC();
1231 }
1232 
1233 /*
1234  * This function should be called during kernel startup to initialize
1235  * the BFin IRQ handling routines.
1236  */
1237 
1238 int __init init_arch_irq(void)
1239 {
1240         int irq;
1241         unsigned long ilat = 0;
1242 
1243 #ifndef CONFIG_BF60x
1244         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
1245 #ifdef SIC_IMASK0
1246         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1247         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1248 # ifdef SIC_IMASK2
1249         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1250 # endif
1251 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1252         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1253         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1254 # endif
1255 #else
1256         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1257 #endif
1258 #else /* CONFIG_BF60x */
1259         bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1260 #endif
1261 
1262         local_irq_disable();
1263 
1264 #if BFIN_GPIO_PINT
1265 # ifdef CONFIG_PINTx_REASSIGN
1266         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1267         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1268         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1269         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1270 # ifdef CONFIG_BF60x
1271         pint[4]->assign = CONFIG_PINT4_ASSIGN;
1272         pint[5]->assign = CONFIG_PINT5_ASSIGN;
1273 # endif
1274 # endif
1275         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1276         init_pint_lut();
1277 #endif
1278 
1279         for (irq = 0; irq <= SYS_IRQS; irq++) {
1280                 if (irq <= IRQ_CORETMR)
1281                         irq_set_chip(irq, &bfin_core_irqchip);
1282                 else
1283                         irq_set_chip(irq, &bfin_internal_irqchip);
1284 
1285                 switch (irq) {
1286 #ifndef CONFIG_BF60x
1287 #if BFIN_GPIO_PINT
1288                 case IRQ_PINT0:
1289                 case IRQ_PINT1:
1290                 case IRQ_PINT2:
1291                 case IRQ_PINT3:
1292 #elif defined(BF537_FAMILY)
1293                 case IRQ_PH_INTA_MAC_RX:
1294                 case IRQ_PF_INTA_PG_INTA:
1295 #elif defined(BF533_FAMILY)
1296                 case IRQ_PROG_INTA:
1297 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1298                 case IRQ_PORTF_INTA:
1299                 case IRQ_PORTG_INTA:
1300                 case IRQ_PORTH_INTA:
1301 #elif defined(CONFIG_BF561)
1302                 case IRQ_PROG0_INTA:
1303                 case IRQ_PROG1_INTA:
1304                 case IRQ_PROG2_INTA:
1305 #elif defined(BF538_FAMILY)
1306                 case IRQ_PORTF_INTA:
1307 #endif
1308                         irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1309                         break;
1310 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1311                 case IRQ_MAC_ERROR:
1312                         irq_set_chained_handler(irq,
1313                                                 bfin_demux_mac_status_irq);
1314                         break;
1315 #endif
1316 #if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1317                 case IRQ_SUPPLE_0:
1318                 case IRQ_SUPPLE_1:
1319                         irq_set_handler(irq, handle_percpu_irq);
1320                         break;
1321 #endif
1322 #endif
1323 
1324 #ifdef CONFIG_TICKSOURCE_CORETMR
1325                 case IRQ_CORETMR:
1326 # ifdef CONFIG_SMP
1327                         irq_set_handler(irq, handle_percpu_irq);
1328 # else
1329                         irq_set_handler(irq, handle_simple_irq);
1330 # endif
1331                         break;
1332 #endif
1333 
1334 #ifdef CONFIG_TICKSOURCE_GPTMR0
1335                 case IRQ_TIMER0:
1336                         irq_set_handler(irq, handle_simple_irq);
1337                         break;
1338 #endif
1339 
1340                 default:
1341 #ifdef CONFIG_IPIPE
1342                         irq_set_handler(irq, handle_level_irq);
1343 #else
1344                         irq_set_handler(irq, handle_simple_irq);
1345 #endif
1346                         break;
1347                 }
1348         }
1349 
1350         init_mach_irq();
1351 
1352 #ifndef CONFIG_BF60x
1353 #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) && !defined(CONFIG_BF60x)
1354         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1355                 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1356                                          handle_level_irq);
1357 #endif
1358         /* if configured as edge, then will be changed to do_edge_IRQ */
1359         for (irq = GPIO_IRQ_BASE;
1360                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1361                 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1362                                          handle_level_irq);
1363 #else
1364         for (irq = BFIN_IRQ(0); irq <= SYS_IRQS; irq++) {
1365                 if (irq < CORE_IRQS) {
1366                         irq_set_chip(irq, &bfin_sec_irqchip);
1367                         __irq_set_handler(irq, handle_sec_fault, 0, NULL);
1368                 } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
1369                         irq_set_chip(irq, &bfin_sec_irqchip);
1370                         irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1371                 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
1372                         irq_set_chip(irq, &bfin_sec_irqchip);
1373                         irq_set_handler(irq, handle_percpu_irq);
1374                 } else {
1375                         irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1376                                         handle_fasteoi_irq);
1377                         __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1378                 }
1379         }
1380         for (irq = GPIO_IRQ_BASE;
1381                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1382                 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1383                                         handle_level_irq);
1384 #endif
1385         bfin_write_IMASK(0);
1386         CSYNC();
1387         ilat = bfin_read_ILAT();
1388         CSYNC();
1389         bfin_write_ILAT(ilat);
1390         CSYNC();
1391 
1392         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1393         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1394          * local_irq_enable()
1395          */
1396 #ifndef CONFIG_BF60x
1397         program_IAR();
1398         /* Therefore it's better to setup IARs before interrupts enabled */
1399         search_IAR();
1400 
1401         /* Enable interrupts IVG7-15 */
1402         bfin_irq_flags |= IMASK_IVG15 |
1403                 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1404                 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1405 
1406         bfin_sti(bfin_irq_flags);
1407 
1408         /* This implicitly covers ANOMALY_05000171
1409          * Boot-ROM code modifies SICA_IWRx wakeup registers
1410          */
1411 #ifdef SIC_IWR0
1412         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1413 # ifdef SIC_IWR1
1414         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1415          * will screw up the bootrom as it relies on MDMA0/1 waking it
1416          * up from IDLE instructions.  See this report for more info:
1417          * http://blackfin.uclinux.org/gf/tracker/4323
1418          */
1419         if (ANOMALY_05000435)
1420                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1421         else
1422                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1423 # endif
1424 # ifdef SIC_IWR2
1425         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1426 # endif
1427 #else
1428         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1429 #endif
1430 #else  /* CONFIG_BF60x */
1431         /* Enable interrupts IVG7-15 */
1432         bfin_irq_flags |= IMASK_IVG15 |
1433             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1434             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1435 
1436 
1437         bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
1438         bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
1439         bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
1440         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1441         udelay(100);
1442         bfin_write_SEC_GCTL(SEC_GCTL_EN);
1443         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1444         init_software_driven_irq();
1445         register_syscore_ops(&sec_pm_syscore_ops);
1446 #endif
1447         return 0;
1448 }
1449 
1450 #ifdef CONFIG_DO_IRQ_L1
1451 __attribute__((l1_text))
1452 #endif
1453 static int vec_to_irq(int vec)
1454 {
1455 #ifndef CONFIG_BF60x
1456         struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1457         struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1458         unsigned long sic_status[3];
1459 #endif
1460         if (likely(vec == EVT_IVTMR_P))
1461                 return IRQ_CORETMR;
1462 #ifndef CONFIG_BF60x
1463 #ifdef SIC_ISR
1464         sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1465 #else
1466         if (smp_processor_id()) {
1467 # ifdef SICB_ISR0
1468                 /* This will be optimized out in UP mode. */
1469                 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1470                 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1471 # endif
1472         } else {
1473                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1474                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1475         }
1476 #endif
1477 #ifdef SIC_ISR2
1478         sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1479 #endif
1480 
1481         for (;; ivg++) {
1482                 if (ivg >= ivg_stop)
1483                         return -1;
1484 #ifdef SIC_ISR
1485                 if (sic_status[0] & ivg->isrflag)
1486 #else
1487                 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1488 #endif
1489                         return ivg->irqno;
1490         }
1491 #else
1492         /* for bf60x read */
1493         return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1494 #endif  /* end of CONFIG_BF60x */
1495 }
1496 
1497 #ifdef CONFIG_DO_IRQ_L1
1498 __attribute__((l1_text))
1499 #endif
1500 void do_irq(int vec, struct pt_regs *fp)
1501 {
1502         int irq = vec_to_irq(vec);
1503         if (irq == -1)
1504                 return;
1505         asm_do_IRQ(irq, fp);
1506 }
1507 
1508 #ifdef CONFIG_IPIPE
1509 
1510 int __ipipe_get_irq_priority(unsigned irq)
1511 {
1512         int ient, prio;
1513 
1514         if (irq <= IRQ_CORETMR)
1515                 return irq;
1516 
1517         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1518                 struct ivgx *ivg = ivg_table + ient;
1519                 if (ivg->irqno == irq) {
1520                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1521                                 if (ivg7_13[prio].ifirst <= ivg &&
1522                                     ivg7_13[prio].istop > ivg)
1523                                         return IVG7 + prio;
1524                         }
1525                 }
1526         }
1527 
1528         return IVG15;
1529 }
1530 
1531 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1532 #ifdef CONFIG_DO_IRQ_L1
1533 __attribute__((l1_text))
1534 #endif
1535 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1536 {
1537         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1538         struct ipipe_domain *this_domain = __ipipe_current_domain;
1539         struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1540         struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1541         int irq, s = 0;
1542 
1543         irq = vec_to_irq(vec);
1544         if (irq == -1)
1545                 return 0;
1546 
1547         if (irq == IRQ_SYSTMR) {
1548 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1549                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1550 #endif
1551                 /* This is basically what we need from the register frame. */
1552                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1553                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1554                 if (this_domain != ipipe_root_domain)
1555                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1556                 else
1557                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1558         }
1559 
1560         /*
1561          * We don't want Linux interrupt handlers to run at the
1562          * current core priority level (i.e. < EVT15), since this
1563          * might delay other interrupts handled by a high priority
1564          * domain. Here is what we do instead:
1565          *
1566          * - we raise the SYNCDEFER bit to prevent
1567          * __ipipe_handle_irq() to sync the pipeline for the root
1568          * stage for the incoming interrupt. Upon return, that IRQ is
1569          * pending in the interrupt log.
1570          *
1571          * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1572          * that _schedule_and_signal_from_int will eventually sync the
1573          * pipeline from EVT15.
1574          */
1575         if (this_domain == ipipe_root_domain) {
1576                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1577                 barrier();
1578         }
1579 
1580         ipipe_trace_irq_entry(irq);
1581         __ipipe_handle_irq(irq, regs);
1582         ipipe_trace_irq_exit(irq);
1583 
1584         if (user_mode(regs) &&
1585             !ipipe_test_foreign_stack() &&
1586             (current->ipipe_flags & PF_EVTRET) != 0) {
1587                 /*
1588                  * Testing for user_regs() does NOT fully eliminate
1589                  * foreign stack contexts, because of the forged
1590                  * interrupt returns we do through
1591                  * __ipipe_call_irqtail. In that case, we might have
1592                  * preempted a foreign stack context in a high
1593                  * priority domain, with a single interrupt level now
1594                  * pending after the irqtail unwinding is done. In
1595                  * which case user_mode() is now true, and the event
1596                  * gets dispatched spuriously.
1597                  */
1598                 current->ipipe_flags &= ~PF_EVTRET;
1599                 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1600         }
1601 
1602         if (this_domain == ipipe_root_domain) {
1603                 set_thread_flag(TIF_IRQ_SYNC);
1604                 if (!s) {
1605                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1606                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1607                 }
1608         }
1609 
1610         return 0;
1611 }
1612 
1613 #endif /* CONFIG_IPIPE */
1614 

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