~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/arch/c6x/platforms/dscr.c

Version: ~ [ linux-5.4-rc3 ] ~ [ linux-5.3.6 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.79 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.149 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.196 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.196 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.75 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  *  Device State Control Registers driver
  3  *
  4  *  Copyright (C) 2011 Texas Instruments Incorporated
  5  *  Author: Mark Salter <msalter@redhat.com>
  6  *
  7  *  This program is free software; you can redistribute it and/or modify
  8  *  it under the terms of the GNU General Public License version 2 as
  9  *  published by the Free Software Foundation.
 10  */
 11 
 12 /*
 13  * The Device State Control Registers (DSCR) provide SoC level control over
 14  * a number of peripherals. Details vary considerably among the various SoC
 15  * parts. In general, the DSCR block will provide one or more configuration
 16  * registers often protected by a lock register. One or more key values must
 17  * be written to a lock register in order to unlock the configuration register.
 18  * The configuration register may be used to enable (and disable in some
 19  * cases) SoC pin drivers, peripheral clock sources (internal or pin), etc.
 20  * In some cases, a configuration register is write once or the individual
 21  * bits are write once. That is, you may be able to enable a device, but
 22  * will not be able to disable it.
 23  *
 24  * In addition to device configuration, the DSCR block may provide registers
 25  * which are used to reset SoC peripherals, provide device ID information,
 26  * provide MAC addresses, and other miscellaneous functions.
 27  */
 28 
 29 #include <linux/of.h>
 30 #include <linux/of_address.h>
 31 #include <linux/of_platform.h>
 32 #include <linux/module.h>
 33 #include <linux/io.h>
 34 #include <linux/delay.h>
 35 #include <asm/soc.h>
 36 #include <asm/dscr.h>
 37 
 38 #define MAX_DEVSTATE_IDS   32
 39 #define MAX_DEVCTL_REGS     8
 40 #define MAX_DEVSTAT_REGS    8
 41 #define MAX_LOCKED_REGS     4
 42 #define MAX_SOC_EMACS       2
 43 
 44 struct rmii_reset_reg {
 45         u32 reg;
 46         u32 mask;
 47 };
 48 
 49 /*
 50  * Some registerd may be locked. In order to write to these
 51  * registers, the key value must first be written to the lockreg.
 52  */
 53 struct locked_reg {
 54         u32 reg;        /* offset from base */
 55         u32 lockreg;    /* offset from base */
 56         u32 key;        /* unlock key */
 57 };
 58 
 59 /*
 60  * This describes a contiguous area of like control bits used to enable/disable
 61  * SoC devices. Each controllable device is given an ID which is used by the
 62  * individual device drivers to control the device state. These IDs start at
 63  * zero and are assigned sequentially to the control bitfield ranges described
 64  * by this structure.
 65  */
 66 struct devstate_ctl_reg {
 67         u32 reg;                /* register holding the control bits */
 68         u8  start_id;           /* start id of this range */
 69         u8  num_ids;            /* number of devices in this range */
 70         u8  enable_only;        /* bits are write-once to enable only */
 71         u8  enable;             /* value used to enable device */
 72         u8  disable;            /* value used to disable device */
 73         u8  shift;              /* starting (rightmost) bit in range */
 74         u8  nbits;              /* number of bits per device */
 75 };
 76 
 77 
 78 /*
 79  * This describes a region of status bits indicating the state of
 80  * various devices. This is used internally to wait for status
 81  * change completion when enabling/disabling a device. Status is
 82  * optional and not all device controls will have a corresponding
 83  * status.
 84  */
 85 struct devstate_stat_reg {
 86         u32 reg;                /* register holding the status bits */
 87         u8  start_id;           /* start id of this range */
 88         u8  num_ids;            /* number of devices in this range */
 89         u8  enable;             /* value indicating enabled state */
 90         u8  disable;            /* value indicating disabled state */
 91         u8  shift;              /* starting (rightmost) bit in range */
 92         u8  nbits;              /* number of bits per device */
 93 };
 94 
 95 struct devstate_info {
 96         struct devstate_ctl_reg *ctl;
 97         struct devstate_stat_reg *stat;
 98 };
 99 
100 /* These are callbacks to SOC-specific code. */
101 struct dscr_ops {
102         void (*init)(struct device_node *node);
103 };
104 
105 struct dscr_regs {
106         spinlock_t              lock;
107         void __iomem            *base;
108         u32                     kick_reg[2];
109         u32                     kick_key[2];
110         struct locked_reg       locked[MAX_LOCKED_REGS];
111         struct devstate_info    devstate_info[MAX_DEVSTATE_IDS];
112         struct rmii_reset_reg   rmii_resets[MAX_SOC_EMACS];
113         struct devstate_ctl_reg devctl[MAX_DEVCTL_REGS];
114         struct devstate_stat_reg devstat[MAX_DEVSTAT_REGS];
115 };
116 
117 static struct dscr_regs dscr;
118 
119 static struct locked_reg *find_locked_reg(u32 reg)
120 {
121         int i;
122 
123         for (i = 0; i < MAX_LOCKED_REGS; i++)
124                 if (dscr.locked[i].key && reg == dscr.locked[i].reg)
125                         return &dscr.locked[i];
126         return NULL;
127 }
128 
129 /*
130  * Write to a register with one lock
131  */
132 static void dscr_write_locked1(u32 reg, u32 val,
133                                u32 lock, u32 key)
134 {
135         void __iomem *reg_addr = dscr.base + reg;
136         void __iomem *lock_addr = dscr.base + lock;
137 
138         /*
139          * For some registers, the lock is relocked after a short number
140          * of cycles. We have to put the lock write and register write in
141          * the same fetch packet to meet this timing. The .align ensures
142          * the two stw instructions are in the same fetch packet.
143          */
144         asm volatile ("b        .s2     0f\n"
145                       "nop      5\n"
146                       "    .align 5\n"
147                       "0:\n"
148                       "stw      .D1T2   %3,*%2\n"
149                       "stw      .D1T2   %1,*%0\n"
150                       :
151                       : "a"(reg_addr), "b"(val), "a"(lock_addr), "b"(key)
152                 );
153 
154         /* in case the hw doesn't reset the lock */
155         soc_writel(0, lock_addr);
156 }
157 
158 /*
159  * Write to a register protected by two lock registers
160  */
161 static void dscr_write_locked2(u32 reg, u32 val,
162                                u32 lock0, u32 key0,
163                                u32 lock1, u32 key1)
164 {
165         soc_writel(key0, dscr.base + lock0);
166         soc_writel(key1, dscr.base + lock1);
167         soc_writel(val, dscr.base + reg);
168         soc_writel(0, dscr.base + lock0);
169         soc_writel(0, dscr.base + lock1);
170 }
171 
172 static void dscr_write(u32 reg, u32 val)
173 {
174         struct locked_reg *lock;
175 
176         lock = find_locked_reg(reg);
177         if (lock)
178                 dscr_write_locked1(reg, val, lock->lockreg, lock->key);
179         else if (dscr.kick_key[0])
180                 dscr_write_locked2(reg, val, dscr.kick_reg[0], dscr.kick_key[0],
181                                    dscr.kick_reg[1], dscr.kick_key[1]);
182         else
183                 soc_writel(val, dscr.base + reg);
184 }
185 
186 
187 /*
188  * Drivers can use this interface to enable/disable SoC IP blocks.
189  */
190 void dscr_set_devstate(int id, enum dscr_devstate_t state)
191 {
192         struct devstate_ctl_reg *ctl;
193         struct devstate_stat_reg *stat;
194         struct devstate_info *info;
195         u32 ctl_val, val;
196         int ctl_shift, ctl_mask;
197         unsigned long flags;
198 
199         if (!dscr.base)
200                 return;
201 
202         if (id < 0 || id >= MAX_DEVSTATE_IDS)
203                 return;
204 
205         info = &dscr.devstate_info[id];
206         ctl = info->ctl;
207         stat = info->stat;
208 
209         if (ctl == NULL)
210                 return;
211 
212         ctl_shift = ctl->shift + ctl->nbits * (id - ctl->start_id);
213         ctl_mask = ((1 << ctl->nbits) - 1) << ctl_shift;
214 
215         switch (state) {
216         case DSCR_DEVSTATE_ENABLED:
217                 ctl_val = ctl->enable << ctl_shift;
218                 break;
219         case DSCR_DEVSTATE_DISABLED:
220                 if (ctl->enable_only)
221                         return;
222                 ctl_val = ctl->disable << ctl_shift;
223                 break;
224         default:
225                 return;
226         }
227 
228         spin_lock_irqsave(&dscr.lock, flags);
229 
230         val = soc_readl(dscr.base + ctl->reg);
231         val &= ~ctl_mask;
232         val |= ctl_val;
233 
234         dscr_write(ctl->reg, val);
235 
236         spin_unlock_irqrestore(&dscr.lock, flags);
237 
238         if (!stat)
239                 return;
240 
241         ctl_shift = stat->shift + stat->nbits * (id - stat->start_id);
242 
243         if (state == DSCR_DEVSTATE_ENABLED)
244                 ctl_val = stat->enable;
245         else
246                 ctl_val = stat->disable;
247 
248         do {
249                 val = soc_readl(dscr.base + stat->reg);
250                 val >>= ctl_shift;
251                 val &= ((1 << stat->nbits) - 1);
252         } while (val != ctl_val);
253 }
254 EXPORT_SYMBOL(dscr_set_devstate);
255 
256 /*
257  * Drivers can use this to reset RMII module.
258  */
259 void dscr_rmii_reset(int id, int assert)
260 {
261         struct rmii_reset_reg *r;
262         unsigned long flags;
263         u32 val;
264 
265         if (id < 0 || id >= MAX_SOC_EMACS)
266                 return;
267 
268         r = &dscr.rmii_resets[id];
269         if (r->mask == 0)
270                 return;
271 
272         spin_lock_irqsave(&dscr.lock, flags);
273 
274         val = soc_readl(dscr.base + r->reg);
275         if (assert)
276                 dscr_write(r->reg, val | r->mask);
277         else
278                 dscr_write(r->reg, val & ~(r->mask));
279 
280         spin_unlock_irqrestore(&dscr.lock, flags);
281 }
282 EXPORT_SYMBOL(dscr_rmii_reset);
283 
284 static void __init dscr_parse_devstat(struct device_node *node,
285                                       void __iomem *base)
286 {
287         u32 val;
288         int err;
289 
290         err = of_property_read_u32_array(node, "ti,dscr-devstat", &val, 1);
291         if (!err)
292                 c6x_devstat = soc_readl(base + val);
293         printk(KERN_INFO "DEVSTAT: %08x\n", c6x_devstat);
294 }
295 
296 static void __init dscr_parse_silicon_rev(struct device_node *node,
297                                          void __iomem *base)
298 {
299         u32 vals[3];
300         int err;
301 
302         err = of_property_read_u32_array(node, "ti,dscr-silicon-rev", vals, 3);
303         if (!err) {
304                 c6x_silicon_rev = soc_readl(base + vals[0]);
305                 c6x_silicon_rev >>= vals[1];
306                 c6x_silicon_rev &= vals[2];
307         }
308 }
309 
310 /*
311  * Some SoCs will have a pair of fuse registers which hold
312  * an ethernet MAC address. The "ti,dscr-mac-fuse-regs"
313  * property is a mapping from fuse register bytes to MAC
314  * address bytes. The expected format is:
315  *
316  *      ti,dscr-mac-fuse-regs = <reg0 b3 b2 b1 b0
317  *                               reg1 b3 b2 b1 b0>
318  *
319  * reg0 and reg1 are the offsets of the two fuse registers.
320  * b3-b0 positionally represent bytes within the fuse register.
321  * b3 is the most significant byte and b0 is the least.
322  * Allowable values for b3-b0 are:
323  *
324  *        0 = fuse register byte not used in MAC address
325  *      1-6 = index+1 into c6x_fuse_mac[]
326  */
327 static void __init dscr_parse_mac_fuse(struct device_node *node,
328                                        void __iomem *base)
329 {
330         u32 vals[10], fuse;
331         int f, i, j, err;
332 
333         err = of_property_read_u32_array(node, "ti,dscr-mac-fuse-regs",
334                                          vals, 10);
335         if (err)
336                 return;
337 
338         for (f = 0; f < 2; f++) {
339                 fuse = soc_readl(base + vals[f * 5]);
340                 for (j = (f * 5) + 1, i = 24; i >= 0; i -= 8, j++)
341                         if (vals[j] && vals[j] <= 6)
342                                 c6x_fuse_mac[vals[j] - 1] = fuse >> i;
343         }
344 }
345 
346 static void __init dscr_parse_rmii_resets(struct device_node *node,
347                                           void __iomem *base)
348 {
349         const __be32 *p;
350         int i, size;
351 
352         /* look for RMII reset registers */
353         p = of_get_property(node, "ti,dscr-rmii-resets", &size);
354         if (p) {
355                 /* parse all the reg/mask pairs we can handle */
356                 size /= (sizeof(*p) * 2);
357                 if (size > MAX_SOC_EMACS)
358                         size = MAX_SOC_EMACS;
359 
360                 for (i = 0; i < size; i++) {
361                         dscr.rmii_resets[i].reg = be32_to_cpup(p++);
362                         dscr.rmii_resets[i].mask = be32_to_cpup(p++);
363                 }
364         }
365 }
366 
367 
368 static void __init dscr_parse_privperm(struct device_node *node,
369                                        void __iomem *base)
370 {
371         u32 vals[2];
372         int err;
373 
374         err = of_property_read_u32_array(node, "ti,dscr-privperm", vals, 2);
375         if (err)
376                 return;
377         dscr_write(vals[0], vals[1]);
378 }
379 
380 /*
381  * SoCs may have "locked" DSCR registers which can only be written
382  * to only after writing a key value to a lock registers. These
383  * regisers can be described with the "ti,dscr-locked-regs" property.
384  * This property provides a list of register descriptions with each
385  * description consisting of three values.
386  *
387  *      ti,dscr-locked-regs = <reg0 lockreg0 key0
388  *                               ...
389  *                             regN lockregN keyN>;
390  *
391  * reg is the offset of the locked register
392  * lockreg is the offset of the lock register
393  * key is the unlock key written to lockreg
394  *
395  */
396 static void __init dscr_parse_locked_regs(struct device_node *node,
397                                           void __iomem *base)
398 {
399         struct locked_reg *r;
400         const __be32 *p;
401         int i, size;
402 
403         p = of_get_property(node, "ti,dscr-locked-regs", &size);
404         if (p) {
405                 /* parse all the register descriptions we can handle */
406                 size /= (sizeof(*p) * 3);
407                 if (size > MAX_LOCKED_REGS)
408                         size = MAX_LOCKED_REGS;
409 
410                 for (i = 0; i < size; i++) {
411                         r = &dscr.locked[i];
412 
413                         r->reg = be32_to_cpup(p++);
414                         r->lockreg = be32_to_cpup(p++);
415                         r->key = be32_to_cpup(p++);
416                 }
417         }
418 }
419 
420 /*
421  * SoCs may have DSCR registers which are only write enabled after
422  * writing specific key values to two registers. The two key registers
423  * and the key values can be parsed from a "ti,dscr-kick-regs"
424  * propety with the following layout:
425  *
426  *      ti,dscr-kick-regs = <kickreg0 key0 kickreg1 key1>
427  *
428  * kickreg is the offset of the "kick" register
429  * key is the value which unlocks writing for protected regs
430  */
431 static void __init dscr_parse_kick_regs(struct device_node *node,
432                                         void __iomem *base)
433 {
434         u32 vals[4];
435         int err;
436 
437         err = of_property_read_u32_array(node, "ti,dscr-kick-regs", vals, 4);
438         if (!err) {
439                 dscr.kick_reg[0] = vals[0];
440                 dscr.kick_key[0] = vals[1];
441                 dscr.kick_reg[1] = vals[2];
442                 dscr.kick_key[1] = vals[3];
443         }
444 }
445 
446 
447 /*
448  * SoCs may provide controls to enable/disable individual IP blocks. These
449  * controls in the DSCR usually control pin drivers but also may control
450  * clocking and or resets. The device tree is used to describe the bitfields
451  * in registers used to control device state. The number of bits and their
452  * values may vary even within the same register.
453  *
454  * The layout of these bitfields is described by the ti,dscr-devstate-ctl-regs
455  * property. This property is a list where each element describes a contiguous
456  * range of control fields with like properties. Each element of the list
457  * consists of 7 cells with the following values:
458  *
459  *   start_id num_ids reg enable disable start_bit nbits
460  *
461  * start_id is device id for the first device control in the range
462  * num_ids is the number of device controls in the range
463  * reg is the offset of the register holding the control bits
464  * enable is the value to enable a device
465  * disable is the value to disable a device (0xffffffff if cannot disable)
466  * start_bit is the bit number of the first bit in the range
467  * nbits is the number of bits per device control
468  */
469 static void __init dscr_parse_devstate_ctl_regs(struct device_node *node,
470                                                 void __iomem *base)
471 {
472         struct devstate_ctl_reg *r;
473         const __be32 *p;
474         int i, j, size;
475 
476         p = of_get_property(node, "ti,dscr-devstate-ctl-regs", &size);
477         if (p) {
478                 /* parse all the ranges we can handle */
479                 size /= (sizeof(*p) * 7);
480                 if (size > MAX_DEVCTL_REGS)
481                         size = MAX_DEVCTL_REGS;
482 
483                 for (i = 0; i < size; i++) {
484                         r = &dscr.devctl[i];
485 
486                         r->start_id = be32_to_cpup(p++);
487                         r->num_ids = be32_to_cpup(p++);
488                         r->reg = be32_to_cpup(p++);
489                         r->enable = be32_to_cpup(p++);
490                         r->disable = be32_to_cpup(p++);
491                         if (r->disable == 0xffffffff)
492                                 r->enable_only = 1;
493                         r->shift = be32_to_cpup(p++);
494                         r->nbits = be32_to_cpup(p++);
495 
496                         for (j = r->start_id;
497                              j < (r->start_id + r->num_ids);
498                              j++)
499                                 dscr.devstate_info[j].ctl = r;
500                 }
501         }
502 }
503 
504 /*
505  * SoCs may provide status registers indicating the state (enabled/disabled) of
506  * devices on the SoC. The device tree is used to describe the bitfields in
507  * registers used to provide device status. The number of bits and their
508  * values used to provide status may vary even within the same register.
509  *
510  * The layout of these bitfields is described by the ti,dscr-devstate-stat-regs
511  * property. This property is a list where each element describes a contiguous
512  * range of status fields with like properties. Each element of the list
513  * consists of 7 cells with the following values:
514  *
515  *   start_id num_ids reg enable disable start_bit nbits
516  *
517  * start_id is device id for the first device status in the range
518  * num_ids is the number of devices covered by the range
519  * reg is the offset of the register holding the status bits
520  * enable is the value indicating device is enabled
521  * disable is the value indicating device is disabled
522  * start_bit is the bit number of the first bit in the range
523  * nbits is the number of bits per device status
524  */
525 static void __init dscr_parse_devstate_stat_regs(struct device_node *node,
526                                                  void __iomem *base)
527 {
528         struct devstate_stat_reg *r;
529         const __be32 *p;
530         int i, j, size;
531 
532         p = of_get_property(node, "ti,dscr-devstate-stat-regs", &size);
533         if (p) {
534                 /* parse all the ranges we can handle */
535                 size /= (sizeof(*p) * 7);
536                 if (size > MAX_DEVSTAT_REGS)
537                         size = MAX_DEVSTAT_REGS;
538 
539                 for (i = 0; i < size; i++) {
540                         r = &dscr.devstat[i];
541 
542                         r->start_id = be32_to_cpup(p++);
543                         r->num_ids = be32_to_cpup(p++);
544                         r->reg = be32_to_cpup(p++);
545                         r->enable = be32_to_cpup(p++);
546                         r->disable = be32_to_cpup(p++);
547                         r->shift = be32_to_cpup(p++);
548                         r->nbits = be32_to_cpup(p++);
549 
550                         for (j = r->start_id;
551                              j < (r->start_id + r->num_ids);
552                              j++)
553                                 dscr.devstate_info[j].stat = r;
554                 }
555         }
556 }
557 
558 static struct of_device_id dscr_ids[] __initdata = {
559         { .compatible = "ti,c64x+dscr" },
560         {}
561 };
562 
563 /*
564  * Probe for DSCR area.
565  *
566  * This has to be done early on in case timer or interrupt controller
567  * needs something. e.g. On C6455 SoC, timer must be enabled through
568  * DSCR before it is functional.
569  */
570 void __init dscr_probe(void)
571 {
572         struct device_node *node;
573         void __iomem *base;
574 
575         spin_lock_init(&dscr.lock);
576 
577         node = of_find_matching_node(NULL, dscr_ids);
578         if (!node)
579                 return;
580 
581         base = of_iomap(node, 0);
582         if (!base) {
583                 of_node_put(node);
584                 return;
585         }
586 
587         dscr.base = base;
588 
589         dscr_parse_devstat(node, base);
590         dscr_parse_silicon_rev(node, base);
591         dscr_parse_mac_fuse(node, base);
592         dscr_parse_rmii_resets(node, base);
593         dscr_parse_locked_regs(node, base);
594         dscr_parse_kick_regs(node, base);
595         dscr_parse_devstate_ctl_regs(node, base);
596         dscr_parse_devstate_stat_regs(node, base);
597         dscr_parse_privperm(node, base);
598 }
599 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp