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Linux/arch/c6x/platforms/timer64.c

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  1 /*
  2  *  Copyright (C) 2010, 2011 Texas Instruments Incorporated
  3  *  Contributed by: Mark Salter (msalter@redhat.com)
  4  *
  5  *  This program is free software; you can redistribute it and/or modify
  6  *  it under the terms of the GNU General Public License version 2 as
  7  *  published by the Free Software Foundation.
  8  */
  9 
 10 #include <linux/clockchips.h>
 11 #include <linux/interrupt.h>
 12 #include <linux/io.h>
 13 #include <linux/of.h>
 14 #include <linux/of_irq.h>
 15 #include <linux/of_address.h>
 16 #include <asm/soc.h>
 17 #include <asm/dscr.h>
 18 #include <asm/special_insns.h>
 19 #include <asm/timer64.h>
 20 
 21 struct timer_regs {
 22         u32     reserved0;
 23         u32     emumgt;
 24         u32     reserved1;
 25         u32     reserved2;
 26         u32     cntlo;
 27         u32     cnthi;
 28         u32     prdlo;
 29         u32     prdhi;
 30         u32     tcr;
 31         u32     tgcr;
 32         u32     wdtcr;
 33 };
 34 
 35 static struct timer_regs __iomem *timer;
 36 
 37 #define TCR_TSTATLO          0x001
 38 #define TCR_INVOUTPLO        0x002
 39 #define TCR_INVINPLO         0x004
 40 #define TCR_CPLO             0x008
 41 #define TCR_ENAMODELO_ONCE   0x040
 42 #define TCR_ENAMODELO_CONT   0x080
 43 #define TCR_ENAMODELO_MASK   0x0c0
 44 #define TCR_PWIDLO_MASK      0x030
 45 #define TCR_CLKSRCLO         0x100
 46 #define TCR_TIENLO           0x200
 47 #define TCR_TSTATHI          (0x001 << 16)
 48 #define TCR_INVOUTPHI        (0x002 << 16)
 49 #define TCR_CPHI             (0x008 << 16)
 50 #define TCR_PWIDHI_MASK      (0x030 << 16)
 51 #define TCR_ENAMODEHI_ONCE   (0x040 << 16)
 52 #define TCR_ENAMODEHI_CONT   (0x080 << 16)
 53 #define TCR_ENAMODEHI_MASK   (0x0c0 << 16)
 54 
 55 #define TGCR_TIMLORS         0x001
 56 #define TGCR_TIMHIRS         0x002
 57 #define TGCR_TIMMODE_UD32    0x004
 58 #define TGCR_TIMMODE_WDT64   0x008
 59 #define TGCR_TIMMODE_CD32    0x00c
 60 #define TGCR_TIMMODE_MASK    0x00c
 61 #define TGCR_PSCHI_MASK      (0x00f << 8)
 62 #define TGCR_TDDRHI_MASK     (0x00f << 12)
 63 
 64 /*
 65  * Timer clocks are divided down from the CPU clock
 66  * The divisor is in the EMUMGTCLKSPD register
 67  */
 68 #define TIMER_DIVISOR \
 69         ((soc_readl(&timer->emumgt) & (0xf << 16)) >> 16)
 70 
 71 #define TIMER64_RATE (c6x_core_freq / TIMER_DIVISOR)
 72 
 73 #define TIMER64_MODE_DISABLED 0
 74 #define TIMER64_MODE_ONE_SHOT TCR_ENAMODELO_ONCE
 75 #define TIMER64_MODE_PERIODIC TCR_ENAMODELO_CONT
 76 
 77 static int timer64_mode;
 78 static int timer64_devstate_id = -1;
 79 
 80 static void timer64_config(unsigned long period)
 81 {
 82         u32 tcr = soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK;
 83 
 84         soc_writel(tcr, &timer->tcr);
 85         soc_writel(period - 1, &timer->prdlo);
 86         soc_writel(0, &timer->cntlo);
 87         tcr |= timer64_mode;
 88         soc_writel(tcr, &timer->tcr);
 89 }
 90 
 91 static void timer64_enable(void)
 92 {
 93         u32 val;
 94 
 95         if (timer64_devstate_id >= 0)
 96                 dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
 97 
 98         /* disable timer, reset count */
 99         soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
100         soc_writel(0, &timer->prdlo);
101 
102         /* use internal clock and 1 cycle pulse width */
103         val = soc_readl(&timer->tcr);
104         soc_writel(val & ~(TCR_CLKSRCLO | TCR_PWIDLO_MASK), &timer->tcr);
105 
106         /* dual 32-bit unchained mode */
107         val = soc_readl(&timer->tgcr) & ~TGCR_TIMMODE_MASK;
108         soc_writel(val, &timer->tgcr);
109         soc_writel(val | (TGCR_TIMLORS | TGCR_TIMMODE_UD32), &timer->tgcr);
110 }
111 
112 static void timer64_disable(void)
113 {
114         /* disable timer, reset count */
115         soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
116         soc_writel(0, &timer->prdlo);
117 
118         if (timer64_devstate_id >= 0)
119                 dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_DISABLED);
120 }
121 
122 static int next_event(unsigned long delta,
123                       struct clock_event_device *evt)
124 {
125         timer64_config(delta);
126         return 0;
127 }
128 
129 static int set_periodic(struct clock_event_device *evt)
130 {
131         timer64_enable();
132         timer64_mode = TIMER64_MODE_PERIODIC;
133         timer64_config(TIMER64_RATE / HZ);
134         return 0;
135 }
136 
137 static int set_oneshot(struct clock_event_device *evt)
138 {
139         timer64_enable();
140         timer64_mode = TIMER64_MODE_ONE_SHOT;
141         return 0;
142 }
143 
144 static int shutdown(struct clock_event_device *evt)
145 {
146         timer64_mode = TIMER64_MODE_DISABLED;
147         timer64_disable();
148         return 0;
149 }
150 
151 static struct clock_event_device t64_clockevent_device = {
152         .name                   = "TIMER64_EVT32_TIMER",
153         .features               = CLOCK_EVT_FEAT_ONESHOT |
154                                   CLOCK_EVT_FEAT_PERIODIC,
155         .rating                 = 200,
156         .set_state_shutdown     = shutdown,
157         .set_state_periodic     = set_periodic,
158         .set_state_oneshot      = set_oneshot,
159         .set_next_event         = next_event,
160 };
161 
162 static irqreturn_t timer_interrupt(int irq, void *dev_id)
163 {
164         struct clock_event_device *cd = &t64_clockevent_device;
165 
166         cd->event_handler(cd);
167 
168         return IRQ_HANDLED;
169 }
170 
171 static struct irqaction timer_iact = {
172         .name           = "timer",
173         .flags          = IRQF_TIMER,
174         .handler        = timer_interrupt,
175         .dev_id         = &t64_clockevent_device,
176 };
177 
178 void __init timer64_init(void)
179 {
180         struct clock_event_device *cd = &t64_clockevent_device;
181         struct device_node *np, *first = NULL;
182         u32 val;
183         int err, found = 0;
184 
185         for_each_compatible_node(np, NULL, "ti,c64x+timer64") {
186                 err = of_property_read_u32(np, "ti,core-mask", &val);
187                 if (!err) {
188                         if (val & (1 << get_coreid())) {
189                                 found = 1;
190                                 break;
191                         }
192                 } else if (!first)
193                         first = np;
194         }
195         if (!found) {
196                 /* try first one with no core-mask */
197                 if (first)
198                         np = of_node_get(first);
199                 else {
200                         pr_debug("Cannot find ti,c64x+timer64 timer.\n");
201                         return;
202                 }
203         }
204 
205         timer = of_iomap(np, 0);
206         if (!timer) {
207                 pr_debug("%pOF: Cannot map timer registers.\n", np);
208                 goto out;
209         }
210         pr_debug("%pOF: Timer registers=%p.\n", np, timer);
211 
212         cd->irq = irq_of_parse_and_map(np, 0);
213         if (cd->irq == NO_IRQ) {
214                 pr_debug("%pOF: Cannot find interrupt.\n", np);
215                 iounmap(timer);
216                 goto out;
217         }
218 
219         /* If there is a device state control, save the ID. */
220         err = of_property_read_u32(np, "ti,dscr-dev-enable", &val);
221         if (!err) {
222                 timer64_devstate_id = val;
223 
224                 /*
225                  * It is necessary to enable the timer block here because
226                  * the TIMER_DIVISOR macro needs to read a timer register
227                  * to get the divisor.
228                  */
229                 dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
230         }
231 
232         pr_debug("%pOF: Timer irq=%d.\n", np, cd->irq);
233 
234         clockevents_calc_mult_shift(cd, c6x_core_freq / TIMER_DIVISOR, 5);
235 
236         cd->max_delta_ns        = clockevent_delta2ns(0x7fffffff, cd);
237         cd->max_delta_ticks     = 0x7fffffff;
238         cd->min_delta_ns        = clockevent_delta2ns(250, cd);
239         cd->min_delta_ticks     = 250;
240 
241         cd->cpumask             = cpumask_of(smp_processor_id());
242 
243         clockevents_register_device(cd);
244         setup_irq(cd->irq, &timer_iact);
245 
246 out:
247         of_node_put(np);
248         return;
249 }
250 

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