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Linux/arch/cris/arch-v32/drivers/mach-fs/nandflash.c

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  1 /*
  2  *  arch/cris/arch-v32/drivers/nandflash.c
  3  *
  4  *  Copyright (c) 2004
  5  *
  6  *  Derived from drivers/mtd/nand/spia.c
  7  *        Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  *
 13  */
 14 
 15 #include <linux/slab.h>
 16 #include <linux/init.h>
 17 #include <linux/module.h>
 18 #include <linux/mtd/mtd.h>
 19 #include <linux/mtd/nand.h>
 20 #include <linux/mtd/partitions.h>
 21 #include <arch/memmap.h>
 22 #include <hwregs/reg_map.h>
 23 #include <hwregs/reg_rdwr.h>
 24 #include <hwregs/gio_defs.h>
 25 #include <hwregs/bif_core_defs.h>
 26 #include <asm/io.h>
 27 
 28 #define CE_BIT 4
 29 #define CLE_BIT 5
 30 #define ALE_BIT 6
 31 #define BY_BIT 7
 32 
 33 struct mtd_info_wrapper {
 34         struct nand_chip chip;
 35 };
 36 
 37 /* Bitmask for control pins */
 38 #define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
 39 
 40 /* Bitmask for mtd nand control bits */
 41 #define CTRL_BITMASK (NAND_NCE | NAND_CLE | NAND_ALE)
 42 
 43 
 44 static struct mtd_info *crisv32_mtd;
 45 /*
 46  *      hardware specific access to control-lines
 47  */
 48 static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
 49                               unsigned int ctrl)
 50 {
 51         unsigned long flags;
 52         reg_gio_rw_pa_dout dout;
 53         struct nand_chip *this = mtd_to_nand(mtd);
 54 
 55         local_irq_save(flags);
 56 
 57         /* control bits change */
 58         if (ctrl & NAND_CTRL_CHANGE) {
 59                 dout = REG_RD(gio, regi_gio, rw_pa_dout);
 60                 dout.data &= ~PIN_BITMASK;
 61 
 62 #if (CE_BIT == 4 && NAND_NCE == 1 &&  \
 63      CLE_BIT == 5 && NAND_CLE == 2 && \
 64      ALE_BIT == 6 && NAND_ALE == 4)
 65                 /* Pins in same order as control bits, but shifted.
 66                  * Optimize for this case; works for 2.6.18 */
 67                 dout.data |= ((ctrl & CTRL_BITMASK) ^ NAND_NCE) << CE_BIT;
 68 #else
 69                 /* the slow way */
 70                 if (!(ctrl & NAND_NCE))
 71                         dout.data |= (1 << CE_BIT);
 72                 if (ctrl & NAND_CLE)
 73                         dout.data |= (1 << CLE_BIT);
 74                 if (ctrl & NAND_ALE)
 75                         dout.data |= (1 << ALE_BIT);
 76 #endif
 77                 REG_WR(gio, regi_gio, rw_pa_dout, dout);
 78         }
 79 
 80         /* command to chip */
 81         if (cmd != NAND_CMD_NONE)
 82                 writeb(cmd, this->IO_ADDR_W);
 83 
 84         local_irq_restore(flags);
 85 }
 86 
 87 /*
 88 *       read device ready pin
 89 */
 90 static int crisv32_device_ready(struct mtd_info *mtd)
 91 {
 92         reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din);
 93         return ((din.data & (1 << BY_BIT)) >> BY_BIT);
 94 }
 95 
 96 /*
 97  * Main initialization routine
 98  */
 99 struct mtd_info *__init crisv32_nand_flash_probe(void)
100 {
101         void __iomem *read_cs;
102         void __iomem *write_cs;
103 
104         reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core,
105                 rw_grp3_cfg);
106         reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe);
107         struct mtd_info_wrapper *wrapper;
108         struct nand_chip *this;
109         int err = 0;
110 
111         /* Allocate memory for MTD device structure and private data */
112         wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL);
113         if (!wrapper) {
114                 printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
115                         "device structure.\n");
116                 err = -ENOMEM;
117                 return NULL;
118         }
119 
120         read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192);
121         write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192);
122 
123         if (!read_cs || !write_cs) {
124                 printk(KERN_ERR "CRISv32 NAND ioremap failed\n");
125                 err = -EIO;
126                 goto out_mtd;
127         }
128 
129         /* Get pointer to private data */
130         this = &wrapper->chip;
131         crisv32_mtd = nand_to_mtd(this);
132 
133         pa_oe.oe |= 1 << CE_BIT;
134         pa_oe.oe |= 1 << ALE_BIT;
135         pa_oe.oe |= 1 << CLE_BIT;
136         pa_oe.oe &= ~(1 << BY_BIT);
137         REG_WR(gio, regi_gio, rw_pa_oe, pa_oe);
138 
139         bif_cfg.gated_csp0 = regk_bif_core_rd;
140         bif_cfg.gated_csp1 = regk_bif_core_wr;
141         REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);
142 
143         /* Set address of NAND IO lines */
144         this->IO_ADDR_R = read_cs;
145         this->IO_ADDR_W = write_cs;
146         this->cmd_ctrl = crisv32_hwcontrol;
147         this->dev_ready = crisv32_device_ready;
148         /* 20 us command delay time */
149         this->chip_delay = 20;
150         this->ecc.mode = NAND_ECC_SOFT;
151         this->ecc.algo = NAND_ECC_HAMMING;
152 
153         /* Enable the following for a flash based bad block table */
154         /* this->bbt_options = NAND_BBT_USE_FLASH; */
155 
156         /* Scan to find existence of the device */
157         if (nand_scan(crisv32_mtd, 1)) {
158                 err = -ENXIO;
159                 goto out_ior;
160         }
161 
162         return crisv32_mtd;
163 
164 out_ior:
165         iounmap((void *)read_cs);
166         iounmap((void *)write_cs);
167 out_mtd:
168         kfree(wrapper);
169         return NULL;
170 }
171 
172 

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