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Linux/arch/cris/arch-v32/kernel/time.c

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  1 /*
  2  *  linux/arch/cris/arch-v32/kernel/time.c
  3  *
  4  *  Copyright (C) 2003-2010 Axis Communications AB
  5  *
  6  */
  7 
  8 #include <linux/timex.h>
  9 #include <linux/time.h>
 10 #include <linux/clocksource.h>
 11 #include <linux/clockchips.h>
 12 #include <linux/interrupt.h>
 13 #include <linux/swap.h>
 14 #include <linux/sched.h>
 15 #include <linux/init.h>
 16 #include <linux/threads.h>
 17 #include <linux/cpufreq.h>
 18 #include <linux/sched_clock.h>
 19 #include <linux/mm.h>
 20 #include <asm/types.h>
 21 #include <asm/signal.h>
 22 #include <asm/io.h>
 23 #include <asm/delay.h>
 24 #include <asm/irq.h>
 25 #include <asm/irq_regs.h>
 26 
 27 #include <hwregs/reg_map.h>
 28 #include <hwregs/reg_rdwr.h>
 29 #include <hwregs/timer_defs.h>
 30 #include <hwregs/intr_vect_defs.h>
 31 #ifdef CONFIG_CRIS_MACH_ARTPEC3
 32 #include <hwregs/clkgen_defs.h>
 33 #endif
 34 
 35 /* Watchdog defines */
 36 #define ETRAX_WD_KEY_MASK       0x7F /* key is 7 bit */
 37 #define ETRAX_WD_HZ             763 /* watchdog counts at 763 Hz */
 38 /* Number of 763 counts before watchdog bites */
 39 #define ETRAX_WD_CNT            ((2*ETRAX_WD_HZ)/HZ + 1)
 40 
 41 #define CRISV32_TIMER_FREQ      (100000000lu)
 42 
 43 unsigned long timer_regs[NR_CPUS] =
 44 {
 45         regi_timer0,
 46 };
 47 
 48 extern int set_rtc_mmss(unsigned long nowtime);
 49 
 50 #ifdef CONFIG_CPU_FREQ
 51 static int cris_time_freq_notifier(struct notifier_block *nb,
 52                                    unsigned long val, void *data);
 53 
 54 static struct notifier_block cris_time_freq_notifier_block = {
 55         .notifier_call = cris_time_freq_notifier,
 56 };
 57 #endif
 58 
 59 unsigned long get_ns_in_jiffie(void)
 60 {
 61         reg_timer_r_tmr0_data data;
 62         unsigned long ns;
 63 
 64         data = REG_RD(timer, regi_timer0, r_tmr0_data);
 65         ns = (TIMER0_DIV - data) * 10;
 66         return ns;
 67 }
 68 
 69 /* From timer MDS describing the hardware watchdog:
 70  * 4.3.1 Watchdog Operation
 71  * The watchdog timer is an 8-bit timer with a configurable start value.
 72  * Once started the watchdog counts downwards with a frequency of 763 Hz
 73  * (100/131072 MHz). When the watchdog counts down to 1, it generates an
 74  * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
 75  * chip.
 76  */
 77 /* This gives us 1.3 ms to do something useful when the NMI comes */
 78 
 79 /* Right now, starting the watchdog is the same as resetting it */
 80 #define start_watchdog reset_watchdog
 81 
 82 #if defined(CONFIG_ETRAX_WATCHDOG)
 83 static short int watchdog_key = 42;  /* arbitrary 7 bit number */
 84 #endif
 85 
 86 /* Number of pages to consider "out of memory". It is normal that the memory
 87  * is used though, so set this really low. */
 88 #define WATCHDOG_MIN_FREE_PAGES 8
 89 
 90 #if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
 91 /* for reliable NICE_DOGGY behaviour */
 92 static int bite_in_progress;
 93 #endif
 94 
 95 void reset_watchdog(void)
 96 {
 97 #if defined(CONFIG_ETRAX_WATCHDOG)
 98         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 99 
100 #if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
101         if (unlikely(bite_in_progress))
102                 return;
103 #endif
104         /* Only keep watchdog happy as long as we have memory left! */
105         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
106                 /* Reset the watchdog with the inverse of the old key */
107                 /* Invert key, which is 7 bits */
108                 watchdog_key ^= ETRAX_WD_KEY_MASK;
109                 wd_ctrl.cnt = ETRAX_WD_CNT;
110                 wd_ctrl.cmd = regk_timer_start;
111                 wd_ctrl.key = watchdog_key;
112                 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
113         }
114 #endif
115 }
116 
117 /* stop the watchdog - we still need the correct key */
118 
119 void stop_watchdog(void)
120 {
121 #if defined(CONFIG_ETRAX_WATCHDOG)
122         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
123         watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
124         wd_ctrl.cnt = ETRAX_WD_CNT;
125         wd_ctrl.cmd = regk_timer_stop;
126         wd_ctrl.key = watchdog_key;
127         REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
128 #endif
129 }
130 
131 extern void show_registers(struct pt_regs *regs);
132 
133 void handle_watchdog_bite(struct pt_regs *regs)
134 {
135 #if defined(CONFIG_ETRAX_WATCHDOG)
136         extern int cause_of_death;
137 
138         nmi_enter();
139         oops_in_progress = 1;
140 #if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
141         bite_in_progress = 1;
142 #endif
143         printk(KERN_WARNING "Watchdog bite\n");
144 
145         /* Check if forced restart or unexpected watchdog */
146         if (cause_of_death == 0xbedead) {
147 #ifdef CONFIG_CRIS_MACH_ARTPEC3
148                 /* There is a bug in Artpec-3 (voodoo TR 78) that requires
149                  * us to go to lower frequency for the reset to be reliable
150                  */
151                 reg_clkgen_rw_clk_ctrl ctrl =
152                         REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
153                 ctrl.pll = 0;
154                 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
155 #endif
156                 while(1);
157         }
158 
159         /* Unexpected watchdog, stop the watchdog and dump registers. */
160         stop_watchdog();
161         printk(KERN_WARNING "Oops: bitten by watchdog\n");
162         show_registers(regs);
163         oops_in_progress = 0;
164         printk("\n"); /* Flush mtdoops.  */
165 #ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
166         reset_watchdog();
167 #endif
168         while(1) /* nothing */;
169 #endif
170 }
171 
172 extern void cris_profile_sample(struct pt_regs *regs);
173 static void __iomem *timer_base;
174 
175 static void crisv32_clkevt_mode(enum clock_event_mode mode,
176                                 struct clock_event_device *dev)
177 {
178         reg_timer_rw_tmr0_ctrl ctrl = {
179                 .op = regk_timer_hold,
180                 .freq = regk_timer_f100,
181         };
182 
183         REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
184 }
185 
186 static int crisv32_clkevt_next_event(unsigned long evt,
187                                      struct clock_event_device *dev)
188 {
189         reg_timer_rw_tmr0_ctrl ctrl = {
190                 .op = regk_timer_ld,
191                 .freq = regk_timer_f100,
192         };
193 
194         REG_WR(timer, timer_base, rw_tmr0_div, evt);
195         REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
196 
197         ctrl.op = regk_timer_run;
198         REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
199 
200         return 0;
201 }
202 
203 static irqreturn_t crisv32_timer_interrupt(int irq, void *dev_id)
204 {
205         struct clock_event_device *evt = dev_id;
206         reg_timer_rw_tmr0_ctrl ctrl = {
207                 .op = regk_timer_hold,
208                 .freq = regk_timer_f100,
209         };
210         reg_timer_rw_ack_intr ack = { .tmr0 = 1 };
211         reg_timer_r_masked_intr intr;
212 
213         intr = REG_RD(timer, timer_base, r_masked_intr);
214         if (!intr.tmr0)
215                 return IRQ_NONE;
216 
217         REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
218         REG_WR(timer, timer_base, rw_ack_intr, ack);
219 
220         reset_watchdog();
221 #ifdef CONFIG_SYSTEM_PROFILER
222         cris_profile_sample(get_irq_regs());
223 #endif
224 
225         evt->event_handler(evt);
226 
227         return IRQ_HANDLED;
228 }
229 
230 static struct clock_event_device crisv32_clockevent = {
231         .name = "crisv32-timer",
232         .rating = 300,
233         .features = CLOCK_EVT_FEAT_ONESHOT,
234         .set_mode = crisv32_clkevt_mode,
235         .set_next_event = crisv32_clkevt_next_event,
236 };
237 
238 /* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */
239 static struct irqaction irq_timer = {
240         .handler = crisv32_timer_interrupt,
241         .flags = IRQF_TIMER | IRQF_SHARED,
242         .name = "crisv32-timer",
243         .dev_id = &crisv32_clockevent,
244 };
245 
246 static u64 notrace crisv32_timer_sched_clock(void)
247 {
248         return REG_RD(timer, timer_base, r_time);
249 }
250 
251 static void __init crisv32_timer_init(void)
252 {
253         reg_timer_rw_intr_mask timer_intr_mask;
254         reg_timer_rw_tmr0_ctrl ctrl = {
255                 .op = regk_timer_hold,
256                 .freq = regk_timer_f100,
257         };
258 
259         REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
260 
261         timer_intr_mask = REG_RD(timer, timer_base, rw_intr_mask);
262         timer_intr_mask.tmr0 = 1;
263         REG_WR(timer, timer_base, rw_intr_mask, timer_intr_mask);
264 }
265 
266 void __init time_init(void)
267 {
268         int irq;
269         int ret;
270 
271         /* Probe for the RTC and read it if it exists.
272          * Before the RTC can be probed the loops_per_usec variable needs
273          * to be initialized to make usleep work. A better value for
274          * loops_per_usec is calculated by the kernel later once the
275          * clock has started.
276          */
277         loops_per_usec = 50;
278 
279         irq = TIMER0_INTR_VECT;
280         timer_base = (void __iomem *) regi_timer0;
281 
282         crisv32_timer_init();
283 
284         sched_clock_register(crisv32_timer_sched_clock, 32,
285                              CRISV32_TIMER_FREQ);
286 
287         clocksource_mmio_init(timer_base + REG_RD_ADDR_timer_r_time,
288                               "crisv32-timer", CRISV32_TIMER_FREQ,
289                               300, 32, clocksource_mmio_readl_up);
290 
291         crisv32_clockevent.cpumask = cpu_possible_mask;
292         crisv32_clockevent.irq = irq;
293 
294         ret = setup_irq(irq, &irq_timer);
295         if (ret)
296                 pr_warn("failed to setup irq %d\n", irq);
297 
298         clockevents_config_and_register(&crisv32_clockevent,
299                                         CRISV32_TIMER_FREQ,
300                                         2, 0xffffffff);
301 
302         /* Enable watchdog if we should use one. */
303 
304 #if defined(CONFIG_ETRAX_WATCHDOG)
305         printk(KERN_INFO "Enabling watchdog...\n");
306         start_watchdog();
307 
308         /* If we use the hardware watchdog, we want to trap it as an NMI
309          * and dump registers before it resets us.  For this to happen, we
310          * must set the "m" NMI enable flag (which once set, is unset only
311          * when an NMI is taken). */
312         {
313                 unsigned long flags;
314                 local_save_flags(flags);
315                 flags |= (1<<30); /* NMI M flag is at bit 30 */
316                 local_irq_restore(flags);
317         }
318 #endif
319 
320 #ifdef CONFIG_CPU_FREQ
321         cpufreq_register_notifier(&cris_time_freq_notifier_block,
322                                   CPUFREQ_TRANSITION_NOTIFIER);
323 #endif
324 }
325 
326 #ifdef CONFIG_CPU_FREQ
327 static int cris_time_freq_notifier(struct notifier_block *nb,
328                                    unsigned long val, void *data)
329 {
330         struct cpufreq_freqs *freqs = data;
331         if (val == CPUFREQ_POSTCHANGE) {
332                 reg_timer_r_tmr0_data data;
333                 reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
334                 do {
335                         data = REG_RD(timer, timer_regs[freqs->cpu],
336                                 r_tmr0_data);
337                 } while (data > 20);
338                 REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
339         }
340         return 0;
341 }
342 #endif
343 

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