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Linux/arch/cris/arch-v32/kernel/time.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 /*
  3  *  linux/arch/cris/arch-v32/kernel/time.c
  4  *
  5  *  Copyright (C) 2003-2010 Axis Communications AB
  6  *
  7  */
  8 
  9 #include <linux/timex.h>
 10 #include <linux/time.h>
 11 #include <linux/clocksource.h>
 12 #include <linux/clockchips.h>
 13 #include <linux/interrupt.h>
 14 #include <linux/swap.h>
 15 #include <linux/sched.h>
 16 #include <linux/init.h>
 17 #include <linux/threads.h>
 18 #include <linux/cpufreq.h>
 19 #include <linux/sched_clock.h>
 20 #include <linux/mm.h>
 21 #include <asm/types.h>
 22 #include <asm/signal.h>
 23 #include <asm/io.h>
 24 #include <asm/delay.h>
 25 #include <asm/irq.h>
 26 #include <asm/irq_regs.h>
 27 
 28 #include <hwregs/reg_map.h>
 29 #include <hwregs/reg_rdwr.h>
 30 #include <hwregs/timer_defs.h>
 31 #include <hwregs/intr_vect_defs.h>
 32 #ifdef CONFIG_CRIS_MACH_ARTPEC3
 33 #include <hwregs/clkgen_defs.h>
 34 #endif
 35 
 36 /* Watchdog defines */
 37 #define ETRAX_WD_KEY_MASK       0x7F /* key is 7 bit */
 38 #define ETRAX_WD_HZ             763 /* watchdog counts at 763 Hz */
 39 /* Number of 763 counts before watchdog bites */
 40 #define ETRAX_WD_CNT            ((2*ETRAX_WD_HZ)/HZ + 1)
 41 
 42 #define CRISV32_TIMER_FREQ      (100000000lu)
 43 
 44 unsigned long timer_regs[NR_CPUS] =
 45 {
 46         regi_timer0,
 47 };
 48 
 49 extern int set_rtc_mmss(unsigned long nowtime);
 50 
 51 #ifdef CONFIG_CPU_FREQ
 52 static int cris_time_freq_notifier(struct notifier_block *nb,
 53                                    unsigned long val, void *data);
 54 
 55 static struct notifier_block cris_time_freq_notifier_block = {
 56         .notifier_call = cris_time_freq_notifier,
 57 };
 58 #endif
 59 
 60 unsigned long get_ns_in_jiffie(void)
 61 {
 62         reg_timer_r_tmr0_data data;
 63         unsigned long ns;
 64 
 65         data = REG_RD(timer, regi_timer0, r_tmr0_data);
 66         ns = (TIMER0_DIV - data) * 10;
 67         return ns;
 68 }
 69 
 70 /* From timer MDS describing the hardware watchdog:
 71  * 4.3.1 Watchdog Operation
 72  * The watchdog timer is an 8-bit timer with a configurable start value.
 73  * Once started the watchdog counts downwards with a frequency of 763 Hz
 74  * (100/131072 MHz). When the watchdog counts down to 1, it generates an
 75  * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
 76  * chip.
 77  */
 78 /* This gives us 1.3 ms to do something useful when the NMI comes */
 79 
 80 /* Right now, starting the watchdog is the same as resetting it */
 81 #define start_watchdog reset_watchdog
 82 
 83 #if defined(CONFIG_ETRAX_WATCHDOG)
 84 static short int watchdog_key = 42;  /* arbitrary 7 bit number */
 85 #endif
 86 
 87 /* Number of pages to consider "out of memory". It is normal that the memory
 88  * is used though, so set this really low. */
 89 #define WATCHDOG_MIN_FREE_PAGES 8
 90 
 91 #if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
 92 /* for reliable NICE_DOGGY behaviour */
 93 static int bite_in_progress;
 94 #endif
 95 
 96 void reset_watchdog(void)
 97 {
 98 #if defined(CONFIG_ETRAX_WATCHDOG)
 99         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
100 
101 #if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
102         if (unlikely(bite_in_progress))
103                 return;
104 #endif
105         /* Only keep watchdog happy as long as we have memory left! */
106         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
107                 /* Reset the watchdog with the inverse of the old key */
108                 /* Invert key, which is 7 bits */
109                 watchdog_key ^= ETRAX_WD_KEY_MASK;
110                 wd_ctrl.cnt = ETRAX_WD_CNT;
111                 wd_ctrl.cmd = regk_timer_start;
112                 wd_ctrl.key = watchdog_key;
113                 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
114         }
115 #endif
116 }
117 
118 /* stop the watchdog - we still need the correct key */
119 
120 void stop_watchdog(void)
121 {
122 #if defined(CONFIG_ETRAX_WATCHDOG)
123         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
124         watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
125         wd_ctrl.cnt = ETRAX_WD_CNT;
126         wd_ctrl.cmd = regk_timer_stop;
127         wd_ctrl.key = watchdog_key;
128         REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
129 #endif
130 }
131 
132 extern void show_registers(struct pt_regs *regs);
133 
134 void handle_watchdog_bite(struct pt_regs *regs)
135 {
136 #if defined(CONFIG_ETRAX_WATCHDOG)
137         extern int cause_of_death;
138 
139         nmi_enter();
140         oops_in_progress = 1;
141 #if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
142         bite_in_progress = 1;
143 #endif
144         printk(KERN_WARNING "Watchdog bite\n");
145 
146         /* Check if forced restart or unexpected watchdog */
147         if (cause_of_death == 0xbedead) {
148 #ifdef CONFIG_CRIS_MACH_ARTPEC3
149                 /* There is a bug in Artpec-3 (voodoo TR 78) that requires
150                  * us to go to lower frequency for the reset to be reliable
151                  */
152                 reg_clkgen_rw_clk_ctrl ctrl =
153                         REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
154                 ctrl.pll = 0;
155                 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
156 #endif
157                 while(1);
158         }
159 
160         /* Unexpected watchdog, stop the watchdog and dump registers. */
161         stop_watchdog();
162         printk(KERN_WARNING "Oops: bitten by watchdog\n");
163         show_registers(regs);
164         oops_in_progress = 0;
165         printk("\n"); /* Flush mtdoops.  */
166 #ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
167         reset_watchdog();
168 #endif
169         while(1) /* nothing */;
170 #endif
171 }
172 
173 extern void cris_profile_sample(struct pt_regs *regs);
174 static void __iomem *timer_base;
175 
176 static int crisv32_clkevt_switch_state(struct clock_event_device *dev)
177 {
178         reg_timer_rw_tmr0_ctrl ctrl = {
179                 .op = regk_timer_hold,
180                 .freq = regk_timer_f100,
181         };
182 
183         REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
184         return 0;
185 }
186 
187 static int crisv32_clkevt_next_event(unsigned long evt,
188                                      struct clock_event_device *dev)
189 {
190         reg_timer_rw_tmr0_ctrl ctrl = {
191                 .op = regk_timer_ld,
192                 .freq = regk_timer_f100,
193         };
194 
195         REG_WR(timer, timer_base, rw_tmr0_div, evt);
196         REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
197 
198         ctrl.op = regk_timer_run;
199         REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
200 
201         return 0;
202 }
203 
204 static irqreturn_t crisv32_timer_interrupt(int irq, void *dev_id)
205 {
206         struct clock_event_device *evt = dev_id;
207         reg_timer_rw_tmr0_ctrl ctrl = {
208                 .op = regk_timer_hold,
209                 .freq = regk_timer_f100,
210         };
211         reg_timer_rw_ack_intr ack = { .tmr0 = 1 };
212         reg_timer_r_masked_intr intr;
213 
214         intr = REG_RD(timer, timer_base, r_masked_intr);
215         if (!intr.tmr0)
216                 return IRQ_NONE;
217 
218         REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
219         REG_WR(timer, timer_base, rw_ack_intr, ack);
220 
221         reset_watchdog();
222 #ifdef CONFIG_SYSTEM_PROFILER
223         cris_profile_sample(get_irq_regs());
224 #endif
225 
226         evt->event_handler(evt);
227 
228         return IRQ_HANDLED;
229 }
230 
231 static struct clock_event_device crisv32_clockevent = {
232         .name = "crisv32-timer",
233         .rating = 300,
234         .features = CLOCK_EVT_FEAT_ONESHOT,
235         .set_state_oneshot = crisv32_clkevt_switch_state,
236         .set_state_shutdown = crisv32_clkevt_switch_state,
237         .tick_resume = crisv32_clkevt_switch_state,
238         .set_next_event = crisv32_clkevt_next_event,
239 };
240 
241 /* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */
242 static struct irqaction irq_timer = {
243         .handler = crisv32_timer_interrupt,
244         .flags = IRQF_TIMER | IRQF_SHARED,
245         .name = "crisv32-timer",
246         .dev_id = &crisv32_clockevent,
247 };
248 
249 static u64 notrace crisv32_timer_sched_clock(void)
250 {
251         return REG_RD(timer, timer_base, r_time);
252 }
253 
254 static void __init crisv32_timer_init(void)
255 {
256         reg_timer_rw_intr_mask timer_intr_mask;
257         reg_timer_rw_tmr0_ctrl ctrl = {
258                 .op = regk_timer_hold,
259                 .freq = regk_timer_f100,
260         };
261 
262         REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
263 
264         timer_intr_mask = REG_RD(timer, timer_base, rw_intr_mask);
265         timer_intr_mask.tmr0 = 1;
266         REG_WR(timer, timer_base, rw_intr_mask, timer_intr_mask);
267 }
268 
269 void __init time_init(void)
270 {
271         int irq;
272         int ret;
273 
274         /* Probe for the RTC and read it if it exists.
275          * Before the RTC can be probed the loops_per_usec variable needs
276          * to be initialized to make usleep work. A better value for
277          * loops_per_usec is calculated by the kernel later once the
278          * clock has started.
279          */
280         loops_per_usec = 50;
281 
282         irq = TIMER0_INTR_VECT;
283         timer_base = (void __iomem *) regi_timer0;
284 
285         crisv32_timer_init();
286 
287         sched_clock_register(crisv32_timer_sched_clock, 32,
288                              CRISV32_TIMER_FREQ);
289 
290         clocksource_mmio_init(timer_base + REG_RD_ADDR_timer_r_time,
291                               "crisv32-timer", CRISV32_TIMER_FREQ,
292                               300, 32, clocksource_mmio_readl_up);
293 
294         crisv32_clockevent.cpumask = cpu_possible_mask;
295         crisv32_clockevent.irq = irq;
296 
297         ret = setup_irq(irq, &irq_timer);
298         if (ret)
299                 pr_warn("failed to setup irq %d\n", irq);
300 
301         clockevents_config_and_register(&crisv32_clockevent,
302                                         CRISV32_TIMER_FREQ,
303                                         2, 0xffffffff);
304 
305         /* Enable watchdog if we should use one. */
306 
307 #if defined(CONFIG_ETRAX_WATCHDOG)
308         printk(KERN_INFO "Enabling watchdog...\n");
309         start_watchdog();
310 
311         /* If we use the hardware watchdog, we want to trap it as an NMI
312          * and dump registers before it resets us.  For this to happen, we
313          * must set the "m" NMI enable flag (which once set, is unset only
314          * when an NMI is taken). */
315         {
316                 unsigned long flags;
317                 local_save_flags(flags);
318                 flags |= (1<<30); /* NMI M flag is at bit 30 */
319                 local_irq_restore(flags);
320         }
321 #endif
322 
323 #ifdef CONFIG_CPU_FREQ
324         cpufreq_register_notifier(&cris_time_freq_notifier_block,
325                                   CPUFREQ_TRANSITION_NOTIFIER);
326 #endif
327 }
328 
329 #ifdef CONFIG_CPU_FREQ
330 static int cris_time_freq_notifier(struct notifier_block *nb,
331                                    unsigned long val, void *data)
332 {
333         struct cpufreq_freqs *freqs = data;
334         if (val == CPUFREQ_POSTCHANGE) {
335                 reg_timer_r_tmr0_data data;
336                 reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
337                 do {
338                         data = REG_RD(timer, timer_regs[freqs->cpu],
339                                 r_tmr0_data);
340                 } while (data > 20);
341                 REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
342         }
343         return 0;
344 }
345 #endif
346 

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