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Linux/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h

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  1 #ifndef __iop_crc_par_defs_h
  2 #define __iop_crc_par_defs_h
  3 
  4 /*
  5  * This file is autogenerated from
  6  *   file:           ../../inst/io_proc/rtl/iop_crc_par.r
  7  *     id:           <not found>
  8  *     last modfied: Mon Apr 11 16:08:45 2005
  9  *
 10  *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r
 11  *      id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
 12  * Any changes here will be lost.
 13  *
 14  * -*- buffer-read-only: t -*-
 15  */
 16 /* Main access macros */
 17 #ifndef REG_RD
 18 #define REG_RD( scope, inst, reg ) \
 19   REG_READ( reg_##scope##_##reg, \
 20             (inst) + REG_RD_ADDR_##scope##_##reg )
 21 #endif
 22 
 23 #ifndef REG_WR
 24 #define REG_WR( scope, inst, reg, val ) \
 25   REG_WRITE( reg_##scope##_##reg, \
 26              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
 27 #endif
 28 
 29 #ifndef REG_RD_VECT
 30 #define REG_RD_VECT( scope, inst, reg, index ) \
 31   REG_READ( reg_##scope##_##reg, \
 32             (inst) + REG_RD_ADDR_##scope##_##reg + \
 33             (index) * STRIDE_##scope##_##reg )
 34 #endif
 35 
 36 #ifndef REG_WR_VECT
 37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
 38   REG_WRITE( reg_##scope##_##reg, \
 39              (inst) + REG_WR_ADDR_##scope##_##reg + \
 40              (index) * STRIDE_##scope##_##reg, (val) )
 41 #endif
 42 
 43 #ifndef REG_RD_INT
 44 #define REG_RD_INT( scope, inst, reg ) \
 45   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
 46 #endif
 47 
 48 #ifndef REG_WR_INT
 49 #define REG_WR_INT( scope, inst, reg, val ) \
 50   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
 51 #endif
 52 
 53 #ifndef REG_RD_INT_VECT
 54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
 55   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
 56             (index) * STRIDE_##scope##_##reg )
 57 #endif
 58 
 59 #ifndef REG_WR_INT_VECT
 60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
 61   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
 62              (index) * STRIDE_##scope##_##reg, (val) )
 63 #endif
 64 
 65 #ifndef REG_TYPE_CONV
 66 #define REG_TYPE_CONV( type, orgtype, val ) \
 67   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
 68 #endif
 69 
 70 #ifndef reg_page_size
 71 #define reg_page_size 8192
 72 #endif
 73 
 74 #ifndef REG_ADDR
 75 #define REG_ADDR( scope, inst, reg ) \
 76   ( (inst) + REG_RD_ADDR_##scope##_##reg )
 77 #endif
 78 
 79 #ifndef REG_ADDR_VECT
 80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
 81   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
 82     (index) * STRIDE_##scope##_##reg )
 83 #endif
 84 
 85 /* C-code for register scope iop_crc_par */
 86 
 87 /* Register rw_cfg, scope iop_crc_par, type rw */
 88 typedef struct {
 89   unsigned int mode    : 1;
 90   unsigned int crc_out : 1;
 91   unsigned int rev_out : 1;
 92   unsigned int inv_out : 1;
 93   unsigned int trig    : 2;
 94   unsigned int poly    : 3;
 95   unsigned int dummy1  : 23;
 96 } reg_iop_crc_par_rw_cfg;
 97 #define REG_RD_ADDR_iop_crc_par_rw_cfg 0
 98 #define REG_WR_ADDR_iop_crc_par_rw_cfg 0
 99 
100 /* Register rw_init_crc, scope iop_crc_par, type rw */
101 typedef unsigned int reg_iop_crc_par_rw_init_crc;
102 #define REG_RD_ADDR_iop_crc_par_rw_init_crc 4
103 #define REG_WR_ADDR_iop_crc_par_rw_init_crc 4
104 
105 /* Register rw_correct_crc, scope iop_crc_par, type rw */
106 typedef unsigned int reg_iop_crc_par_rw_correct_crc;
107 #define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8
108 #define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8
109 
110 /* Register rw_ctrl, scope iop_crc_par, type rw */
111 typedef struct {
112   unsigned int en : 1;
113   unsigned int dummy1 : 31;
114 } reg_iop_crc_par_rw_ctrl;
115 #define REG_RD_ADDR_iop_crc_par_rw_ctrl 12
116 #define REG_WR_ADDR_iop_crc_par_rw_ctrl 12
117 
118 /* Register rw_set_last, scope iop_crc_par, type rw */
119 typedef struct {
120   unsigned int tr_dif : 1;
121   unsigned int dummy1 : 31;
122 } reg_iop_crc_par_rw_set_last;
123 #define REG_RD_ADDR_iop_crc_par_rw_set_last 16
124 #define REG_WR_ADDR_iop_crc_par_rw_set_last 16
125 
126 /* Register rw_wr1byte, scope iop_crc_par, type rw */
127 typedef struct {
128   unsigned int data : 8;
129   unsigned int dummy1 : 24;
130 } reg_iop_crc_par_rw_wr1byte;
131 #define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20
132 #define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20
133 
134 /* Register rw_wr2byte, scope iop_crc_par, type rw */
135 typedef struct {
136   unsigned int data : 16;
137   unsigned int dummy1 : 16;
138 } reg_iop_crc_par_rw_wr2byte;
139 #define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24
140 #define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24
141 
142 /* Register rw_wr3byte, scope iop_crc_par, type rw */
143 typedef struct {
144   unsigned int data : 24;
145   unsigned int dummy1 : 8;
146 } reg_iop_crc_par_rw_wr3byte;
147 #define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28
148 #define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28
149 
150 /* Register rw_wr4byte, scope iop_crc_par, type rw */
151 typedef struct {
152   unsigned int data : 32;
153 } reg_iop_crc_par_rw_wr4byte;
154 #define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32
155 #define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32
156 
157 /* Register rw_wr1byte_last, scope iop_crc_par, type rw */
158 typedef struct {
159   unsigned int data : 8;
160   unsigned int dummy1 : 24;
161 } reg_iop_crc_par_rw_wr1byte_last;
162 #define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36
163 #define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36
164 
165 /* Register rw_wr2byte_last, scope iop_crc_par, type rw */
166 typedef struct {
167   unsigned int data : 16;
168   unsigned int dummy1 : 16;
169 } reg_iop_crc_par_rw_wr2byte_last;
170 #define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40
171 #define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40
172 
173 /* Register rw_wr3byte_last, scope iop_crc_par, type rw */
174 typedef struct {
175   unsigned int data : 24;
176   unsigned int dummy1 : 8;
177 } reg_iop_crc_par_rw_wr3byte_last;
178 #define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44
179 #define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44
180 
181 /* Register rw_wr4byte_last, scope iop_crc_par, type rw */
182 typedef struct {
183   unsigned int data : 32;
184 } reg_iop_crc_par_rw_wr4byte_last;
185 #define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48
186 #define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48
187 
188 /* Register r_stat, scope iop_crc_par, type r */
189 typedef struct {
190   unsigned int err  : 1;
191   unsigned int busy : 1;
192   unsigned int dummy1 : 30;
193 } reg_iop_crc_par_r_stat;
194 #define REG_RD_ADDR_iop_crc_par_r_stat 52
195 
196 /* Register r_sh_reg, scope iop_crc_par, type r */
197 typedef unsigned int reg_iop_crc_par_r_sh_reg;
198 #define REG_RD_ADDR_iop_crc_par_r_sh_reg 56
199 
200 /* Register r_crc, scope iop_crc_par, type r */
201 typedef unsigned int reg_iop_crc_par_r_crc;
202 #define REG_RD_ADDR_iop_crc_par_r_crc 60
203 
204 /* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
205 typedef struct {
206   unsigned int last : 2;
207   unsigned int dummy1 : 30;
208 } reg_iop_crc_par_rw_strb_rec_dif_in;
209 #define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
210 #define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
211 
212 
213 /* Constants */
214 enum {
215   regk_iop_crc_par_calc                    = 0x00000001,
216   regk_iop_crc_par_ccitt                   = 0x00000002,
217   regk_iop_crc_par_check                   = 0x00000000,
218   regk_iop_crc_par_crc16                   = 0x00000001,
219   regk_iop_crc_par_crc32                   = 0x00000000,
220   regk_iop_crc_par_crc5                    = 0x00000003,
221   regk_iop_crc_par_crc5_11                 = 0x00000004,
222   regk_iop_crc_par_dif_in                  = 0x00000002,
223   regk_iop_crc_par_hi                      = 0x00000000,
224   regk_iop_crc_par_neg                     = 0x00000002,
225   regk_iop_crc_par_no                      = 0x00000000,
226   regk_iop_crc_par_pos                     = 0x00000001,
227   regk_iop_crc_par_pos_neg                 = 0x00000003,
228   regk_iop_crc_par_rw_cfg_default          = 0x00000000,
229   regk_iop_crc_par_rw_ctrl_default         = 0x00000000,
230   regk_iop_crc_par_yes                     = 0x00000001
231 };
232 #endif /* __iop_crc_par_defs_h */
233 

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