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Linux/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h

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  1 #ifndef __timer_defs_h
  2 #define __timer_defs_h
  3 
  4 /*
  5  * This file is autogenerated from
  6  *   file:           timer.r
  7  * 
  8  *   by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r
  9  * Any changes here will be lost.
 10  *
 11  * -*- buffer-read-only: t -*-
 12  */
 13 /* Main access macros */
 14 #ifndef REG_RD
 15 #define REG_RD( scope, inst, reg ) \
 16   REG_READ( reg_##scope##_##reg, \
 17             (inst) + REG_RD_ADDR_##scope##_##reg )
 18 #endif
 19 
 20 #ifndef REG_WR
 21 #define REG_WR( scope, inst, reg, val ) \
 22   REG_WRITE( reg_##scope##_##reg, \
 23              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
 24 #endif
 25 
 26 #ifndef REG_RD_VECT
 27 #define REG_RD_VECT( scope, inst, reg, index ) \
 28   REG_READ( reg_##scope##_##reg, \
 29             (inst) + REG_RD_ADDR_##scope##_##reg + \
 30             (index) * STRIDE_##scope##_##reg )
 31 #endif
 32 
 33 #ifndef REG_WR_VECT
 34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
 35   REG_WRITE( reg_##scope##_##reg, \
 36              (inst) + REG_WR_ADDR_##scope##_##reg + \
 37              (index) * STRIDE_##scope##_##reg, (val) )
 38 #endif
 39 
 40 #ifndef REG_RD_INT
 41 #define REG_RD_INT( scope, inst, reg ) \
 42   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
 43 #endif
 44 
 45 #ifndef REG_WR_INT
 46 #define REG_WR_INT( scope, inst, reg, val ) \
 47   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
 48 #endif
 49 
 50 #ifndef REG_RD_INT_VECT
 51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
 52   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
 53             (index) * STRIDE_##scope##_##reg )
 54 #endif
 55 
 56 #ifndef REG_WR_INT_VECT
 57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
 58   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
 59              (index) * STRIDE_##scope##_##reg, (val) )
 60 #endif
 61 
 62 #ifndef REG_TYPE_CONV
 63 #define REG_TYPE_CONV( type, orgtype, val ) \
 64   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
 65 #endif
 66 
 67 #ifndef reg_page_size
 68 #define reg_page_size 8192
 69 #endif
 70 
 71 #ifndef REG_ADDR
 72 #define REG_ADDR( scope, inst, reg ) \
 73   ( (inst) + REG_RD_ADDR_##scope##_##reg )
 74 #endif
 75 
 76 #ifndef REG_ADDR_VECT
 77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
 78   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
 79     (index) * STRIDE_##scope##_##reg )
 80 #endif
 81 
 82 /* C-code for register scope timer */
 83 
 84 /* Register rw_tmr0_div, scope timer, type rw */
 85 typedef unsigned int reg_timer_rw_tmr0_div;
 86 #define REG_RD_ADDR_timer_rw_tmr0_div 0
 87 #define REG_WR_ADDR_timer_rw_tmr0_div 0
 88 
 89 /* Register r_tmr0_data, scope timer, type r */
 90 typedef unsigned int reg_timer_r_tmr0_data;
 91 #define REG_RD_ADDR_timer_r_tmr0_data 4
 92 
 93 /* Register rw_tmr0_ctrl, scope timer, type rw */
 94 typedef struct {
 95   unsigned int op   : 2;
 96   unsigned int freq : 3;
 97   unsigned int dummy1 : 27;
 98 } reg_timer_rw_tmr0_ctrl;
 99 #define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
100 #define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
101 
102 /* Register rw_tmr1_div, scope timer, type rw */
103 typedef unsigned int reg_timer_rw_tmr1_div;
104 #define REG_RD_ADDR_timer_rw_tmr1_div 16
105 #define REG_WR_ADDR_timer_rw_tmr1_div 16
106 
107 /* Register r_tmr1_data, scope timer, type r */
108 typedef unsigned int reg_timer_r_tmr1_data;
109 #define REG_RD_ADDR_timer_r_tmr1_data 20
110 
111 /* Register rw_tmr1_ctrl, scope timer, type rw */
112 typedef struct {
113   unsigned int op   : 2;
114   unsigned int freq : 3;
115   unsigned int dummy1 : 27;
116 } reg_timer_rw_tmr1_ctrl;
117 #define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
118 #define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
119 
120 /* Register rs_cnt_data, scope timer, type rs */
121 typedef struct {
122   unsigned int tmr : 24;
123   unsigned int cnt : 8;
124 } reg_timer_rs_cnt_data;
125 #define REG_RD_ADDR_timer_rs_cnt_data 32
126 
127 /* Register r_cnt_data, scope timer, type r */
128 typedef struct {
129   unsigned int tmr : 24;
130   unsigned int cnt : 8;
131 } reg_timer_r_cnt_data;
132 #define REG_RD_ADDR_timer_r_cnt_data 36
133 
134 /* Register rw_cnt_cfg, scope timer, type rw */
135 typedef struct {
136   unsigned int clk : 2;
137   unsigned int dummy1 : 30;
138 } reg_timer_rw_cnt_cfg;
139 #define REG_RD_ADDR_timer_rw_cnt_cfg 40
140 #define REG_WR_ADDR_timer_rw_cnt_cfg 40
141 
142 /* Register rw_trig, scope timer, type rw */
143 typedef unsigned int reg_timer_rw_trig;
144 #define REG_RD_ADDR_timer_rw_trig 48
145 #define REG_WR_ADDR_timer_rw_trig 48
146 
147 /* Register rw_trig_cfg, scope timer, type rw */
148 typedef struct {
149   unsigned int tmr : 2;
150   unsigned int dummy1 : 30;
151 } reg_timer_rw_trig_cfg;
152 #define REG_RD_ADDR_timer_rw_trig_cfg 52
153 #define REG_WR_ADDR_timer_rw_trig_cfg 52
154 
155 /* Register r_time, scope timer, type r */
156 typedef unsigned int reg_timer_r_time;
157 #define REG_RD_ADDR_timer_r_time 56
158 
159 /* Register rw_out, scope timer, type rw */
160 typedef struct {
161   unsigned int tmr : 2;
162   unsigned int dummy1 : 30;
163 } reg_timer_rw_out;
164 #define REG_RD_ADDR_timer_rw_out 60
165 #define REG_WR_ADDR_timer_rw_out 60
166 
167 /* Register rw_wd_ctrl, scope timer, type rw */
168 typedef struct {
169   unsigned int cnt : 8;
170   unsigned int cmd : 1;
171   unsigned int key : 7;
172   unsigned int dummy1 : 16;
173 } reg_timer_rw_wd_ctrl;
174 #define REG_RD_ADDR_timer_rw_wd_ctrl 64
175 #define REG_WR_ADDR_timer_rw_wd_ctrl 64
176 
177 /* Register r_wd_stat, scope timer, type r */
178 typedef struct {
179   unsigned int cnt : 8;
180   unsigned int cmd : 1;
181   unsigned int dummy1 : 23;
182 } reg_timer_r_wd_stat;
183 #define REG_RD_ADDR_timer_r_wd_stat 68
184 
185 /* Register rw_intr_mask, scope timer, type rw */
186 typedef struct {
187   unsigned int tmr0 : 1;
188   unsigned int tmr1 : 1;
189   unsigned int cnt  : 1;
190   unsigned int trig : 1;
191   unsigned int dummy1 : 28;
192 } reg_timer_rw_intr_mask;
193 #define REG_RD_ADDR_timer_rw_intr_mask 72
194 #define REG_WR_ADDR_timer_rw_intr_mask 72
195 
196 /* Register rw_ack_intr, scope timer, type rw */
197 typedef struct {
198   unsigned int tmr0 : 1;
199   unsigned int tmr1 : 1;
200   unsigned int cnt  : 1;
201   unsigned int trig : 1;
202   unsigned int dummy1 : 28;
203 } reg_timer_rw_ack_intr;
204 #define REG_RD_ADDR_timer_rw_ack_intr 76
205 #define REG_WR_ADDR_timer_rw_ack_intr 76
206 
207 /* Register r_intr, scope timer, type r */
208 typedef struct {
209   unsigned int tmr0 : 1;
210   unsigned int tmr1 : 1;
211   unsigned int cnt  : 1;
212   unsigned int trig : 1;
213   unsigned int dummy1 : 28;
214 } reg_timer_r_intr;
215 #define REG_RD_ADDR_timer_r_intr 80
216 
217 /* Register r_masked_intr, scope timer, type r */
218 typedef struct {
219   unsigned int tmr0 : 1;
220   unsigned int tmr1 : 1;
221   unsigned int cnt  : 1;
222   unsigned int trig : 1;
223   unsigned int dummy1 : 28;
224 } reg_timer_r_masked_intr;
225 #define REG_RD_ADDR_timer_r_masked_intr 84
226 
227 /* Register rw_test, scope timer, type rw */
228 typedef struct {
229   unsigned int dis : 1;
230   unsigned int en  : 1;
231   unsigned int dummy1 : 30;
232 } reg_timer_rw_test;
233 #define REG_RD_ADDR_timer_rw_test 88
234 #define REG_WR_ADDR_timer_rw_test 88
235 
236 
237 /* Constants */
238 enum {
239   regk_timer_ext                           = 0x00000001,
240   regk_timer_f100                          = 0x00000007,
241   regk_timer_f29_493                       = 0x00000004,
242   regk_timer_f32                           = 0x00000005,
243   regk_timer_f32_768                       = 0x00000006,
244   regk_timer_f90                           = 0x00000003,
245   regk_timer_hold                          = 0x00000001,
246   regk_timer_ld                            = 0x00000000,
247   regk_timer_no                            = 0x00000000,
248   regk_timer_off                           = 0x00000000,
249   regk_timer_run                           = 0x00000002,
250   regk_timer_rw_cnt_cfg_default            = 0x00000000,
251   regk_timer_rw_intr_mask_default          = 0x00000000,
252   regk_timer_rw_out_default                = 0x00000000,
253   regk_timer_rw_test_default               = 0x00000000,
254   regk_timer_rw_tmr0_ctrl_default          = 0x00000000,
255   regk_timer_rw_tmr1_ctrl_default          = 0x00000000,
256   regk_timer_rw_trig_cfg_default           = 0x00000000,
257   regk_timer_start                         = 0x00000001,
258   regk_timer_stop                          = 0x00000000,
259   regk_timer_time                          = 0x00000001,
260   regk_timer_tmr0                          = 0x00000002,
261   regk_timer_tmr1                          = 0x00000003,
262   regk_timer_vclk                          = 0x00000002,
263   regk_timer_yes                           = 0x00000001
264 };
265 #endif /* __timer_defs_h */
266 

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