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TOMOYO Linux Cross Reference
Linux/arch/frv/kernel/setup.c

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /* setup.c: FRV specific setup
  2  *
  3  * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
  4  * Written by David Howells (dhowells@redhat.com)
  5  * - Derived from arch/m68k/kernel/setup.c
  6  *
  7  * This program is free software; you can redistribute it and/or
  8  * modify it under the terms of the GNU General Public License
  9  * as published by the Free Software Foundation; either version
 10  * 2 of the License, or (at your option) any later version.
 11  */
 12 
 13 #include <generated/utsrelease.h>
 14 #include <linux/kernel.h>
 15 #include <linux/sched.h>
 16 #include <linux/delay.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/fs.h>
 19 #include <linux/mm.h>
 20 #include <linux/fb.h>
 21 #include <linux/console.h>
 22 #include <linux/genhd.h>
 23 #include <linux/errno.h>
 24 #include <linux/string.h>
 25 #include <linux/major.h>
 26 #include <linux/bootmem.h>
 27 #include <linux/highmem.h>
 28 #include <linux/seq_file.h>
 29 #include <linux/serial.h>
 30 #include <linux/serial_core.h>
 31 #include <linux/serial_reg.h>
 32 #include <linux/serial_8250.h>
 33 
 34 #include <asm/setup.h>
 35 #include <asm/irq.h>
 36 #include <asm/sections.h>
 37 #include <asm/pgalloc.h>
 38 #include <asm/busctl-regs.h>
 39 #include <asm/serial-regs.h>
 40 #include <asm/timer-regs.h>
 41 #include <asm/irc-regs.h>
 42 #include <asm/spr-regs.h>
 43 #include <asm/mb-regs.h>
 44 #include <asm/mb93493-regs.h>
 45 #include <asm/gdb-stub.h>
 46 #include <asm/io.h>
 47 
 48 #ifdef CONFIG_BLK_DEV_INITRD
 49 #include <asm/pgtable.h>
 50 #endif
 51 
 52 #include "local.h"
 53 
 54 #ifdef CONFIG_MB93090_MB00
 55 static void __init mb93090_display(void);
 56 #endif
 57 #ifdef CONFIG_MMU
 58 static void __init setup_linux_memory(void);
 59 #else
 60 static void __init setup_uclinux_memory(void);
 61 #endif
 62 
 63 #ifdef CONFIG_MB93090_MB00
 64 static char __initdata mb93090_banner[] = "FJ/RH FR-V Linux";
 65 static char __initdata mb93090_version[] = UTS_RELEASE;
 66 
 67 int __nongprelbss mb93090_mb00_detected;
 68 #endif
 69 
 70 const char __frv_unknown_system[] = "unknown";
 71 const char __frv_mb93091_cb10[] = "mb93091-cb10";
 72 const char __frv_mb93091_cb11[] = "mb93091-cb11";
 73 const char __frv_mb93091_cb30[] = "mb93091-cb30";
 74 const char __frv_mb93091_cb41[] = "mb93091-cb41";
 75 const char __frv_mb93091_cb60[] = "mb93091-cb60";
 76 const char __frv_mb93091_cb70[] = "mb93091-cb70";
 77 const char __frv_mb93091_cb451[] = "mb93091-cb451";
 78 const char __frv_mb93090_mb00[] = "mb93090-mb00";
 79 
 80 const char __frv_mb93493[] = "mb93493";
 81 
 82 const char __frv_mb93093[] = "mb93093";
 83 
 84 static const char *__nongprelbss cpu_series;
 85 static const char *__nongprelbss cpu_core;
 86 static const char *__nongprelbss cpu_silicon;
 87 static const char *__nongprelbss cpu_mmu;
 88 static const char *__nongprelbss cpu_system;
 89 static const char *__nongprelbss cpu_board1;
 90 static const char *__nongprelbss cpu_board2;
 91 
 92 static unsigned long __nongprelbss cpu_psr_all;
 93 static unsigned long __nongprelbss cpu_hsr0_all;
 94 
 95 unsigned long __nongprelbss pdm_suspend_mode;
 96 
 97 unsigned long __nongprelbss rom_length;
 98 unsigned long __nongprelbss memory_start;
 99 unsigned long __nongprelbss memory_end;
100 
101 unsigned long __nongprelbss dma_coherent_mem_start;
102 unsigned long __nongprelbss dma_coherent_mem_end;
103 
104 unsigned long __initdata __sdram_old_base;
105 unsigned long __initdata num_mappedpages;
106 
107 struct cpuinfo_frv __nongprelbss boot_cpu_data;
108 
109 char __initdata command_line[COMMAND_LINE_SIZE];
110 char __initdata redboot_command_line[COMMAND_LINE_SIZE];
111 
112 #ifdef CONFIG_PM
113 #define __pminit
114 #define __pminitdata
115 #else
116 #define __pminit __init
117 #define __pminitdata __initdata
118 #endif
119 
120 struct clock_cmode {
121         uint8_t xbus, sdram, corebus, core, dsu;
122 };
123 
124 #define _frac(N,D) ((N)<<4 | (D))
125 #define _x0_16  _frac(1,6)
126 #define _x0_25  _frac(1,4)
127 #define _x0_33  _frac(1,3)
128 #define _x0_375 _frac(3,8)
129 #define _x0_5   _frac(1,2)
130 #define _x0_66  _frac(2,3)
131 #define _x0_75  _frac(3,4)
132 #define _x1     _frac(1,1)
133 #define _x1_5   _frac(3,2)
134 #define _x2     _frac(2,1)
135 #define _x3     _frac(3,1)
136 #define _x4     _frac(4,1)
137 #define _x4_5   _frac(9,2)
138 #define _x6     _frac(6,1)
139 #define _x8     _frac(8,1)
140 #define _x9     _frac(9,1)
141 
142 int __nongprelbss clock_p0_current;
143 int __nongprelbss clock_cm_current;
144 int __nongprelbss clock_cmode_current;
145 #ifdef CONFIG_PM
146 int __nongprelbss clock_cmodes_permitted;
147 unsigned long __nongprelbss clock_bits_settable;
148 #endif
149 
150 static struct clock_cmode __pminitdata undef_clock_cmode = { _x1, _x1, _x1, _x1, _x1 };
151 
152 static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403[16] = {
153         [4]     = {     _x1,    _x1,    _x2,    _x2,    _x0_25  },
154         [5]     = {     _x1,    _x2,    _x4,    _x4,    _x0_5   },
155         [8]     = {     _x1,    _x1,    _x1,    _x2,    _x0_25  },
156         [9]     = {     _x1,    _x2,    _x2,    _x4,    _x0_5   },
157         [11]    = {     _x1,    _x4,    _x4,    _x8,    _x1     },
158         [12]    = {     _x1,    _x1,    _x2,    _x4,    _x0_5   },
159         [13]    = {     _x1,    _x2,    _x4,    _x8,    _x1     },
160 };
161 
162 static struct clock_cmode __pminitdata clock_cmodes_fr405[16] = {
163         [0]     = {     _x1,    _x1,    _x1,    _x1,    _x0_5   },
164         [1]     = {     _x1,    _x1,    _x1,    _x3,    _x0_25  },
165         [2]     = {     _x1,    _x1,    _x2,    _x6,    _x0_5   },
166         [3]     = {     _x1,    _x2,    _x2,    _x6,    _x0_5   },
167         [4]     = {     _x1,    _x1,    _x2,    _x2,    _x0_16  },
168         [8]     = {     _x1,    _x1,    _x1,    _x2,    _x0_16  },
169         [9]     = {     _x1,    _x2,    _x2,    _x4,    _x0_33  },
170         [12]    = {     _x1,    _x1,    _x2,    _x4,    _x0_33  },
171         [14]    = {     _x1,    _x3,    _x3,    _x9,    _x0_75  },
172         [15]    = {     _x1,    _x1_5,  _x1_5,  _x4_5,  _x0_375 },
173 
174 #define CLOCK_CMODES_PERMITTED_FR405 0xd31f
175 };
176 
177 static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = {
178         [0]     = {     _x1,    _x2,    _x2,    _x4,    _x0_33  },
179         [1]     = {     _x1,    _x3,    _x3,    _x6,    _x0_5   },
180         [2]     = {     _x1,    _x2,    _x4,    _x8,    _x0_66  },
181         [3]     = {     _x1,    _x1_5,  _x3,    _x6,    _x0_5   },
182         [4]     = {     _x1,    _x3,    _x3,    _x9,    _x0_75  },
183         [5]     = {     _x1,    _x2,    _x2,    _x6,    _x0_5   },
184         [6]     = {     _x1,    _x1_5,  _x1_5,  _x4_5,  _x0_375 },
185 };
186 
187 static const struct clock_cmode __pminitdata *clock_cmodes;
188 static int __pminitdata clock_doubled;
189 
190 static struct uart_port __pminitdata __frv_uart0 = {
191         .uartclk                = 0,
192         .membase                = (char *) UART0_BASE,
193         .irq                    = IRQ_CPU_UART0,
194         .regshift               = 3,
195         .iotype                 = UPIO_MEM,
196         .flags                  = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
197 };
198 
199 static struct uart_port __pminitdata __frv_uart1 = {
200         .uartclk                = 0,
201         .membase                = (char *) UART1_BASE,
202         .irq                    = IRQ_CPU_UART1,
203         .regshift               = 3,
204         .iotype                 = UPIO_MEM,
205         .flags                  = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
206 };
207 
208 #if 0
209 static void __init printk_xampr(unsigned long ampr, unsigned long amlr, char i_d, int n)
210 {
211         unsigned long phys, virt, cxn, size;
212 
213 #ifdef CONFIG_MMU
214         virt = amlr & 0xffffc000;
215         cxn = amlr & 0x3fff;
216 #else
217         virt = ampr & 0xffffc000;
218         cxn = 0;
219 #endif
220         phys = ampr & xAMPRx_PPFN;
221         size = 1 << (((ampr & xAMPRx_SS) >> 4) + 17);
222 
223         printk("%cAMPR%d: va %08lx-%08lx [pa %08lx] %c%c%c%c [cxn:%04lx]\n",
224                i_d, n,
225                virt, virt + size - 1,
226                phys,
227                ampr & xAMPRx_S  ? 'S' : '-',
228                ampr & xAMPRx_C  ? 'C' : '-',
229                ampr & DAMPRx_WP ? 'W' : '-',
230                ampr & xAMPRx_V  ? 'V' : '-',
231                cxn
232                );
233 }
234 #endif
235 
236 /*****************************************************************************/
237 /*
238  * dump the memory map
239  */
240 static void __init dump_memory_map(void)
241 {
242 
243 #if 0
244         /* dump the protection map */
245         printk_xampr(__get_IAMPR(0),  __get_IAMLR(0),  'I', 0);
246         printk_xampr(__get_IAMPR(1),  __get_IAMLR(1),  'I', 1);
247         printk_xampr(__get_IAMPR(2),  __get_IAMLR(2),  'I', 2);
248         printk_xampr(__get_IAMPR(3),  __get_IAMLR(3),  'I', 3);
249         printk_xampr(__get_IAMPR(4),  __get_IAMLR(4),  'I', 4);
250         printk_xampr(__get_IAMPR(5),  __get_IAMLR(5),  'I', 5);
251         printk_xampr(__get_IAMPR(6),  __get_IAMLR(6),  'I', 6);
252         printk_xampr(__get_IAMPR(7),  __get_IAMLR(7),  'I', 7);
253         printk_xampr(__get_IAMPR(8),  __get_IAMLR(8),  'I', 8);
254         printk_xampr(__get_IAMPR(9),  __get_IAMLR(9),  'i', 9);
255         printk_xampr(__get_IAMPR(10), __get_IAMLR(10), 'I', 10);
256         printk_xampr(__get_IAMPR(11), __get_IAMLR(11), 'I', 11);
257         printk_xampr(__get_IAMPR(12), __get_IAMLR(12), 'I', 12);
258         printk_xampr(__get_IAMPR(13), __get_IAMLR(13), 'I', 13);
259         printk_xampr(__get_IAMPR(14), __get_IAMLR(14), 'I', 14);
260         printk_xampr(__get_IAMPR(15), __get_IAMLR(15), 'I', 15);
261 
262         printk_xampr(__get_DAMPR(0),  __get_DAMLR(0),  'D', 0);
263         printk_xampr(__get_DAMPR(1),  __get_DAMLR(1),  'D', 1);
264         printk_xampr(__get_DAMPR(2),  __get_DAMLR(2),  'D', 2);
265         printk_xampr(__get_DAMPR(3),  __get_DAMLR(3),  'D', 3);
266         printk_xampr(__get_DAMPR(4),  __get_DAMLR(4),  'D', 4);
267         printk_xampr(__get_DAMPR(5),  __get_DAMLR(5),  'D', 5);
268         printk_xampr(__get_DAMPR(6),  __get_DAMLR(6),  'D', 6);
269         printk_xampr(__get_DAMPR(7),  __get_DAMLR(7),  'D', 7);
270         printk_xampr(__get_DAMPR(8),  __get_DAMLR(8),  'D', 8);
271         printk_xampr(__get_DAMPR(9),  __get_DAMLR(9),  'D', 9);
272         printk_xampr(__get_DAMPR(10), __get_DAMLR(10), 'D', 10);
273         printk_xampr(__get_DAMPR(11), __get_DAMLR(11), 'D', 11);
274         printk_xampr(__get_DAMPR(12), __get_DAMLR(12), 'D', 12);
275         printk_xampr(__get_DAMPR(13), __get_DAMLR(13), 'D', 13);
276         printk_xampr(__get_DAMPR(14), __get_DAMLR(14), 'D', 14);
277         printk_xampr(__get_DAMPR(15), __get_DAMLR(15), 'D', 15);
278 #endif
279 
280 #if 0
281         /* dump the bus controller registers */
282         printk("LGCR: %08lx\n", __get_LGCR());
283         printk("Master: %08lx-%08lx CR=%08lx\n",
284                __get_LEMBR(), __get_LEMBR() + __get_LEMAM(),
285                __get_LMAICR());
286 
287         int loop;
288         for (loop = 1; loop <= 7; loop++) {
289                 unsigned long lcr = __get_LCR(loop), lsbr = __get_LSBR(loop);
290                 printk("CS#%d: %08lx-%08lx %c%c%c%c%c%c%c%c%c\n",
291                        loop,
292                        lsbr, lsbr + __get_LSAM(loop),
293                        lcr & 0x80000000 ? 'r' : '-',
294                        lcr & 0x40000000 ? 'w' : '-',
295                        lcr & 0x08000000 ? 'b' : '-',
296                        lcr & 0x04000000 ? 'B' : '-',
297                        lcr & 0x02000000 ? 'C' : '-',
298                        lcr & 0x01000000 ? 'D' : '-',
299                        lcr & 0x00800000 ? 'W' : '-',
300                        lcr & 0x00400000 ? 'R' : '-',
301                        (lcr & 0x00030000) == 0x00000000 ? '4' :
302                        (lcr & 0x00030000) == 0x00010000 ? '2' :
303                        (lcr & 0x00030000) == 0x00020000 ? '1' :
304                        '-'
305                        );
306         }
307 #endif
308 
309 #if 0
310         printk("\n");
311 #endif
312 } /* end dump_memory_map() */
313 
314 /*****************************************************************************/
315 /*
316  * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system
317  */
318 #ifdef CONFIG_MB93091_VDK
319 static void __init detect_mb93091(void)
320 {
321 #ifdef CONFIG_MB93090_MB00
322         /* Detect CB70 without motherboard */
323         if (!(cpu_system == __frv_mb93091_cb70 && ((*(unsigned short *)0xffc00030) & 0x100))) {
324                 cpu_board1 = __frv_mb93090_mb00;
325                 mb93090_mb00_detected = 1;
326         }
327 #endif
328 
329 #ifdef CONFIG_FUJITSU_MB93493
330         cpu_board2 = __frv_mb93493;
331 #endif
332 
333 } /* end detect_mb93091() */
334 #endif
335 
336 /*****************************************************************************/
337 /*
338  * determine the CPU type and set appropriate parameters
339  *
340  * Family     Series      CPU Core    Silicon    Imple  Vers
341  * ----------------------------------------------------------
342  * FR-V --+-> FR400 --+-> FR401 --+-> MB93401     02     00 [1]
343  *        |           |           |
344  *        |           |           +-> MB93401/A   02     01
345  *        |           |           |
346  *        |           |           +-> MB93403     02     02
347  *        |           |
348  *        |           +-> FR405 ----> MB93405     04     00
349  *        |
350  *        +-> FR450 ----> FR451 ----> MB93451     05     00
351  *        |
352  *        +-> FR500 ----> FR501 --+-> MB93501     01     01 [2]
353  *        |                       |
354  *        |                       +-> MB93501/A   01     02
355  *        |
356  *        +-> FR550 --+-> FR551 ----> MB93555     03     01
357  *
358  *  [1] The MB93401 is an obsolete CPU replaced by the MB93401A
359  *  [2] The MB93501 is an obsolete CPU replaced by the MB93501A
360  *
361  * Imple is PSR(Processor Status Register)[31:28].
362  * Vers is PSR(Processor Status Register)[27:24].
363  *
364  * A "Silicon" consists of CPU core and some on-chip peripherals.
365  */
366 static void __init determine_cpu(void)
367 {
368         unsigned long hsr0 = __get_HSR(0);
369         unsigned long psr = __get_PSR();
370 
371         /* work out what selectable services the CPU supports */
372         __set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM);
373         cpu_psr_all = __get_PSR();
374         __set_PSR(psr);
375 
376         __set_HSR(0, hsr0 | HSR0_GRLE | HSR0_GRHE | HSR0_FRLE | HSR0_FRHE);
377         cpu_hsr0_all = __get_HSR(0);
378         __set_HSR(0, hsr0);
379 
380         /* derive other service specs from the CPU type */
381         cpu_series              = "unknown";
382         cpu_core                = "unknown";
383         cpu_silicon             = "unknown";
384         cpu_mmu                 = "Prot";
385         cpu_system              = __frv_unknown_system;
386         clock_cmodes            = NULL;
387         clock_doubled           = 0;
388 #ifdef CONFIG_PM
389         clock_bits_settable     = CLOCK_BIT_CM_H | CLOCK_BIT_CM_M | CLOCK_BIT_P0;
390 #endif
391 
392         switch (PSR_IMPLE(psr)) {
393         case PSR_IMPLE_FR401:
394                 cpu_series      = "fr400";
395                 cpu_core        = "fr401";
396                 pdm_suspend_mode = HSR0_PDM_PLL_RUN;
397 
398                 switch (PSR_VERSION(psr)) {
399                 case PSR_VERSION_FR401_MB93401:
400                         cpu_silicon     = "mb93401";
401                         cpu_system      = __frv_mb93091_cb10;
402                         clock_cmodes    = clock_cmodes_fr401_fr403;
403                         clock_doubled   = 1;
404                         break;
405                 case PSR_VERSION_FR401_MB93401A:
406                         cpu_silicon     = "mb93401/A";
407                         cpu_system      = __frv_mb93091_cb11;
408                         clock_cmodes    = clock_cmodes_fr401_fr403;
409                         break;
410                 case PSR_VERSION_FR401_MB93403:
411                         cpu_silicon     = "mb93403";
412 #ifndef CONFIG_MB93093_PDK
413                         cpu_system      = __frv_mb93091_cb30;
414 #else
415                         cpu_system      = __frv_mb93093;
416 #endif
417                         clock_cmodes    = clock_cmodes_fr401_fr403;
418                         break;
419                 default:
420                         break;
421                 }
422                 break;
423 
424         case PSR_IMPLE_FR405:
425                 cpu_series      = "fr400";
426                 cpu_core        = "fr405";
427                 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
428 
429                 switch (PSR_VERSION(psr)) {
430                 case PSR_VERSION_FR405_MB93405:
431                         cpu_silicon     = "mb93405";
432                         cpu_system      = __frv_mb93091_cb60;
433                         clock_cmodes    = clock_cmodes_fr405;
434 #ifdef CONFIG_PM
435                         clock_bits_settable |= CLOCK_BIT_CMODE;
436                         clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
437 #endif
438 
439                         /* the FPGA on the CB70 has extra registers
440                          * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
441                          *   how we tell the difference between it and a CB60
442                          */
443                         if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
444                                 cpu_system = __frv_mb93091_cb70;
445                         break;
446                 default:
447                         break;
448                 }
449                 break;
450 
451         case PSR_IMPLE_FR451:
452                 cpu_series      = "fr450";
453                 cpu_core        = "fr451";
454                 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
455 #ifdef CONFIG_PM
456                 clock_bits_settable |= CLOCK_BIT_CMODE;
457                 clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
458 #endif
459                 switch (PSR_VERSION(psr)) {
460                 case PSR_VERSION_FR451_MB93451:
461                         cpu_silicon     = "mb93451";
462                         cpu_mmu         = "Prot, SAT, xSAT, DAT";
463                         cpu_system      = __frv_mb93091_cb451;
464                         clock_cmodes    = clock_cmodes_fr405;
465                         break;
466                 default:
467                         break;
468                 }
469                 break;
470 
471         case PSR_IMPLE_FR501:
472                 cpu_series      = "fr500";
473                 cpu_core        = "fr501";
474                 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
475 
476                 switch (PSR_VERSION(psr)) {
477                 case PSR_VERSION_FR501_MB93501:  cpu_silicon = "mb93501";   break;
478                 case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break;
479                 default:
480                         break;
481                 }
482                 break;
483 
484         case PSR_IMPLE_FR551:
485                 cpu_series      = "fr550";
486                 cpu_core        = "fr551";
487                 pdm_suspend_mode = HSR0_PDM_PLL_RUN;
488 
489                 switch (PSR_VERSION(psr)) {
490                 case PSR_VERSION_FR551_MB93555:
491                         cpu_silicon     = "mb93555";
492                         cpu_mmu         = "Prot, SAT";
493                         cpu_system      = __frv_mb93091_cb41;
494                         clock_cmodes    = clock_cmodes_fr555;
495                         clock_doubled   = 1;
496                         break;
497                 default:
498                         break;
499                 }
500                 break;
501 
502         default:
503                 break;
504         }
505 
506         printk("- Series:%s CPU:%s Silicon:%s\n",
507                cpu_series, cpu_core, cpu_silicon);
508 
509 #ifdef CONFIG_MB93091_VDK
510         detect_mb93091();
511 #endif
512 
513 #if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
514         cpu_board2 = __frv_mb93493;
515 #endif
516 
517 } /* end determine_cpu() */
518 
519 /*****************************************************************************/
520 /*
521  * calculate the bus clock speed
522  */
523 void __pminit determine_clocks(int verbose)
524 {
525         const struct clock_cmode *mode, *tmode;
526         unsigned long clkc, psr, quot;
527 
528         clkc = __get_CLKC();
529         psr = __get_PSR();
530 
531         clock_p0_current = !!(clkc & CLKC_P0);
532         clock_cm_current = clkc & CLKC_CM;
533         clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s;
534 
535         if (verbose)
536                 printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc);
537 
538         /* the CB70 has some alternative ways of setting the clock speed through switches accessed
539          * through the FPGA.  */
540         if (cpu_system == __frv_mb93091_cb70) {
541                 unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
542 
543                 if (clkswr & 0x1000)
544                         __clkin_clock_speed_HZ = 60000000UL;
545                 else
546                         __clkin_clock_speed_HZ =
547                                 ((clkswr >> 8) & 0xf) * 10000000 +
548                                 ((clkswr >> 4) & 0xf) * 1000000 +
549                                 ((clkswr     ) & 0xf) * 100000;
550         }
551         /* the FR451 is currently fixed at 24MHz */
552         else if (cpu_system == __frv_mb93091_cb451) {
553                 //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
554                 unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
555 
556                 if (clkswr & 0x1000)
557                         __clkin_clock_speed_HZ = 60000000UL;
558                 else
559                         __clkin_clock_speed_HZ =
560                                 ((clkswr >> 8) & 0xf) * 10000000 +
561                                 ((clkswr >> 4) & 0xf) * 1000000 +
562                                 ((clkswr     ) & 0xf) * 100000;
563         }
564         /* otherwise determine the clockspeed from VDK or other registers */
565         else {
566                 __clkin_clock_speed_HZ = __get_CLKIN();
567         }
568 
569         /* look up the appropriate clock relationships table entry */
570         mode = &undef_clock_cmode;
571         if (clock_cmodes) {
572                 tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s];
573                 if (tmode->xbus)
574                         mode = tmode;
575         }
576 
577 #define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))
578 
579         if (clock_doubled)
580                 __clkin_clock_speed_HZ <<= 1;
581 
582         __ext_bus_clock_speed_HZ        = CLOCK(__clkin_clock_speed_HZ, mode->xbus);
583         __sdram_clock_speed_HZ          = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
584         __dsu_clock_speed_HZ            = CLOCK(__clkin_clock_speed_HZ, mode->dsu);
585 
586         switch (clkc & CLKC_CM) {
587         case 0: /* High */
588                 __core_bus_clock_speed_HZ       = CLOCK(__clkin_clock_speed_HZ, mode->corebus);
589                 __core_clock_speed_HZ           = CLOCK(__clkin_clock_speed_HZ, mode->core);
590                 break;
591         case 1: /* Medium */
592                 __core_bus_clock_speed_HZ       = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
593                 __core_clock_speed_HZ           = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
594                 break;
595         case 2: /* Low; not supported */
596         case 3: /* UNDEF */
597                 printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM);
598                 panic("Bye");
599         }
600 
601         __res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ;
602         if (clkc & CLKC_P0)
603                 __res_bus_clock_speed_HZ >>= 1;
604 
605         if (verbose) {
606                 printk("CLKIN: %lu.%3.3luMHz\n",
607                        __clkin_clock_speed_HZ / 1000000,
608                        (__clkin_clock_speed_HZ / 1000) % 1000);
609 
610                 printk("CLKS:"
611                        " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
612                        __ext_bus_clock_speed_HZ / 1000000,
613                        __res_bus_clock_speed_HZ / 1000000,
614                        __sdram_clock_speed_HZ / 1000000,
615                        __core_bus_clock_speed_HZ / 1000000,
616                        __core_clock_speed_HZ / 1000000,
617                        __dsu_clock_speed_HZ / 1000000
618                        );
619         }
620 
621         /* calculate the number of __delay() loop iterations per sec (2 insn loop) */
622         __delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2);
623 
624         /* set the serial prescaler */
625         __serial_clock_speed_HZ = __res_bus_clock_speed_HZ;
626         quot = 1;
627         while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000)
628                 quot += 1;
629 
630         /* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
631          * - we have to be careful - dividing too much can mean we can't get 115200 baud
632          */
633         if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0))
634                 quot <<= 1;
635 
636         __serial_clock_speed_HZ /= quot;
637         __frv_uart0.uartclk = __serial_clock_speed_HZ;
638         __frv_uart1.uartclk = __serial_clock_speed_HZ;
639 
640         if (verbose)
641                 printk("      uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot);
642 
643         while (!(__get_UART0_LSR() & UART_LSR_TEMT))
644                 continue;
645 
646         while (!(__get_UART1_LSR() & UART_LSR_TEMT))
647                 continue;
648 
649         __set_UCPVR(quot);
650         __set_UCPSR(0);
651 } /* end determine_clocks() */
652 
653 /*****************************************************************************/
654 /*
655  * reserve some DMA consistent memory
656  */
657 #ifdef CONFIG_RESERVE_DMA_COHERENT
658 static void __init reserve_dma_coherent(void)
659 {
660         unsigned long ampr;
661 
662         /* find the first non-kernel memory tile and steal it */
663 #define __steal_AMPR(r)                                         \
664         if (__get_DAMPR(r) & xAMPRx_V) {                        \
665                 ampr = __get_DAMPR(r);                          \
666                 __set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C);     \
667                 __set_IAMPR(r, 0);                              \
668                 goto found;                                     \
669         }
670 
671         __steal_AMPR(1);
672         __steal_AMPR(2);
673         __steal_AMPR(3);
674         __steal_AMPR(4);
675         __steal_AMPR(5);
676         __steal_AMPR(6);
677 
678         if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) {
679                 __steal_AMPR(7);
680                 __steal_AMPR(8);
681                 __steal_AMPR(9);
682                 __steal_AMPR(10);
683                 __steal_AMPR(11);
684                 __steal_AMPR(12);
685                 __steal_AMPR(13);
686                 __steal_AMPR(14);
687         }
688 
689         /* unable to grant any DMA consistent memory */
690         printk("No DMA consistent memory reserved\n");
691         return;
692 
693  found:
694         dma_coherent_mem_start = ampr & xAMPRx_PPFN;
695         ampr &= xAMPRx_SS;
696         ampr >>= 4;
697         ampr = 1 << (ampr - 3 + 20);
698         dma_coherent_mem_end = dma_coherent_mem_start + ampr;
699 
700         printk("DMA consistent memory reserved %lx-%lx\n",
701                dma_coherent_mem_start, dma_coherent_mem_end);
702 
703 } /* end reserve_dma_coherent() */
704 #endif
705 
706 /*****************************************************************************/
707 /*
708  * calibrate the delay loop
709  */
710 void __cpuinit calibrate_delay(void)
711 {
712         loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);
713 
714         printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
715                loops_per_jiffy / (500000 / HZ),
716                (loops_per_jiffy / (5000 / HZ)) % 100);
717 
718 } /* end calibrate_delay() */
719 
720 /*****************************************************************************/
721 /*
722  * look through the command line for some things we need to know immediately
723  */
724 static void __init parse_cmdline_early(char *cmdline)
725 {
726         if (!cmdline)
727                 return;
728 
729         while (*cmdline) {
730                 if (*cmdline == ' ')
731                         cmdline++;
732 
733                 /* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
734                  * out from the SDRAM controller mask register
735                  */
736                 if (!memcmp(cmdline, "mem=", 4)) {
737                         unsigned long long mem_size;
738 
739                         mem_size = memparse(cmdline + 4, &cmdline);
740                         memory_end = memory_start + mem_size;
741                 }
742 
743                 while (*cmdline && *cmdline != ' ')
744                         cmdline++;
745         }
746 
747 } /* end parse_cmdline_early() */
748 
749 /*****************************************************************************/
750 /*
751  *
752  */
753 void __init setup_arch(char **cmdline_p)
754 {
755 #ifdef CONFIG_MMU
756         printk("Linux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
757 #else
758         printk("uClinux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
759 #endif
760 
761         memcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE);
762 
763         determine_cpu();
764         determine_clocks(1);
765 
766         /* For printk-directly-beats-on-serial-hardware hack */
767         console_set_baud(115200);
768 #ifdef CONFIG_GDBSTUB
769         gdbstub_set_baud(115200);
770 #endif
771 
772 #ifdef CONFIG_RESERVE_DMA_COHERENT
773         reserve_dma_coherent();
774 #endif
775         dump_memory_map();
776 
777 #ifdef CONFIG_MB93090_MB00
778         if (mb93090_mb00_detected)
779                 mb93090_display();
780 #endif
781 
782         /* register those serial ports that are available */
783 #ifdef CONFIG_FRV_ONCPU_SERIAL
784 #ifndef CONFIG_GDBSTUB_UART0
785         __reg(UART0_BASE + UART_IER * 8) = 0;
786         early_serial_setup(&__frv_uart0);
787 #endif
788 #ifndef CONFIG_GDBSTUB_UART1
789         __reg(UART1_BASE + UART_IER * 8) = 0;
790         early_serial_setup(&__frv_uart1);
791 #endif
792 #endif
793 
794         /* deal with the command line - RedBoot may have passed one to the kernel */
795         memcpy(command_line, boot_command_line, sizeof(command_line));
796         *cmdline_p = &command_line[0];
797         parse_cmdline_early(command_line);
798 
799         /* set up the memory description
800          * - by now the stack is part of the init task */
801         printk("Memory %08lx-%08lx\n", memory_start, memory_end);
802 
803         BUG_ON(memory_start == memory_end);
804 
805         init_mm.start_code = (unsigned long) &_stext;
806         init_mm.end_code = (unsigned long) &_etext;
807         init_mm.end_data = (unsigned long) &_edata;
808 #if 0 /* DAVIDM - don't set brk just incase someone decides to use it */
809         init_mm.brk = (unsigned long) &_end;
810 #else
811         init_mm.brk = (unsigned long) 0;
812 #endif
813 
814 #ifdef DEBUG
815         printk("KERNEL -> TEXT=0x%06x-0x%06x DATA=0x%06x-0x%06x BSS=0x%06x-0x%06x\n",
816                (int) &_stext, (int) &_etext,
817                (int) &_sdata, (int) &_edata,
818                (int) &_sbss, (int) &_ebss);
819 #endif
820 
821 #ifdef CONFIG_VT
822 #if defined(CONFIG_VGA_CONSOLE)
823         conswitchp = &vga_con;
824 #elif defined(CONFIG_DUMMY_CONSOLE)
825         conswitchp = &dummy_con;
826 #endif
827 #endif
828 
829 #ifdef CONFIG_MMU
830         setup_linux_memory();
831 #else
832         setup_uclinux_memory();
833 #endif
834 
835         /* get kmalloc into gear */
836         paging_init();
837 
838         /* init DMA */
839         frv_dma_init();
840 #ifdef DEBUG
841         printk("Done setup_arch\n");
842 #endif
843 
844         /* start the decrement timer running */
845 //      asm volatile("movgs %0,timerd" :: "r"(10000000));
846 //      __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
847 
848 } /* end setup_arch() */
849 
850 #if 0
851 /*****************************************************************************/
852 /*
853  *
854  */
855 static int __devinit setup_arch_serial(void)
856 {
857         /* register those serial ports that are available */
858 #ifndef CONFIG_GDBSTUB_UART0
859         early_serial_setup(&__frv_uart0);
860 #endif
861 #ifndef CONFIG_GDBSTUB_UART1
862         early_serial_setup(&__frv_uart1);
863 #endif
864 
865         return 0;
866 } /* end setup_arch_serial() */
867 
868 late_initcall(setup_arch_serial);
869 #endif
870 
871 /*****************************************************************************/
872 /*
873  * set up the memory map for normal MMU linux
874  */
875 #ifdef CONFIG_MMU
876 static void __init setup_linux_memory(void)
877 {
878         unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem;
879 
880         kstart  = (unsigned long) &__kernel_image_start - PAGE_OFFSET;
881         kend    = (unsigned long) &__kernel_image_end - PAGE_OFFSET;
882 
883         kstart = kstart & PAGE_MASK;
884         kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
885 
886         /* give all the memory to the bootmap allocator,  tell it to put the
887          * boot mem_map immediately following the kernel image
888          */
889         bootmap_size = init_bootmem_node(NODE_DATA(0),
890                                          kend >> PAGE_SHIFT,            /* map addr */
891                                          memory_start >> PAGE_SHIFT,    /* start of RAM */
892                                          memory_end >> PAGE_SHIFT       /* end of RAM */
893                                          );
894 
895         /* pass the memory that the kernel can immediately use over to the bootmem allocator */
896         max_mapnr = num_physpages = (memory_end - memory_start) >> PAGE_SHIFT;
897         low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT;
898         high_mem = 0;
899 
900         if (num_physpages > low_top_pfn) {
901 #ifdef CONFIG_HIGHMEM
902                 high_mem = num_physpages - low_top_pfn;
903 #else
904                 max_mapnr = num_physpages = low_top_pfn;
905 #endif
906         }
907         else {
908                 low_top_pfn = num_physpages;
909         }
910 
911         min_low_pfn = memory_start >> PAGE_SHIFT;
912         max_low_pfn = low_top_pfn;
913         max_pfn = memory_end >> PAGE_SHIFT;
914 
915         num_mappedpages = low_top_pfn;
916 
917         printk(KERN_NOTICE "%ldMB LOWMEM available.\n", low_top_pfn >> (20 - PAGE_SHIFT));
918 
919         free_bootmem(memory_start, low_top_pfn << PAGE_SHIFT);
920 
921 #ifdef CONFIG_HIGHMEM
922         if (high_mem)
923                 printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", high_mem >> (20 - PAGE_SHIFT));
924 #endif
925 
926         /* take back the memory occupied by the kernel image and the bootmem alloc map */
927         reserve_bootmem(kstart, kend - kstart + bootmap_size,
928                         BOOTMEM_DEFAULT);
929 
930         /* reserve the memory occupied by the initial ramdisk */
931 #ifdef CONFIG_BLK_DEV_INITRD
932         if (LOADER_TYPE && INITRD_START) {
933                 if (INITRD_START + INITRD_SIZE <= (low_top_pfn << PAGE_SHIFT)) {
934                         reserve_bootmem(INITRD_START, INITRD_SIZE,
935                                         BOOTMEM_DEFAULT);
936                         initrd_start = INITRD_START + PAGE_OFFSET;
937                         initrd_end = initrd_start + INITRD_SIZE;
938                 }
939                 else {
940                         printk(KERN_ERR
941                                "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n"
942                                "disabling initrd\n",
943                                INITRD_START + INITRD_SIZE,
944                                low_top_pfn << PAGE_SHIFT);
945                         initrd_start = 0;
946                 }
947         }
948 #endif
949 
950 } /* end setup_linux_memory() */
951 #endif
952 
953 /*****************************************************************************/
954 /*
955  * set up the memory map for uClinux
956  */
957 #ifndef CONFIG_MMU
958 static void __init setup_uclinux_memory(void)
959 {
960 #ifdef CONFIG_PROTECT_KERNEL
961         unsigned long dampr;
962 #endif
963         unsigned long kend;
964         int bootmap_size;
965 
966         kend = (unsigned long) &__kernel_image_end;
967         kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
968 
969         /* give all the memory to the bootmap allocator,  tell it to put the
970          * boot mem_map immediately following the kernel image
971          */
972         bootmap_size = init_bootmem_node(NODE_DATA(0),
973                                          kend >> PAGE_SHIFT,            /* map addr */
974                                          memory_start >> PAGE_SHIFT,    /* start of RAM */
975                                          memory_end >> PAGE_SHIFT       /* end of RAM */
976                                          );
977 
978         /* free all the usable memory */
979         free_bootmem(memory_start, memory_end - memory_start);
980 
981         high_memory = (void *) (memory_end & PAGE_MASK);
982         max_mapnr = num_physpages = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
983 
984         min_low_pfn = memory_start >> PAGE_SHIFT;
985         max_low_pfn = memory_end >> PAGE_SHIFT;
986         max_pfn = max_low_pfn;
987 
988         /* now take back the bits the core kernel is occupying */
989 #ifndef CONFIG_PROTECT_KERNEL
990         reserve_bootmem(kend, bootmap_size, BOOTMEM_DEFAULT);
991         reserve_bootmem((unsigned long) &__kernel_image_start,
992                         kend - (unsigned long) &__kernel_image_start,
993                         BOOTMEM_DEFAULT);
994 
995 #else
996         dampr = __get_DAMPR(0);
997         dampr &= xAMPRx_SS;
998         dampr = (dampr >> 4) + 17;
999         dampr = 1 << dampr;
1000 
1001         reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN, dampr, BOOTMEM_DEFAULT);
1002 #endif
1003 
1004         /* reserve some memory to do uncached DMA through if requested */
1005 #ifdef CONFIG_RESERVE_DMA_COHERENT
1006         if (dma_coherent_mem_start)
1007                 reserve_bootmem(dma_coherent_mem_start,
1008                                 dma_coherent_mem_end - dma_coherent_mem_start,
1009                                 BOOTMEM_DEFAULT);
1010 #endif
1011 
1012 } /* end setup_uclinux_memory() */
1013 #endif
1014 
1015 /*****************************************************************************/
1016 /*
1017  * get CPU information for use by procfs
1018  */
1019 static int show_cpuinfo(struct seq_file *m, void *v)
1020 {
1021         const char *gr, *fr, *fm, *fp, *cm, *nem, *ble;
1022 #ifdef CONFIG_PM
1023         const char *sep;
1024 #endif
1025 
1026         gr  = cpu_hsr0_all & HSR0_GRHE  ? "gr0-63"      : "gr0-31";
1027         fr  = cpu_hsr0_all & HSR0_FRHE  ? "fr0-63"      : "fr0-31";
1028         fm  = cpu_psr_all  & PSR_EM     ? ", Media"     : "";
1029         fp  = cpu_psr_all  & PSR_EF     ? ", FPU"       : "";
1030         cm  = cpu_psr_all  & PSR_CM     ? ", CCCR"      : "";
1031         nem = cpu_psr_all  & PSR_NEM    ? ", NE"        : "";
1032         ble = cpu_psr_all  & PSR_BE     ? "BE"          : "LE";
1033 
1034         seq_printf(m,
1035                    "CPU-Series:\t%s\n"
1036                    "CPU-Core:\t%s, %s, %s%s%s\n"
1037                    "CPU:\t\t%s\n"
1038                    "MMU:\t\t%s\n"
1039                    "FP-Media:\t%s%s%s\n"
1040                    "System:\t\t%s",
1041                    cpu_series,
1042                    cpu_core, gr, ble, cm, nem,
1043                    cpu_silicon,
1044                    cpu_mmu,
1045                    fr, fm, fp,
1046                    cpu_system);
1047 
1048         if (cpu_board1)
1049                 seq_printf(m, ", %s", cpu_board1);
1050 
1051         if (cpu_board2)
1052                 seq_printf(m, ", %s", cpu_board2);
1053 
1054         seq_printf(m, "\n");
1055 
1056 #ifdef CONFIG_PM
1057         seq_printf(m, "PM-Controls:");
1058         sep = "\t";
1059 
1060         if (clock_bits_settable & CLOCK_BIT_CMODE) {
1061                 seq_printf(m, "%scmode=0x%04hx", sep, clock_cmodes_permitted);
1062                 sep = ", ";
1063         }
1064 
1065         if (clock_bits_settable & CLOCK_BIT_CM) {
1066                 seq_printf(m, "%scm=0x%lx", sep, clock_bits_settable & CLOCK_BIT_CM);
1067                 sep = ", ";
1068         }
1069 
1070         if (clock_bits_settable & CLOCK_BIT_P0) {
1071                 seq_printf(m, "%sp0=0x3", sep);
1072                 sep = ", ";
1073         }
1074 
1075         seq_printf(m, "%ssuspend=0x22\n", sep);
1076 #endif
1077 
1078         seq_printf(m,
1079                    "PM-Status:\tcmode=%d, cm=%d, p0=%d\n",
1080                    clock_cmode_current, clock_cm_current, clock_p0_current);
1081 
1082 #define print_clk(TAG, VAR) \
1083         seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100)
1084 
1085         print_clk("In",    __clkin_clock_speed_HZ);
1086         print_clk("Core",  __core_clock_speed_HZ);
1087         print_clk("SDRAM", __sdram_clock_speed_HZ);
1088         print_clk("CBus",  __core_bus_clock_speed_HZ);
1089         print_clk("Res",   __res_bus_clock_speed_HZ);
1090         print_clk("Ext",   __ext_bus_clock_speed_HZ);
1091         print_clk("DSU",   __dsu_clock_speed_HZ);
1092 
1093         seq_printf(m,
1094                    "BogoMips:\t%lu.%02lu\n",
1095                    (loops_per_jiffy * HZ) / 500000, ((loops_per_jiffy * HZ) / 5000) % 100);
1096 
1097         return 0;
1098 } /* end show_cpuinfo() */
1099 
1100 static void *c_start(struct seq_file *m, loff_t *pos)
1101 {
1102         return *pos < NR_CPUS ? (void *) 0x12345678 : NULL;
1103 }
1104 
1105 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1106 {
1107         ++*pos;
1108         return c_start(m, pos);
1109 }
1110 
1111 static void c_stop(struct seq_file *m, void *v)
1112 {
1113 }
1114 
1115 const struct seq_operations cpuinfo_op = {
1116         .start  = c_start,
1117         .next   = c_next,
1118         .stop   = c_stop,
1119         .show   = show_cpuinfo,
1120 };
1121 
1122 void arch_gettod(int *year, int *mon, int *day, int *hour,
1123                  int *min, int *sec)
1124 {
1125         *year = *mon = *day = *hour = *min = *sec = 0;
1126 }
1127 
1128 /*****************************************************************************/
1129 /*
1130  *
1131  */
1132 #ifdef CONFIG_MB93090_MB00
1133 static void __init mb93090_sendlcdcmd(uint32_t cmd)
1134 {
1135         unsigned long base = __addr_LCD();
1136         int loop;
1137 
1138         /* request reading of the busy flag */
1139         __set_LCD(base, LCD_CMD_READ_BUSY);
1140         __set_LCD(base, LCD_CMD_READ_BUSY & ~LCD_E);
1141 
1142         /* wait for the busy flag to become clear */
1143         for (loop = 10000; loop > 0; loop--)
1144                 if (!(__get_LCD(base) & 0x80))
1145                         break;
1146 
1147         /* send the command */
1148         __set_LCD(base, cmd);
1149         __set_LCD(base, cmd & ~LCD_E);
1150 
1151 } /* end mb93090_sendlcdcmd() */
1152 
1153 /*****************************************************************************/
1154 /*
1155  * write to the MB93090 LEDs and LCD
1156  */
1157 static void __init mb93090_display(void)
1158 {
1159         const char *p;
1160 
1161         __set_LEDS(0);
1162 
1163         /* set up the LCD */
1164         mb93090_sendlcdcmd(LCD_CMD_CLEAR);
1165         mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0));
1166         mb93090_sendlcdcmd(LCD_CMD_ON(0,0));
1167         mb93090_sendlcdcmd(LCD_CMD_HOME);
1168 
1169         mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0));
1170         for (p = mb93090_banner; *p; p++)
1171                 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1172 
1173         mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64));
1174         for (p = mb93090_version; *p; p++)
1175                 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1176 
1177 } /* end mb93090_display() */
1178 
1179 #endif // CONFIG_MB93090_MB00
1180 

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