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TOMOYO Linux Cross Reference
Linux/arch/i386/kernel/i8259.c

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  1 #include <linux/config.h>
  2 #include <linux/errno.h>
  3 #include <linux/signal.h>
  4 #include <linux/sched.h>
  5 #include <linux/ioport.h>
  6 #include <linux/interrupt.h>
  7 #include <linux/timex.h>
  8 #include <linux/slab.h>
  9 #include <linux/random.h>
 10 #include <linux/smp_lock.h>
 11 #include <linux/init.h>
 12 #include <linux/kernel_stat.h>
 13 #include <linux/sysdev.h>
 14 
 15 #include <asm/atomic.h>
 16 #include <asm/system.h>
 17 #include <asm/io.h>
 18 #include <asm/irq.h>
 19 #include <asm/bitops.h>
 20 #include <asm/pgtable.h>
 21 #include <asm/delay.h>
 22 #include <asm/desc.h>
 23 #include <asm/apic.h>
 24 #include <asm/arch_hooks.h>
 25 #include <asm/i8259.h>
 26 
 27 #include <linux/irq.h>
 28 
 29 #include <io_ports.h>
 30 
 31 /*
 32  * This is the 'legacy' 8259A Programmable Interrupt Controller,
 33  * present in the majority of PC/AT boxes.
 34  * plus some generic x86 specific things if generic specifics makes
 35  * any sense at all.
 36  * this file should become arch/i386/kernel/irq.c when the old irq.c
 37  * moves to arch independent land
 38  */
 39 
 40 spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
 41 
 42 static void end_8259A_irq (unsigned int irq)
 43 {
 44         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
 45                                                         irq_desc[irq].action)
 46                 enable_8259A_irq(irq);
 47 }
 48 
 49 #define shutdown_8259A_irq      disable_8259A_irq
 50 
 51 void mask_and_ack_8259A(unsigned int);
 52 
 53 unsigned int startup_8259A_irq(unsigned int irq)
 54 { 
 55         enable_8259A_irq(irq);
 56         return 0; /* never anything pending */
 57 }
 58 
 59 static struct hw_interrupt_type i8259A_irq_type = {
 60         "XT-PIC",
 61         startup_8259A_irq,
 62         shutdown_8259A_irq,
 63         enable_8259A_irq,
 64         disable_8259A_irq,
 65         mask_and_ack_8259A,
 66         end_8259A_irq,
 67         NULL
 68 };
 69 
 70 /*
 71  * 8259A PIC functions to handle ISA devices:
 72  */
 73 
 74 /*
 75  * This contains the irq mask for both 8259A irq controllers,
 76  */
 77 unsigned int cached_irq_mask = 0xffff;
 78 
 79 /*
 80  * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 81  * boards the timer interrupt is not really connected to any IO-APIC pin,
 82  * it's fed to the master 8259A's IR0 line only.
 83  *
 84  * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 85  * this 'mixed mode' IRQ handling costs nothing because it's only used
 86  * at IRQ setup time.
 87  */
 88 unsigned long io_apic_irqs;
 89 
 90 void disable_8259A_irq(unsigned int irq)
 91 {
 92         unsigned int mask = 1 << irq;
 93         unsigned long flags;
 94 
 95         spin_lock_irqsave(&i8259A_lock, flags);
 96         cached_irq_mask |= mask;
 97         if (irq & 8)
 98                 outb(cached_slave_mask, PIC_SLAVE_IMR);
 99         else
100                 outb(cached_master_mask, PIC_MASTER_IMR);
101         spin_unlock_irqrestore(&i8259A_lock, flags);
102 }
103 
104 void enable_8259A_irq(unsigned int irq)
105 {
106         unsigned int mask = ~(1 << irq);
107         unsigned long flags;
108 
109         spin_lock_irqsave(&i8259A_lock, flags);
110         cached_irq_mask &= mask;
111         if (irq & 8)
112                 outb(cached_slave_mask, PIC_SLAVE_IMR);
113         else
114                 outb(cached_master_mask, PIC_MASTER_IMR);
115         spin_unlock_irqrestore(&i8259A_lock, flags);
116 }
117 
118 int i8259A_irq_pending(unsigned int irq)
119 {
120         unsigned int mask = 1<<irq;
121         unsigned long flags;
122         int ret;
123 
124         spin_lock_irqsave(&i8259A_lock, flags);
125         if (irq < 8)
126                 ret = inb(PIC_MASTER_CMD) & mask;
127         else
128                 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
129         spin_unlock_irqrestore(&i8259A_lock, flags);
130 
131         return ret;
132 }
133 
134 void make_8259A_irq(unsigned int irq)
135 {
136         disable_irq_nosync(irq);
137         io_apic_irqs &= ~(1<<irq);
138         irq_desc[irq].handler = &i8259A_irq_type;
139         enable_irq(irq);
140 }
141 
142 /*
143  * This function assumes to be called rarely. Switching between
144  * 8259A registers is slow.
145  * This has to be protected by the irq controller spinlock
146  * before being called.
147  */
148 static inline int i8259A_irq_real(unsigned int irq)
149 {
150         int value;
151         int irqmask = 1<<irq;
152 
153         if (irq < 8) {
154                 outb(0x0B,PIC_MASTER_CMD);      /* ISR register */
155                 value = inb(PIC_MASTER_CMD) & irqmask;
156                 outb(0x0A,PIC_MASTER_CMD);      /* back to the IRR register */
157                 return value;
158         }
159         outb(0x0B,PIC_SLAVE_CMD);       /* ISR register */
160         value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
161         outb(0x0A,PIC_SLAVE_CMD);       /* back to the IRR register */
162         return value;
163 }
164 
165 /*
166  * Careful! The 8259A is a fragile beast, it pretty
167  * much _has_ to be done exactly like this (mask it
168  * first, _then_ send the EOI, and the order of EOI
169  * to the two 8259s is important!
170  */
171 void mask_and_ack_8259A(unsigned int irq)
172 {
173         unsigned int irqmask = 1 << irq;
174         unsigned long flags;
175 
176         spin_lock_irqsave(&i8259A_lock, flags);
177         /*
178          * Lightweight spurious IRQ detection. We do not want
179          * to overdo spurious IRQ handling - it's usually a sign
180          * of hardware problems, so we only do the checks we can
181          * do without slowing down good hardware unnecesserily.
182          *
183          * Note that IRQ7 and IRQ15 (the two spurious IRQs
184          * usually resulting from the 8259A-1|2 PICs) occur
185          * even if the IRQ is masked in the 8259A. Thus we
186          * can check spurious 8259A IRQs without doing the
187          * quite slow i8259A_irq_real() call for every IRQ.
188          * This does not cover 100% of spurious interrupts,
189          * but should be enough to warn the user that there
190          * is something bad going on ...
191          */
192         if (cached_irq_mask & irqmask)
193                 goto spurious_8259A_irq;
194         cached_irq_mask |= irqmask;
195 
196 handle_real_irq:
197         if (irq & 8) {
198                 inb(PIC_SLAVE_IMR);     /* DUMMY - (do we need this?) */
199                 outb(cached_slave_mask, PIC_SLAVE_IMR);
200                 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
201                 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
202         } else {
203                 inb(PIC_MASTER_IMR);    /* DUMMY - (do we need this?) */
204                 outb(cached_master_mask, PIC_MASTER_IMR);
205                 outb(0x60+irq,PIC_MASTER_CMD);  /* 'Specific EOI to master */
206         }
207         spin_unlock_irqrestore(&i8259A_lock, flags);
208         return;
209 
210 spurious_8259A_irq:
211         /*
212          * this is the slow path - should happen rarely.
213          */
214         if (i8259A_irq_real(irq))
215                 /*
216                  * oops, the IRQ _is_ in service according to the
217                  * 8259A - not spurious, go handle it.
218                  */
219                 goto handle_real_irq;
220 
221         {
222                 static int spurious_irq_mask;
223                 /*
224                  * At this point we can be sure the IRQ is spurious,
225                  * lets ACK and report it. [once per IRQ]
226                  */
227                 if (!(spurious_irq_mask & irqmask)) {
228                         printk("spurious 8259A interrupt: IRQ%d.\n", irq);
229                         spurious_irq_mask |= irqmask;
230                 }
231                 atomic_inc(&irq_err_count);
232                 /*
233                  * Theoretically we do not have to handle this IRQ,
234                  * but in Linux this does not cause problems and is
235                  * simpler for us.
236                  */
237                 goto handle_real_irq;
238         }
239 }
240 
241 static int i8259A_resume(struct sys_device *dev)
242 {
243         init_8259A(0);
244         return 0;
245 }
246 
247 static struct sysdev_class i8259_sysdev_class = {
248         set_kset_name("i8259"),
249         .resume = i8259A_resume,
250 };
251 
252 static struct sys_device device_i8259A = {
253         .id     = 0,
254         .cls    = &i8259_sysdev_class,
255 };
256 
257 static int __init i8259A_init_sysfs(void)
258 {
259         int error = sysdev_class_register(&i8259_sysdev_class);
260         if (!error)
261                 error = sys_device_register(&device_i8259A);
262         return error;
263 }
264 
265 device_initcall(i8259A_init_sysfs);
266 
267 void init_8259A(int auto_eoi)
268 {
269         unsigned long flags;
270 
271         spin_lock_irqsave(&i8259A_lock, flags);
272 
273         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
274         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
275 
276         /*
277          * outb_p - this has to work on a wide range of PC hardware.
278          */
279         outb_p(0x11, PIC_MASTER_CMD);   /* ICW1: select 8259A-1 init */
280         outb_p(0x20 + 0, PIC_MASTER_IMR);       /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
281         outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);   /* 8259A-1 (the master) has a slave on IR2 */
282         if (auto_eoi)   /* master does Auto EOI */
283                 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
284         else            /* master expects normal EOI */
285                 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
286 
287         outb_p(0x11, PIC_SLAVE_CMD);    /* ICW1: select 8259A-2 init */
288         outb_p(0x20 + 8, PIC_SLAVE_IMR);        /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
289         outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);  /* 8259A-2 is a slave on master's IR2 */
290         outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
291         if (auto_eoi)
292                 /*
293                  * in AEOI mode we just have to mask the interrupt
294                  * when acking.
295                  */
296                 i8259A_irq_type.ack = disable_8259A_irq;
297         else
298                 i8259A_irq_type.ack = mask_and_ack_8259A;
299 
300         udelay(100);            /* wait for 8259A to initialize */
301 
302         outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
303         outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
304 
305         spin_unlock_irqrestore(&i8259A_lock, flags);
306 }
307 
308 /*
309  * Note that on a 486, we don't want to do a SIGFPE on an irq13
310  * as the irq is unreliable, and exception 16 works correctly
311  * (ie as explained in the intel literature). On a 386, you
312  * can't use exception 16 due to bad IBM design, so we have to
313  * rely on the less exact irq13.
314  *
315  * Careful.. Not only is IRQ13 unreliable, but it is also
316  * leads to races. IBM designers who came up with it should
317  * be shot.
318  */
319  
320 /*
321  * =PC9800NOTE= In NEC PC-9800, we use irq8 instead of irq13!
322  */
323 
324 static irqreturn_t math_error_irq(int cpl, void *dev_id, struct pt_regs *regs)
325 {
326         extern void math_error(void *);
327 #ifndef CONFIG_X86_PC9800
328         outb(0,0xF0);
329 #endif
330         if (ignore_fpu_irq || !boot_cpu_data.hard_math)
331                 return IRQ_NONE;
332         math_error((void *)regs->eip);
333         return IRQ_HANDLED;
334 }
335 
336 /*
337  * New motherboards sometimes make IRQ 13 be a PCI interrupt,
338  * so allow interrupt sharing.
339  */
340 static struct irqaction fpu_irq = { math_error_irq, 0, 0, "fpu", NULL, NULL };
341 
342 void __init init_ISA_irqs (void)
343 {
344         int i;
345 
346 #ifdef CONFIG_X86_LOCAL_APIC
347         init_bsp_APIC();
348 #endif
349         init_8259A(0);
350 
351         for (i = 0; i < NR_IRQS; i++) {
352                 irq_desc[i].status = IRQ_DISABLED;
353                 irq_desc[i].action = 0;
354                 irq_desc[i].depth = 1;
355 
356                 if (i < 16) {
357                         /*
358                          * 16 old-style INTA-cycle interrupts:
359                          */
360                         irq_desc[i].handler = &i8259A_irq_type;
361                 } else {
362                         /*
363                          * 'high' PCI IRQs filled in on demand
364                          */
365                         irq_desc[i].handler = &no_irq_type;
366                 }
367         }
368 }
369 
370 static void setup_timer(void)
371 {
372         extern spinlock_t i8253_lock;
373         unsigned long flags;
374 
375         spin_lock_irqsave(&i8253_lock, flags);
376         outb_p(0x34,PIT_MODE);          /* binary, mode 2, LSB/MSB, ch 0 */
377         udelay(10);
378         outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
379         udelay(10);
380         outb(LATCH >> 8 , PIT_CH0);     /* MSB */
381         spin_unlock_irqrestore(&i8253_lock, flags);
382 }
383 
384 static int timer_resume(struct sys_device *dev)
385 {
386         setup_timer();
387         return 0;
388 }
389 
390 static struct sysdev_class timer_sysclass = {
391         set_kset_name("timer"),
392         .resume = timer_resume,
393 };
394 
395 static struct sys_device device_timer = {
396         .id     = 0,
397         .cls    = &timer_sysclass,
398 };
399 
400 static int __init init_timer_sysfs(void)
401 {
402         int error = sysdev_class_register(&timer_sysclass);
403         if (!error)
404                 error = sys_device_register(&device_timer);
405         return error;
406 }
407 
408 device_initcall(init_timer_sysfs);
409 
410 void __init init_IRQ(void)
411 {
412         int i;
413 
414         /* all the set up before the call gates are initialised */
415         pre_intr_init_hook();
416 
417         /*
418          * Cover the whole vector space, no vector can escape
419          * us. (some of these will be overridden and become
420          * 'special' SMP interrupts)
421          */
422         for (i = 0; i < NR_IRQS; i++) {
423                 int vector = FIRST_EXTERNAL_VECTOR + i;
424                 if (vector != SYSCALL_VECTOR) 
425                         set_intr_gate(vector, interrupt[i]);
426         }
427 
428         /* setup after call gates are initialised (usually add in
429          * the architecture specific gates)
430          */
431         intr_init_hook();
432 
433         /*
434          * Set the clock to HZ Hz, we already have a valid
435          * vector now:
436          */
437         setup_timer();
438 
439         /*
440          * External FPU? Set up irq13 if so, for
441          * original braindamaged IBM FERR coupling.
442          */
443         if (boot_cpu_data.hard_math && !cpu_has_fpu)
444                 setup_irq(FPU_IRQ, &fpu_irq);
445 }
446 

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