~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/arch/ia64/kernel/mca.c

Version: ~ [ linux-4.14 ] ~ [ linux-4.13.12 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.61 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.97 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.46 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.80 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.50 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.95 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.39.4 ] ~ [ linux-2.6.38.8 ] ~ [ linux-2.6.37.6 ] ~ [ linux-2.6.36.4 ] ~ [ linux-2.6.35.14 ] ~ [ linux-2.6.34.15 ] ~ [ linux-2.6.33.20 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.27.62 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * File:        mca.c
  3  * Purpose:     Generic MCA handling layer
  4  *
  5  * Copyright (C) 2003 Hewlett-Packard Co
  6  *      David Mosberger-Tang <davidm@hpl.hp.com>
  7  *
  8  * Copyright (C) 2002 Dell Inc.
  9  * Copyright (C) Matt Domsch <Matt_Domsch@dell.com>
 10  *
 11  * Copyright (C) 2002 Intel
 12  * Copyright (C) Jenna Hall <jenna.s.hall@intel.com>
 13  *
 14  * Copyright (C) 2001 Intel
 15  * Copyright (C) Fred Lewis <frederick.v.lewis@intel.com>
 16  *
 17  * Copyright (C) 2000 Intel
 18  * Copyright (C) Chuck Fleckenstein <cfleck@co.intel.com>
 19  *
 20  * Copyright (C) 1999, 2004-2008 Silicon Graphics, Inc.
 21  * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
 22  *
 23  * Copyright (C) 2006 FUJITSU LIMITED
 24  * Copyright (C) Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
 25  *
 26  * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com>
 27  *            Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
 28  *            added min save state dump, added INIT handler.
 29  *
 30  * 2001-01-03 Fred Lewis <frederick.v.lewis@intel.com>
 31  *            Added setup of CMCI and CPEI IRQs, logging of corrected platform
 32  *            errors, completed code for logging of corrected & uncorrected
 33  *            machine check errors, and updated for conformance with Nov. 2000
 34  *            revision of the SAL 3.0 spec.
 35  *
 36  * 2002-01-04 Jenna Hall <jenna.s.hall@intel.com>
 37  *            Aligned MCA stack to 16 bytes, added platform vs. CPU error flag,
 38  *            set SAL default return values, changed error record structure to
 39  *            linked list, added init call to sal_get_state_info_size().
 40  *
 41  * 2002-03-25 Matt Domsch <Matt_Domsch@dell.com>
 42  *            GUID cleanups.
 43  *
 44  * 2003-04-15 David Mosberger-Tang <davidm@hpl.hp.com>
 45  *            Added INIT backtrace support.
 46  *
 47  * 2003-12-08 Keith Owens <kaos@sgi.com>
 48  *            smp_call_function() must not be called from interrupt context
 49  *            (can deadlock on tasklist_lock).
 50  *            Use keventd to call smp_call_function().
 51  *
 52  * 2004-02-01 Keith Owens <kaos@sgi.com>
 53  *            Avoid deadlock when using printk() for MCA and INIT records.
 54  *            Delete all record printing code, moved to salinfo_decode in user
 55  *            space.  Mark variables and functions static where possible.
 56  *            Delete dead variables and functions.  Reorder to remove the need
 57  *            for forward declarations and to consolidate related code.
 58  *
 59  * 2005-08-12 Keith Owens <kaos@sgi.com>
 60  *            Convert MCA/INIT handlers to use per event stacks and SAL/OS
 61  *            state.
 62  *
 63  * 2005-10-07 Keith Owens <kaos@sgi.com>
 64  *            Add notify_die() hooks.
 65  *
 66  * 2006-09-15 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
 67  *            Add printing support for MCA/INIT.
 68  *
 69  * 2007-04-27 Russ Anderson <rja@sgi.com>
 70  *            Support multiple cpus going through OS_MCA in the same event.
 71  */
 72 #include <linux/jiffies.h>
 73 #include <linux/types.h>
 74 #include <linux/init.h>
 75 #include <linux/sched/signal.h>
 76 #include <linux/sched/debug.h>
 77 #include <linux/sched/task.h>
 78 #include <linux/interrupt.h>
 79 #include <linux/irq.h>
 80 #include <linux/bootmem.h>
 81 #include <linux/acpi.h>
 82 #include <linux/timer.h>
 83 #include <linux/module.h>
 84 #include <linux/kernel.h>
 85 #include <linux/smp.h>
 86 #include <linux/workqueue.h>
 87 #include <linux/cpumask.h>
 88 #include <linux/kdebug.h>
 89 #include <linux/cpu.h>
 90 #include <linux/gfp.h>
 91 
 92 #include <asm/delay.h>
 93 #include <asm/machvec.h>
 94 #include <asm/meminit.h>
 95 #include <asm/page.h>
 96 #include <asm/ptrace.h>
 97 #include <asm/sal.h>
 98 #include <asm/mca.h>
 99 #include <asm/kexec.h>
100 
101 #include <asm/irq.h>
102 #include <asm/hw_irq.h>
103 #include <asm/tlb.h>
104 
105 #include "mca_drv.h"
106 #include "entry.h"
107 
108 #if defined(IA64_MCA_DEBUG_INFO)
109 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
110 #else
111 # define IA64_MCA_DEBUG(fmt...)
112 #endif
113 
114 #define NOTIFY_INIT(event, regs, arg, spin)                             \
115 do {                                                                    \
116         if ((notify_die((event), "INIT", (regs), (arg), 0, 0)           \
117                         == NOTIFY_STOP) && ((spin) == 1))               \
118                 ia64_mca_spin(__func__);                                \
119 } while (0)
120 
121 #define NOTIFY_MCA(event, regs, arg, spin)                              \
122 do {                                                                    \
123         if ((notify_die((event), "MCA", (regs), (arg), 0, 0)            \
124                         == NOTIFY_STOP) && ((spin) == 1))               \
125                 ia64_mca_spin(__func__);                                \
126 } while (0)
127 
128 /* Used by mca_asm.S */
129 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
130 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
131 DEFINE_PER_CPU(u64, ia64_mca_pal_pte);      /* PTE to map PAL code */
132 DEFINE_PER_CPU(u64, ia64_mca_pal_base);    /* vaddr PAL code granule */
133 DEFINE_PER_CPU(u64, ia64_mca_tr_reload);   /* Flag for TR reload */
134 
135 unsigned long __per_cpu_mca[NR_CPUS];
136 
137 /* In mca_asm.S */
138 extern void                     ia64_os_init_dispatch_monarch (void);
139 extern void                     ia64_os_init_dispatch_slave (void);
140 
141 static int monarch_cpu = -1;
142 
143 static ia64_mc_info_t           ia64_mc_info;
144 
145 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
146 #define MIN_CPE_POLL_INTERVAL (2*60*HZ)  /* 2 minutes */
147 #define CMC_POLL_INTERVAL     (1*60*HZ)  /* 1 minute */
148 #define CPE_HISTORY_LENGTH    5
149 #define CMC_HISTORY_LENGTH    5
150 
151 #ifdef CONFIG_ACPI
152 static struct timer_list cpe_poll_timer;
153 #endif
154 static struct timer_list cmc_poll_timer;
155 /*
156  * This variable tells whether we are currently in polling mode.
157  * Start with this in the wrong state so we won't play w/ timers
158  * before the system is ready.
159  */
160 static int cmc_polling_enabled = 1;
161 
162 /*
163  * Clearing this variable prevents CPE polling from getting activated
164  * in mca_late_init.  Use it if your system doesn't provide a CPEI,
165  * but encounters problems retrieving CPE logs.  This should only be
166  * necessary for debugging.
167  */
168 static int cpe_poll_enabled = 1;
169 
170 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
171 
172 static int mca_init __initdata;
173 
174 /*
175  * limited & delayed printing support for MCA/INIT handler
176  */
177 
178 #define mprintk(fmt...) ia64_mca_printk(fmt)
179 
180 #define MLOGBUF_SIZE (512+256*NR_CPUS)
181 #define MLOGBUF_MSGMAX 256
182 static char mlogbuf[MLOGBUF_SIZE];
183 static DEFINE_SPINLOCK(mlogbuf_wlock);  /* mca context only */
184 static DEFINE_SPINLOCK(mlogbuf_rlock);  /* normal context only */
185 static unsigned long mlogbuf_start;
186 static unsigned long mlogbuf_end;
187 static unsigned int mlogbuf_finished = 0;
188 static unsigned long mlogbuf_timestamp = 0;
189 
190 static int loglevel_save = -1;
191 #define BREAK_LOGLEVEL(__console_loglevel)              \
192         oops_in_progress = 1;                           \
193         if (loglevel_save < 0)                          \
194                 loglevel_save = __console_loglevel;     \
195         __console_loglevel = 15;
196 
197 #define RESTORE_LOGLEVEL(__console_loglevel)            \
198         if (loglevel_save >= 0) {                       \
199                 __console_loglevel = loglevel_save;     \
200                 loglevel_save = -1;                     \
201         }                                               \
202         mlogbuf_finished = 0;                           \
203         oops_in_progress = 0;
204 
205 /*
206  * Push messages into buffer, print them later if not urgent.
207  */
208 void ia64_mca_printk(const char *fmt, ...)
209 {
210         va_list args;
211         int printed_len;
212         char temp_buf[MLOGBUF_MSGMAX];
213         char *p;
214 
215         va_start(args, fmt);
216         printed_len = vscnprintf(temp_buf, sizeof(temp_buf), fmt, args);
217         va_end(args);
218 
219         /* Copy the output into mlogbuf */
220         if (oops_in_progress) {
221                 /* mlogbuf was abandoned, use printk directly instead. */
222                 printk("%s", temp_buf);
223         } else {
224                 spin_lock(&mlogbuf_wlock);
225                 for (p = temp_buf; *p; p++) {
226                         unsigned long next = (mlogbuf_end + 1) % MLOGBUF_SIZE;
227                         if (next != mlogbuf_start) {
228                                 mlogbuf[mlogbuf_end] = *p;
229                                 mlogbuf_end = next;
230                         } else {
231                                 /* buffer full */
232                                 break;
233                         }
234                 }
235                 mlogbuf[mlogbuf_end] = '\0';
236                 spin_unlock(&mlogbuf_wlock);
237         }
238 }
239 EXPORT_SYMBOL(ia64_mca_printk);
240 
241 /*
242  * Print buffered messages.
243  *  NOTE: call this after returning normal context. (ex. from salinfod)
244  */
245 void ia64_mlogbuf_dump(void)
246 {
247         char temp_buf[MLOGBUF_MSGMAX];
248         char *p;
249         unsigned long index;
250         unsigned long flags;
251         unsigned int printed_len;
252 
253         /* Get output from mlogbuf */
254         while (mlogbuf_start != mlogbuf_end) {
255                 temp_buf[0] = '\0';
256                 p = temp_buf;
257                 printed_len = 0;
258 
259                 spin_lock_irqsave(&mlogbuf_rlock, flags);
260 
261                 index = mlogbuf_start;
262                 while (index != mlogbuf_end) {
263                         *p = mlogbuf[index];
264                         index = (index + 1) % MLOGBUF_SIZE;
265                         if (!*p)
266                                 break;
267                         p++;
268                         if (++printed_len >= MLOGBUF_MSGMAX - 1)
269                                 break;
270                 }
271                 *p = '\0';
272                 if (temp_buf[0])
273                         printk("%s", temp_buf);
274                 mlogbuf_start = index;
275 
276                 mlogbuf_timestamp = 0;
277                 spin_unlock_irqrestore(&mlogbuf_rlock, flags);
278         }
279 }
280 EXPORT_SYMBOL(ia64_mlogbuf_dump);
281 
282 /*
283  * Call this if system is going to down or if immediate flushing messages to
284  * console is required. (ex. recovery was failed, crash dump is going to be
285  * invoked, long-wait rendezvous etc.)
286  *  NOTE: this should be called from monarch.
287  */
288 static void ia64_mlogbuf_finish(int wait)
289 {
290         BREAK_LOGLEVEL(console_loglevel);
291 
292         spin_lock_init(&mlogbuf_rlock);
293         ia64_mlogbuf_dump();
294         printk(KERN_EMERG "mlogbuf_finish: printing switched to urgent mode, "
295                 "MCA/INIT might be dodgy or fail.\n");
296 
297         if (!wait)
298                 return;
299 
300         /* wait for console */
301         printk("Delaying for 5 seconds...\n");
302         udelay(5*1000000);
303 
304         mlogbuf_finished = 1;
305 }
306 
307 /*
308  * Print buffered messages from INIT context.
309  */
310 static void ia64_mlogbuf_dump_from_init(void)
311 {
312         if (mlogbuf_finished)
313                 return;
314 
315         if (mlogbuf_timestamp &&
316                         time_before(jiffies, mlogbuf_timestamp + 30 * HZ)) {
317                 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT "
318                         " and the system seems to be messed up.\n");
319                 ia64_mlogbuf_finish(0);
320                 return;
321         }
322 
323         if (!spin_trylock(&mlogbuf_rlock)) {
324                 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT. "
325                         "Generated messages other than stack dump will be "
326                         "buffered to mlogbuf and will be printed later.\n");
327                 printk(KERN_ERR "INIT: If messages would not printed after "
328                         "this INIT, wait 30sec and assert INIT again.\n");
329                 if (!mlogbuf_timestamp)
330                         mlogbuf_timestamp = jiffies;
331                 return;
332         }
333         spin_unlock(&mlogbuf_rlock);
334         ia64_mlogbuf_dump();
335 }
336 
337 static inline void
338 ia64_mca_spin(const char *func)
339 {
340         if (monarch_cpu == smp_processor_id())
341                 ia64_mlogbuf_finish(0);
342         mprintk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
343         while (1)
344                 cpu_relax();
345 }
346 /*
347  * IA64_MCA log support
348  */
349 #define IA64_MAX_LOGS           2       /* Double-buffering for nested MCAs */
350 #define IA64_MAX_LOG_TYPES      4   /* MCA, INIT, CMC, CPE */
351 
352 typedef struct ia64_state_log_s
353 {
354         spinlock_t      isl_lock;
355         int             isl_index;
356         unsigned long   isl_count;
357         ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
358 } ia64_state_log_t;
359 
360 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
361 
362 #define IA64_LOG_ALLOCATE(it, size) \
363         {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
364                 (ia64_err_rec_t *)alloc_bootmem(size); \
365         ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
366                 (ia64_err_rec_t *)alloc_bootmem(size);}
367 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
368 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
369 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
370 #define IA64_LOG_NEXT_INDEX(it)    ia64_state_log[it].isl_index
371 #define IA64_LOG_CURR_INDEX(it)    1 - ia64_state_log[it].isl_index
372 #define IA64_LOG_INDEX_INC(it) \
373     {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
374     ia64_state_log[it].isl_count++;}
375 #define IA64_LOG_INDEX_DEC(it) \
376     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
377 #define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
378 #define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
379 #define IA64_LOG_COUNT(it)         ia64_state_log[it].isl_count
380 
381 /*
382  * ia64_log_init
383  *      Reset the OS ia64 log buffer
384  * Inputs   :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
385  * Outputs      :       None
386  */
387 static void __init
388 ia64_log_init(int sal_info_type)
389 {
390         u64     max_size = 0;
391 
392         IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
393         IA64_LOG_LOCK_INIT(sal_info_type);
394 
395         // SAL will tell us the maximum size of any error record of this type
396         max_size = ia64_sal_get_state_info_size(sal_info_type);
397         if (!max_size)
398                 /* alloc_bootmem() doesn't like zero-sized allocations! */
399                 return;
400 
401         // set up OS data structures to hold error info
402         IA64_LOG_ALLOCATE(sal_info_type, max_size);
403         memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
404         memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
405 }
406 
407 /*
408  * ia64_log_get
409  *
410  *      Get the current MCA log from SAL and copy it into the OS log buffer.
411  *
412  *  Inputs  :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
413  *              irq_safe    whether you can use printk at this point
414  *  Outputs :   size        (total record length)
415  *              *buffer     (ptr to error record)
416  *
417  */
418 static u64
419 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
420 {
421         sal_log_record_header_t     *log_buffer;
422         u64                         total_len = 0;
423         unsigned long               s;
424 
425         IA64_LOG_LOCK(sal_info_type);
426 
427         /* Get the process state information */
428         log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
429 
430         total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
431 
432         if (total_len) {
433                 IA64_LOG_INDEX_INC(sal_info_type);
434                 IA64_LOG_UNLOCK(sal_info_type);
435                 if (irq_safe) {
436                         IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. Record length = %ld\n",
437                                        __func__, sal_info_type, total_len);
438                 }
439                 *buffer = (u8 *) log_buffer;
440                 return total_len;
441         } else {
442                 IA64_LOG_UNLOCK(sal_info_type);
443                 return 0;
444         }
445 }
446 
447 /*
448  *  ia64_mca_log_sal_error_record
449  *
450  *  This function retrieves a specified error record type from SAL
451  *  and wakes up any processes waiting for error records.
452  *
453  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE)
454  *              FIXME: remove MCA and irq_safe.
455  */
456 static void
457 ia64_mca_log_sal_error_record(int sal_info_type)
458 {
459         u8 *buffer;
460         sal_log_record_header_t *rh;
461         u64 size;
462         int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
463 #ifdef IA64_MCA_DEBUG_INFO
464         static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
465 #endif
466 
467         size = ia64_log_get(sal_info_type, &buffer, irq_safe);
468         if (!size)
469                 return;
470 
471         salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
472 
473         if (irq_safe)
474                 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
475                         smp_processor_id(),
476                         sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
477 
478         /* Clear logs from corrected errors in case there's no user-level logger */
479         rh = (sal_log_record_header_t *)buffer;
480         if (rh->severity == sal_log_severity_corrected)
481                 ia64_sal_clear_state_info(sal_info_type);
482 }
483 
484 /*
485  * search_mca_table
486  *  See if the MCA surfaced in an instruction range
487  *  that has been tagged as recoverable.
488  *
489  *  Inputs
490  *      first   First address range to check
491  *      last    Last address range to check
492  *      ip      Instruction pointer, address we are looking for
493  *
494  * Return value:
495  *      1 on Success (in the table)/ 0 on Failure (not in the  table)
496  */
497 int
498 search_mca_table (const struct mca_table_entry *first,
499                 const struct mca_table_entry *last,
500                 unsigned long ip)
501 {
502         const struct mca_table_entry *curr;
503         u64 curr_start, curr_end;
504 
505         curr = first;
506         while (curr <= last) {
507                 curr_start = (u64) &curr->start_addr + curr->start_addr;
508                 curr_end = (u64) &curr->end_addr + curr->end_addr;
509 
510                 if ((ip >= curr_start) && (ip <= curr_end)) {
511                         return 1;
512                 }
513                 curr++;
514         }
515         return 0;
516 }
517 
518 /* Given an address, look for it in the mca tables. */
519 int mca_recover_range(unsigned long addr)
520 {
521         extern struct mca_table_entry __start___mca_table[];
522         extern struct mca_table_entry __stop___mca_table[];
523 
524         return search_mca_table(__start___mca_table, __stop___mca_table-1, addr);
525 }
526 EXPORT_SYMBOL_GPL(mca_recover_range);
527 
528 #ifdef CONFIG_ACPI
529 
530 int cpe_vector = -1;
531 int ia64_cpe_irq = -1;
532 
533 static irqreturn_t
534 ia64_mca_cpe_int_handler (int cpe_irq, void *arg)
535 {
536         static unsigned long    cpe_history[CPE_HISTORY_LENGTH];
537         static int              index;
538         static DEFINE_SPINLOCK(cpe_history_lock);
539 
540         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
541                        __func__, cpe_irq, smp_processor_id());
542 
543         /* SAL spec states this should run w/ interrupts enabled */
544         local_irq_enable();
545 
546         spin_lock(&cpe_history_lock);
547         if (!cpe_poll_enabled && cpe_vector >= 0) {
548 
549                 int i, count = 1; /* we know 1 happened now */
550                 unsigned long now = jiffies;
551 
552                 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
553                         if (now - cpe_history[i] <= HZ)
554                                 count++;
555                 }
556 
557                 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
558                 if (count >= CPE_HISTORY_LENGTH) {
559 
560                         cpe_poll_enabled = 1;
561                         spin_unlock(&cpe_history_lock);
562                         disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
563 
564                         /*
565                          * Corrected errors will still be corrected, but
566                          * make sure there's a log somewhere that indicates
567                          * something is generating more than we can handle.
568                          */
569                         printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
570 
571                         mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
572 
573                         /* lock already released, get out now */
574                         goto out;
575                 } else {
576                         cpe_history[index++] = now;
577                         if (index == CPE_HISTORY_LENGTH)
578                                 index = 0;
579                 }
580         }
581         spin_unlock(&cpe_history_lock);
582 out:
583         /* Get the CPE error record and log it */
584         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
585 
586         local_irq_disable();
587 
588         return IRQ_HANDLED;
589 }
590 
591 #endif /* CONFIG_ACPI */
592 
593 #ifdef CONFIG_ACPI
594 /*
595  * ia64_mca_register_cpev
596  *
597  *  Register the corrected platform error vector with SAL.
598  *
599  *  Inputs
600  *      cpev        Corrected Platform Error Vector number
601  *
602  *  Outputs
603  *      None
604  */
605 void
606 ia64_mca_register_cpev (int cpev)
607 {
608         /* Register the CPE interrupt vector with SAL */
609         struct ia64_sal_retval isrv;
610 
611         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
612         if (isrv.status) {
613                 printk(KERN_ERR "Failed to register Corrected Platform "
614                        "Error interrupt vector with SAL (status %ld)\n", isrv.status);
615                 return;
616         }
617 
618         IA64_MCA_DEBUG("%s: corrected platform error "
619                        "vector %#x registered\n", __func__, cpev);
620 }
621 #endif /* CONFIG_ACPI */
622 
623 /*
624  * ia64_mca_cmc_vector_setup
625  *
626  *  Setup the corrected machine check vector register in the processor.
627  *  (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
628  *  This function is invoked on a per-processor basis.
629  *
630  * Inputs
631  *      None
632  *
633  * Outputs
634  *      None
635  */
636 void
637 ia64_mca_cmc_vector_setup (void)
638 {
639         cmcv_reg_t      cmcv;
640 
641         cmcv.cmcv_regval        = 0;
642         cmcv.cmcv_mask          = 1;        /* Mask/disable interrupt at first */
643         cmcv.cmcv_vector        = IA64_CMC_VECTOR;
644         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
645 
646         IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x registered.\n",
647                        __func__, smp_processor_id(), IA64_CMC_VECTOR);
648 
649         IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
650                        __func__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
651 }
652 
653 /*
654  * ia64_mca_cmc_vector_disable
655  *
656  *  Mask the corrected machine check vector register in the processor.
657  *  This function is invoked on a per-processor basis.
658  *
659  * Inputs
660  *      dummy(unused)
661  *
662  * Outputs
663  *      None
664  */
665 static void
666 ia64_mca_cmc_vector_disable (void *dummy)
667 {
668         cmcv_reg_t      cmcv;
669 
670         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
671 
672         cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
673         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
674 
675         IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x disabled.\n",
676                        __func__, smp_processor_id(), cmcv.cmcv_vector);
677 }
678 
679 /*
680  * ia64_mca_cmc_vector_enable
681  *
682  *  Unmask the corrected machine check vector register in the processor.
683  *  This function is invoked on a per-processor basis.
684  *
685  * Inputs
686  *      dummy(unused)
687  *
688  * Outputs
689  *      None
690  */
691 static void
692 ia64_mca_cmc_vector_enable (void *dummy)
693 {
694         cmcv_reg_t      cmcv;
695 
696         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
697 
698         cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
699         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
700 
701         IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x enabled.\n",
702                        __func__, smp_processor_id(), cmcv.cmcv_vector);
703 }
704 
705 /*
706  * ia64_mca_cmc_vector_disable_keventd
707  *
708  * Called via keventd (smp_call_function() is not safe in interrupt context) to
709  * disable the cmc interrupt vector.
710  */
711 static void
712 ia64_mca_cmc_vector_disable_keventd(struct work_struct *unused)
713 {
714         on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 0);
715 }
716 
717 /*
718  * ia64_mca_cmc_vector_enable_keventd
719  *
720  * Called via keventd (smp_call_function() is not safe in interrupt context) to
721  * enable the cmc interrupt vector.
722  */
723 static void
724 ia64_mca_cmc_vector_enable_keventd(struct work_struct *unused)
725 {
726         on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 0);
727 }
728 
729 /*
730  * ia64_mca_wakeup
731  *
732  *      Send an inter-cpu interrupt to wake-up a particular cpu.
733  *
734  *  Inputs  :   cpuid
735  *  Outputs :   None
736  */
737 static void
738 ia64_mca_wakeup(int cpu)
739 {
740         platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
741 }
742 
743 /*
744  * ia64_mca_wakeup_all
745  *
746  *      Wakeup all the slave cpus which have rendez'ed previously.
747  *
748  *  Inputs  :   None
749  *  Outputs :   None
750  */
751 static void
752 ia64_mca_wakeup_all(void)
753 {
754         int cpu;
755 
756         /* Clear the Rendez checkin flag for all cpus */
757         for_each_online_cpu(cpu) {
758                 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
759                         ia64_mca_wakeup(cpu);
760         }
761 
762 }
763 
764 /*
765  * ia64_mca_rendez_interrupt_handler
766  *
767  *      This is handler used to put slave processors into spinloop
768  *      while the monarch processor does the mca handling and later
769  *      wake each slave up once the monarch is done.  The state
770  *      IA64_MCA_RENDEZ_CHECKIN_DONE indicates the cpu is rendez'ed
771  *      in SAL.  The state IA64_MCA_RENDEZ_CHECKIN_NOTDONE indicates
772  *      the cpu has come out of OS rendezvous.
773  *
774  *  Inputs  :   None
775  *  Outputs :   None
776  */
777 static irqreturn_t
778 ia64_mca_rendez_int_handler(int rendez_irq, void *arg)
779 {
780         unsigned long flags;
781         int cpu = smp_processor_id();
782         struct ia64_mca_notify_die nd =
783                 { .sos = NULL, .monarch_cpu = &monarch_cpu };
784 
785         /* Mask all interrupts */
786         local_irq_save(flags);
787 
788         NOTIFY_MCA(DIE_MCA_RENDZVOUS_ENTER, get_irq_regs(), (long)&nd, 1);
789 
790         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
791         /* Register with the SAL monarch that the slave has
792          * reached SAL
793          */
794         ia64_sal_mc_rendez();
795 
796         NOTIFY_MCA(DIE_MCA_RENDZVOUS_PROCESS, get_irq_regs(), (long)&nd, 1);
797 
798         /* Wait for the monarch cpu to exit. */
799         while (monarch_cpu != -1)
800                cpu_relax();     /* spin until monarch leaves */
801 
802         NOTIFY_MCA(DIE_MCA_RENDZVOUS_LEAVE, get_irq_regs(), (long)&nd, 1);
803 
804         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
805         /* Enable all interrupts */
806         local_irq_restore(flags);
807         return IRQ_HANDLED;
808 }
809 
810 /*
811  * ia64_mca_wakeup_int_handler
812  *
813  *      The interrupt handler for processing the inter-cpu interrupt to the
814  *      slave cpu which was spinning in the rendez loop.
815  *      Since this spinning is done by turning off the interrupts and
816  *      polling on the wakeup-interrupt bit in the IRR, there is
817  *      nothing useful to be done in the handler.
818  *
819  *  Inputs  :   wakeup_irq  (Wakeup-interrupt bit)
820  *      arg             (Interrupt handler specific argument)
821  *  Outputs :   None
822  *
823  */
824 static irqreturn_t
825 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg)
826 {
827         return IRQ_HANDLED;
828 }
829 
830 /* Function pointer for extra MCA recovery */
831 int (*ia64_mca_ucmc_extension)
832         (void*,struct ia64_sal_os_state*)
833         = NULL;
834 
835 int
836 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
837 {
838         if (ia64_mca_ucmc_extension)
839                 return 1;
840 
841         ia64_mca_ucmc_extension = fn;
842         return 0;
843 }
844 
845 void
846 ia64_unreg_MCA_extension(void)
847 {
848         if (ia64_mca_ucmc_extension)
849                 ia64_mca_ucmc_extension = NULL;
850 }
851 
852 EXPORT_SYMBOL(ia64_reg_MCA_extension);
853 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
854 
855 
856 static inline void
857 copy_reg(const u64 *fr, u64 fnat, unsigned long *tr, unsigned long *tnat)
858 {
859         u64 fslot, tslot, nat;
860         *tr = *fr;
861         fslot = ((unsigned long)fr >> 3) & 63;
862         tslot = ((unsigned long)tr >> 3) & 63;
863         *tnat &= ~(1UL << tslot);
864         nat = (fnat >> fslot) & 1;
865         *tnat |= (nat << tslot);
866 }
867 
868 /* Change the comm field on the MCA/INT task to include the pid that
869  * was interrupted, it makes for easier debugging.  If that pid was 0
870  * (swapper or nested MCA/INIT) then use the start of the previous comm
871  * field suffixed with its cpu.
872  */
873 
874 static void
875 ia64_mca_modify_comm(const struct task_struct *previous_current)
876 {
877         char *p, comm[sizeof(current->comm)];
878         if (previous_current->pid)
879                 snprintf(comm, sizeof(comm), "%s %d",
880                         current->comm, previous_current->pid);
881         else {
882                 int l;
883                 if ((p = strchr(previous_current->comm, ' ')))
884                         l = p - previous_current->comm;
885                 else
886                         l = strlen(previous_current->comm);
887                 snprintf(comm, sizeof(comm), "%s %*s %d",
888                         current->comm, l, previous_current->comm,
889                         task_thread_info(previous_current)->cpu);
890         }
891         memcpy(current->comm, comm, sizeof(current->comm));
892 }
893 
894 static void
895 finish_pt_regs(struct pt_regs *regs, struct ia64_sal_os_state *sos,
896                 unsigned long *nat)
897 {
898         const pal_min_state_area_t *ms = sos->pal_min_state;
899         const u64 *bank;
900 
901         /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
902          * pmsa_{xip,xpsr,xfs}
903          */
904         if (ia64_psr(regs)->ic) {
905                 regs->cr_iip = ms->pmsa_iip;
906                 regs->cr_ipsr = ms->pmsa_ipsr;
907                 regs->cr_ifs = ms->pmsa_ifs;
908         } else {
909                 regs->cr_iip = ms->pmsa_xip;
910                 regs->cr_ipsr = ms->pmsa_xpsr;
911                 regs->cr_ifs = ms->pmsa_xfs;
912 
913                 sos->iip = ms->pmsa_iip;
914                 sos->ipsr = ms->pmsa_ipsr;
915                 sos->ifs = ms->pmsa_ifs;
916         }
917         regs->pr = ms->pmsa_pr;
918         regs->b0 = ms->pmsa_br0;
919         regs->ar_rsc = ms->pmsa_rsc;
920         copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &regs->r1, nat);
921         copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &regs->r2, nat);
922         copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &regs->r3, nat);
923         copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &regs->r8, nat);
924         copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &regs->r9, nat);
925         copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &regs->r10, nat);
926         copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &regs->r11, nat);
927         copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &regs->r12, nat);
928         copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &regs->r13, nat);
929         copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &regs->r14, nat);
930         copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &regs->r15, nat);
931         if (ia64_psr(regs)->bn)
932                 bank = ms->pmsa_bank1_gr;
933         else
934                 bank = ms->pmsa_bank0_gr;
935         copy_reg(&bank[16-16], ms->pmsa_nat_bits, &regs->r16, nat);
936         copy_reg(&bank[17-16], ms->pmsa_nat_bits, &regs->r17, nat);
937         copy_reg(&bank[18-16], ms->pmsa_nat_bits, &regs->r18, nat);
938         copy_reg(&bank[19-16], ms->pmsa_nat_bits, &regs->r19, nat);
939         copy_reg(&bank[20-16], ms->pmsa_nat_bits, &regs->r20, nat);
940         copy_reg(&bank[21-16], ms->pmsa_nat_bits, &regs->r21, nat);
941         copy_reg(&bank[22-16], ms->pmsa_nat_bits, &regs->r22, nat);
942         copy_reg(&bank[23-16], ms->pmsa_nat_bits, &regs->r23, nat);
943         copy_reg(&bank[24-16], ms->pmsa_nat_bits, &regs->r24, nat);
944         copy_reg(&bank[25-16], ms->pmsa_nat_bits, &regs->r25, nat);
945         copy_reg(&bank[26-16], ms->pmsa_nat_bits, &regs->r26, nat);
946         copy_reg(&bank[27-16], ms->pmsa_nat_bits, &regs->r27, nat);
947         copy_reg(&bank[28-16], ms->pmsa_nat_bits, &regs->r28, nat);
948         copy_reg(&bank[29-16], ms->pmsa_nat_bits, &regs->r29, nat);
949         copy_reg(&bank[30-16], ms->pmsa_nat_bits, &regs->r30, nat);
950         copy_reg(&bank[31-16], ms->pmsa_nat_bits, &regs->r31, nat);
951 }
952 
953 /* On entry to this routine, we are running on the per cpu stack, see
954  * mca_asm.h.  The original stack has not been touched by this event.  Some of
955  * the original stack's registers will be in the RBS on this stack.  This stack
956  * also contains a partial pt_regs and switch_stack, the rest of the data is in
957  * PAL minstate.
958  *
959  * The first thing to do is modify the original stack to look like a blocked
960  * task so we can run backtrace on the original task.  Also mark the per cpu
961  * stack as current to ensure that we use the correct task state, it also means
962  * that we can do backtrace on the MCA/INIT handler code itself.
963  */
964 
965 static struct task_struct *
966 ia64_mca_modify_original_stack(struct pt_regs *regs,
967                 const struct switch_stack *sw,
968                 struct ia64_sal_os_state *sos,
969                 const char *type)
970 {
971         char *p;
972         ia64_va va;
973         extern char ia64_leave_kernel[];        /* Need asm address, not function descriptor */
974         const pal_min_state_area_t *ms = sos->pal_min_state;
975         struct task_struct *previous_current;
976         struct pt_regs *old_regs;
977         struct switch_stack *old_sw;
978         unsigned size = sizeof(struct pt_regs) +
979                         sizeof(struct switch_stack) + 16;
980         unsigned long *old_bspstore, *old_bsp;
981         unsigned long *new_bspstore, *new_bsp;
982         unsigned long old_unat, old_rnat, new_rnat, nat;
983         u64 slots, loadrs = regs->loadrs;
984         u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
985         u64 ar_bspstore = regs->ar_bspstore;
986         u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
987         const char *msg;
988         int cpu = smp_processor_id();
989 
990         previous_current = curr_task(cpu);
991         ia64_set_curr_task(cpu, current);
992         if ((p = strchr(current->comm, ' ')))
993                 *p = '\0';
994 
995         /* Best effort attempt to cope with MCA/INIT delivered while in
996          * physical mode.
997          */
998         regs->cr_ipsr = ms->pmsa_ipsr;
999         if (ia64_psr(regs)->dt == 0) {
1000                 va.l = r12;
1001                 if (va.f.reg == 0) {
1002                         va.f.reg = 7;
1003                         r12 = va.l;
1004                 }
1005                 va.l = r13;
1006                 if (va.f.reg == 0) {
1007                         va.f.reg = 7;
1008                         r13 = va.l;
1009                 }
1010         }
1011         if (ia64_psr(regs)->rt == 0) {
1012                 va.l = ar_bspstore;
1013                 if (va.f.reg == 0) {
1014                         va.f.reg = 7;
1015                         ar_bspstore = va.l;
1016                 }
1017                 va.l = ar_bsp;
1018                 if (va.f.reg == 0) {
1019                         va.f.reg = 7;
1020                         ar_bsp = va.l;
1021                 }
1022         }
1023 
1024         /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
1025          * have been copied to the old stack, the old stack may fail the
1026          * validation tests below.  So ia64_old_stack() must restore the dirty
1027          * registers from the new stack.  The old and new bspstore probably
1028          * have different alignments, so loadrs calculated on the old bsp
1029          * cannot be used to restore from the new bsp.  Calculate a suitable
1030          * loadrs for the new stack and save it in the new pt_regs, where
1031          * ia64_old_stack() can get it.
1032          */
1033         old_bspstore = (unsigned long *)ar_bspstore;
1034         old_bsp = (unsigned long *)ar_bsp;
1035         slots = ia64_rse_num_regs(old_bspstore, old_bsp);
1036         new_bspstore = (unsigned long *)((u64)current + IA64_RBS_OFFSET);
1037         new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
1038         regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
1039 
1040         /* Verify the previous stack state before we change it */
1041         if (user_mode(regs)) {
1042                 msg = "occurred in user space";
1043                 /* previous_current is guaranteed to be valid when the task was
1044                  * in user space, so ...
1045                  */
1046                 ia64_mca_modify_comm(previous_current);
1047                 goto no_mod;
1048         }
1049 
1050         if (r13 != sos->prev_IA64_KR_CURRENT) {
1051                 msg = "inconsistent previous current and r13";
1052                 goto no_mod;
1053         }
1054 
1055         if (!mca_recover_range(ms->pmsa_iip)) {
1056                 if ((r12 - r13) >= KERNEL_STACK_SIZE) {
1057                         msg = "inconsistent r12 and r13";
1058                         goto no_mod;
1059                 }
1060                 if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
1061                         msg = "inconsistent ar.bspstore and r13";
1062                         goto no_mod;
1063                 }
1064                 va.p = old_bspstore;
1065                 if (va.f.reg < 5) {
1066                         msg = "old_bspstore is in the wrong region";
1067                         goto no_mod;
1068                 }
1069                 if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
1070                         msg = "inconsistent ar.bsp and r13";
1071                         goto no_mod;
1072                 }
1073                 size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
1074                 if (ar_bspstore + size > r12) {
1075                         msg = "no room for blocked state";
1076                         goto no_mod;
1077                 }
1078         }
1079 
1080         ia64_mca_modify_comm(previous_current);
1081 
1082         /* Make the original task look blocked.  First stack a struct pt_regs,
1083          * describing the state at the time of interrupt.  mca_asm.S built a
1084          * partial pt_regs, copy it and fill in the blanks using minstate.
1085          */
1086         p = (char *)r12 - sizeof(*regs);
1087         old_regs = (struct pt_regs *)p;
1088         memcpy(old_regs, regs, sizeof(*regs));
1089         old_regs->loadrs = loadrs;
1090         old_unat = old_regs->ar_unat;
1091         finish_pt_regs(old_regs, sos, &old_unat);
1092 
1093         /* Next stack a struct switch_stack.  mca_asm.S built a partial
1094          * switch_stack, copy it and fill in the blanks using pt_regs and
1095          * minstate.
1096          *
1097          * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
1098          * ar.pfs is set to 0.
1099          *
1100          * unwind.c::unw_unwind() does special processing for interrupt frames.
1101          * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
1102          * is clear then unw_unwind() does _not_ adjust bsp over pt_regs.  Not
1103          * that this is documented, of course.  Set PRED_NON_SYSCALL in the
1104          * switch_stack on the original stack so it will unwind correctly when
1105          * unwind.c reads pt_regs.
1106          *
1107          * thread.ksp is updated to point to the synthesized switch_stack.
1108          */
1109         p -= sizeof(struct switch_stack);
1110         old_sw = (struct switch_stack *)p;
1111         memcpy(old_sw, sw, sizeof(*sw));
1112         old_sw->caller_unat = old_unat;
1113         old_sw->ar_fpsr = old_regs->ar_fpsr;
1114         copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
1115         copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
1116         copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
1117         copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
1118         old_sw->b0 = (u64)ia64_leave_kernel;
1119         old_sw->b1 = ms->pmsa_br1;
1120         old_sw->ar_pfs = 0;
1121         old_sw->ar_unat = old_unat;
1122         old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
1123         previous_current->thread.ksp = (u64)p - 16;
1124 
1125         /* Finally copy the original stack's registers back to its RBS.
1126          * Registers from ar.bspstore through ar.bsp at the time of the event
1127          * are in the current RBS, copy them back to the original stack.  The
1128          * copy must be done register by register because the original bspstore
1129          * and the current one have different alignments, so the saved RNAT
1130          * data occurs at different places.
1131          *
1132          * mca_asm does cover, so the old_bsp already includes all registers at
1133          * the time of MCA/INIT.  It also does flushrs, so all registers before
1134          * this function have been written to backing store on the MCA/INIT
1135          * stack.
1136          */
1137         new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
1138         old_rnat = regs->ar_rnat;
1139         while (slots--) {
1140                 if (ia64_rse_is_rnat_slot(new_bspstore)) {
1141                         new_rnat = ia64_get_rnat(new_bspstore++);
1142                 }
1143                 if (ia64_rse_is_rnat_slot(old_bspstore)) {
1144                         *old_bspstore++ = old_rnat;
1145                         old_rnat = 0;
1146                 }
1147                 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
1148                 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
1149                 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
1150                 *old_bspstore++ = *new_bspstore++;
1151         }
1152         old_sw->ar_bspstore = (unsigned long)old_bspstore;
1153         old_sw->ar_rnat = old_rnat;
1154 
1155         sos->prev_task = previous_current;
1156         return previous_current;
1157 
1158 no_mod:
1159         mprintk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
1160                         smp_processor_id(), type, msg);
1161         old_unat = regs->ar_unat;
1162         finish_pt_regs(regs, sos, &old_unat);
1163         return previous_current;
1164 }
1165 
1166 /* The monarch/slave interaction is based on monarch_cpu and requires that all
1167  * slaves have entered rendezvous before the monarch leaves.  If any cpu has
1168  * not entered rendezvous yet then wait a bit.  The assumption is that any
1169  * slave that has not rendezvoused after a reasonable time is never going to do
1170  * so.  In this context, slave includes cpus that respond to the MCA rendezvous
1171  * interrupt, as well as cpus that receive the INIT slave event.
1172  */
1173 
1174 static void
1175 ia64_wait_for_slaves(int monarch, const char *type)
1176 {
1177         int c, i , wait;
1178 
1179         /*
1180          * wait 5 seconds total for slaves (arbitrary)
1181          */
1182         for (i = 0; i < 5000; i++) {
1183                 wait = 0;
1184                 for_each_online_cpu(c) {
1185                         if (c == monarch)
1186                                 continue;
1187                         if (ia64_mc_info.imi_rendez_checkin[c]
1188                                         == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
1189                                 udelay(1000);           /* short wait */
1190                                 wait = 1;
1191                                 break;
1192                         }
1193                 }
1194                 if (!wait)
1195                         goto all_in;
1196         }
1197 
1198         /*
1199          * Maybe slave(s) dead. Print buffered messages immediately.
1200          */
1201         ia64_mlogbuf_finish(0);
1202         mprintk(KERN_INFO "OS %s slave did not rendezvous on cpu", type);
1203         for_each_online_cpu(c) {
1204                 if (c == monarch)
1205                         continue;
1206                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
1207                         mprintk(" %d", c);
1208         }
1209         mprintk("\n");
1210         return;
1211 
1212 all_in:
1213         mprintk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type);
1214         return;
1215 }
1216 
1217 /*  mca_insert_tr
1218  *
1219  *  Switch rid when TR reload and needed!
1220  *  iord: 1: itr, 2: itr;
1221  *
1222 */
1223 static void mca_insert_tr(u64 iord)
1224 {
1225 
1226         int i;
1227         u64 old_rr;
1228         struct ia64_tr_entry *p;
1229         unsigned long psr;
1230         int cpu = smp_processor_id();
1231 
1232         if (!ia64_idtrs[cpu])
1233                 return;
1234 
1235         psr = ia64_clear_ic();
1236         for (i = IA64_TR_ALLOC_BASE; i < IA64_TR_ALLOC_MAX; i++) {
1237                 p = ia64_idtrs[cpu] + (iord - 1) * IA64_TR_ALLOC_MAX;
1238                 if (p->pte & 0x1) {
1239                         old_rr = ia64_get_rr(p->ifa);
1240                         if (old_rr != p->rr) {
1241                                 ia64_set_rr(p->ifa, p->rr);
1242                                 ia64_srlz_d();
1243                         }
1244                         ia64_ptr(iord, p->ifa, p->itir >> 2);
1245                         ia64_srlz_i();
1246                         if (iord & 0x1) {
1247                                 ia64_itr(0x1, i, p->ifa, p->pte, p->itir >> 2);
1248                                 ia64_srlz_i();
1249                         }
1250                         if (iord & 0x2) {
1251                                 ia64_itr(0x2, i, p->ifa, p->pte, p->itir >> 2);
1252                                 ia64_srlz_i();
1253                         }
1254                         if (old_rr != p->rr) {
1255                                 ia64_set_rr(p->ifa, old_rr);
1256                                 ia64_srlz_d();
1257                         }
1258                 }
1259         }
1260         ia64_set_psr(psr);
1261 }
1262 
1263 /*
1264  * ia64_mca_handler
1265  *
1266  *      This is uncorrectable machine check handler called from OS_MCA
1267  *      dispatch code which is in turn called from SAL_CHECK().
1268  *      This is the place where the core of OS MCA handling is done.
1269  *      Right now the logs are extracted and displayed in a well-defined
1270  *      format. This handler code is supposed to be run only on the
1271  *      monarch processor. Once the monarch is done with MCA handling
1272  *      further MCA logging is enabled by clearing logs.
1273  *      Monarch also has the duty of sending wakeup-IPIs to pull the
1274  *      slave processors out of rendezvous spinloop.
1275  *
1276  *      If multiple processors call into OS_MCA, the first will become
1277  *      the monarch.  Subsequent cpus will be recorded in the mca_cpu
1278  *      bitmask.  After the first monarch has processed its MCA, it
1279  *      will wake up the next cpu in the mca_cpu bitmask and then go
1280  *      into the rendezvous loop.  When all processors have serviced
1281  *      their MCA, the last monarch frees up the rest of the processors.
1282  */
1283 void
1284 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
1285                  struct ia64_sal_os_state *sos)
1286 {
1287         int recover, cpu = smp_processor_id();
1288         struct task_struct *previous_current;
1289         struct ia64_mca_notify_die nd =
1290                 { .sos = sos, .monarch_cpu = &monarch_cpu, .data = &recover };
1291         static atomic_t mca_count;
1292         static cpumask_t mca_cpu;
1293 
1294         if (atomic_add_return(1, &mca_count) == 1) {
1295                 monarch_cpu = cpu;
1296                 sos->monarch = 1;
1297         } else {
1298                 cpumask_set_cpu(cpu, &mca_cpu);
1299                 sos->monarch = 0;
1300         }
1301         mprintk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d "
1302                 "monarch=%ld\n", sos->proc_state_param, cpu, sos->monarch);
1303 
1304         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
1305 
1306         NOTIFY_MCA(DIE_MCA_MONARCH_ENTER, regs, (long)&nd, 1);
1307 
1308         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA;
1309         if (sos->monarch) {
1310                 ia64_wait_for_slaves(cpu, "MCA");
1311 
1312                 /* Wakeup all the processors which are spinning in the
1313                  * rendezvous loop.  They will leave SAL, then spin in the OS
1314                  * with interrupts disabled until this monarch cpu leaves the
1315                  * MCA handler.  That gets control back to the OS so we can
1316                  * backtrace the other cpus, backtrace when spinning in SAL
1317                  * does not work.
1318                  */
1319                 ia64_mca_wakeup_all();
1320         } else {
1321                 while (cpumask_test_cpu(cpu, &mca_cpu))
1322                         cpu_relax();    /* spin until monarch wakes us */
1323         }
1324 
1325         NOTIFY_MCA(DIE_MCA_MONARCH_PROCESS, regs, (long)&nd, 1);
1326 
1327         /* Get the MCA error record and log it */
1328         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
1329 
1330         /* MCA error recovery */
1331         recover = (ia64_mca_ucmc_extension
1332                 && ia64_mca_ucmc_extension(
1333                         IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
1334                         sos));
1335 
1336         if (recover) {
1337                 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
1338                 rh->severity = sal_log_severity_corrected;
1339                 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
1340                 sos->os_status = IA64_MCA_CORRECTED;
1341         } else {
1342                 /* Dump buffered message to console */
1343                 ia64_mlogbuf_finish(1);
1344         }
1345 
1346         if (__this_cpu_read(ia64_mca_tr_reload)) {
1347                 mca_insert_tr(0x1); /*Reload dynamic itrs*/
1348                 mca_insert_tr(0x2); /*Reload dynamic itrs*/
1349         }
1350 
1351         NOTIFY_MCA(DIE_MCA_MONARCH_LEAVE, regs, (long)&nd, 1);
1352 
1353         if (atomic_dec_return(&mca_count) > 0) {
1354                 int i;
1355 
1356                 /* wake up the next monarch cpu,
1357                  * and put this cpu in the rendez loop.
1358                  */
1359                 for_each_online_cpu(i) {
1360                         if (cpumask_test_cpu(i, &mca_cpu)) {
1361                                 monarch_cpu = i;
1362                                 cpumask_clear_cpu(i, &mca_cpu); /* wake next cpu */
1363                                 while (monarch_cpu != -1)
1364                                         cpu_relax();    /* spin until last cpu leaves */
1365                                 ia64_set_curr_task(cpu, previous_current);
1366                                 ia64_mc_info.imi_rendez_checkin[cpu]
1367                                                 = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1368                                 return;
1369                         }
1370                 }
1371         }
1372         ia64_set_curr_task(cpu, previous_current);
1373         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1374         monarch_cpu = -1;       /* This frees the slaves and previous monarchs */
1375 }
1376 
1377 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd);
1378 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd);
1379 
1380 /*
1381  * ia64_mca_cmc_int_handler
1382  *
1383  *  This is corrected machine check interrupt handler.
1384  *      Right now the logs are extracted and displayed in a well-defined
1385  *      format.
1386  *
1387  * Inputs
1388  *      interrupt number
1389  *      client data arg ptr
1390  *
1391  * Outputs
1392  *      None
1393  */
1394 static irqreturn_t
1395 ia64_mca_cmc_int_handler(int cmc_irq, void *arg)
1396 {
1397         static unsigned long    cmc_history[CMC_HISTORY_LENGTH];
1398         static int              index;
1399         static DEFINE_SPINLOCK(cmc_history_lock);
1400 
1401         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1402                        __func__, cmc_irq, smp_processor_id());
1403 
1404         /* SAL spec states this should run w/ interrupts enabled */
1405         local_irq_enable();
1406 
1407         spin_lock(&cmc_history_lock);
1408         if (!cmc_polling_enabled) {
1409                 int i, count = 1; /* we know 1 happened now */
1410                 unsigned long now = jiffies;
1411 
1412                 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1413                         if (now - cmc_history[i] <= HZ)
1414                                 count++;
1415                 }
1416 
1417                 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1418                 if (count >= CMC_HISTORY_LENGTH) {
1419 
1420                         cmc_polling_enabled = 1;
1421                         spin_unlock(&cmc_history_lock);
1422                         /* If we're being hit with CMC interrupts, we won't
1423                          * ever execute the schedule_work() below.  Need to
1424                          * disable CMC interrupts on this processor now.
1425                          */
1426                         ia64_mca_cmc_vector_disable(NULL);
1427                         schedule_work(&cmc_disable_work);
1428 
1429                         /*
1430                          * Corrected errors will still be corrected, but
1431                          * make sure there's a log somewhere that indicates
1432                          * something is generating more than we can handle.
1433                          */
1434                         printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1435 
1436                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1437 
1438                         /* lock already released, get out now */
1439                         goto out;
1440                 } else {
1441                         cmc_history[index++] = now;
1442                         if (index == CMC_HISTORY_LENGTH)
1443                                 index = 0;
1444                 }
1445         }
1446         spin_unlock(&cmc_history_lock);
1447 out:
1448         /* Get the CMC error record and log it */
1449         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1450 
1451         local_irq_disable();
1452 
1453         return IRQ_HANDLED;
1454 }
1455 
1456 /*
1457  *  ia64_mca_cmc_int_caller
1458  *
1459  *      Triggered by sw interrupt from CMC polling routine.  Calls
1460  *      real interrupt handler and either triggers a sw interrupt
1461  *      on the next cpu or does cleanup at the end.
1462  *
1463  * Inputs
1464  *      interrupt number
1465  *      client data arg ptr
1466  * Outputs
1467  *      handled
1468  */
1469 static irqreturn_t
1470 ia64_mca_cmc_int_caller(int cmc_irq, void *arg)
1471 {
1472         static int start_count = -1;
1473         unsigned int cpuid;
1474 
1475         cpuid = smp_processor_id();
1476 
1477         /* If first cpu, update count */
1478         if (start_count == -1)
1479                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1480 
1481         ia64_mca_cmc_int_handler(cmc_irq, arg);
1482 
1483         cpuid = cpumask_next(cpuid+1, cpu_online_mask);
1484 
1485         if (cpuid < nr_cpu_ids) {
1486                 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1487         } else {
1488                 /* If no log record, switch out of polling mode */
1489                 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1490 
1491                         printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1492                         schedule_work(&cmc_enable_work);
1493                         cmc_polling_enabled = 0;
1494 
1495                 } else {
1496 
1497                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1498                 }
1499 
1500                 start_count = -1;
1501         }
1502 
1503         return IRQ_HANDLED;
1504 }
1505 
1506 /*
1507  *  ia64_mca_cmc_poll
1508  *
1509  *      Poll for Corrected Machine Checks (CMCs)
1510  *
1511  * Inputs   :   dummy(unused)
1512  * Outputs  :   None
1513  *
1514  */
1515 static void
1516 ia64_mca_cmc_poll (unsigned long dummy)
1517 {
1518         /* Trigger a CMC interrupt cascade  */
1519         platform_send_ipi(cpumask_first(cpu_online_mask), IA64_CMCP_VECTOR,
1520                                                         IA64_IPI_DM_INT, 0);
1521 }
1522 
1523 /*
1524  *  ia64_mca_cpe_int_caller
1525  *
1526  *      Triggered by sw interrupt from CPE polling routine.  Calls
1527  *      real interrupt handler and either triggers a sw interrupt
1528  *      on the next cpu or does cleanup at the end.
1529  *
1530  * Inputs
1531  *      interrupt number
1532  *      client data arg ptr
1533  * Outputs
1534  *      handled
1535  */
1536 #ifdef CONFIG_ACPI
1537 
1538 static irqreturn_t
1539 ia64_mca_cpe_int_caller(int cpe_irq, void *arg)
1540 {
1541         static int start_count = -1;
1542         static int poll_time = MIN_CPE_POLL_INTERVAL;
1543         unsigned int cpuid;
1544 
1545         cpuid = smp_processor_id();
1546 
1547         /* If first cpu, update count */
1548         if (start_count == -1)
1549                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1550 
1551         ia64_mca_cpe_int_handler(cpe_irq, arg);
1552 
1553         cpuid = cpumask_next(cpuid+1, cpu_online_mask);
1554 
1555         if (cpuid < NR_CPUS) {
1556                 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1557         } else {
1558                 /*
1559                  * If a log was recorded, increase our polling frequency,
1560                  * otherwise, backoff or return to interrupt mode.
1561                  */
1562                 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1563                         poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1564                 } else if (cpe_vector < 0) {
1565                         poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1566                 } else {
1567                         poll_time = MIN_CPE_POLL_INTERVAL;
1568 
1569                         printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1570                         enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1571                         cpe_poll_enabled = 0;
1572                 }
1573 
1574                 if (cpe_poll_enabled)
1575                         mod_timer(&cpe_poll_timer, jiffies + poll_time);
1576                 start_count = -1;
1577         }
1578 
1579         return IRQ_HANDLED;
1580 }
1581 
1582 /*
1583  *  ia64_mca_cpe_poll
1584  *
1585  *      Poll for Corrected Platform Errors (CPEs), trigger interrupt
1586  *      on first cpu, from there it will trickle through all the cpus.
1587  *
1588  * Inputs   :   dummy(unused)
1589  * Outputs  :   None
1590  *
1591  */
1592 static void
1593 ia64_mca_cpe_poll (unsigned long dummy)
1594 {
1595         /* Trigger a CPE interrupt cascade  */
1596         platform_send_ipi(cpumask_first(cpu_online_mask), IA64_CPEP_VECTOR,
1597                                                         IA64_IPI_DM_INT, 0);
1598 }
1599 
1600 #endif /* CONFIG_ACPI */
1601 
1602 static int
1603 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
1604 {
1605         int c;
1606         struct task_struct *g, *t;
1607         if (val != DIE_INIT_MONARCH_PROCESS)
1608                 return NOTIFY_DONE;
1609 #ifdef CONFIG_KEXEC
1610         if (atomic_read(&kdump_in_progress))
1611                 return NOTIFY_DONE;
1612 #endif
1613 
1614         /*
1615          * FIXME: mlogbuf will brim over with INIT stack dumps.
1616          * To enable show_stack from INIT, we use oops_in_progress which should
1617          * be used in real oops. This would cause something wrong after INIT.
1618          */
1619         BREAK_LOGLEVEL(console_loglevel);
1620         ia64_mlogbuf_dump_from_init();
1621 
1622         printk(KERN_ERR "Processes interrupted by INIT -");
1623         for_each_online_cpu(c) {
1624                 struct ia64_sal_os_state *s;
1625                 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1626                 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1627                 g = s->prev_task;
1628                 if (g) {
1629                         if (g->pid)
1630                                 printk(" %d", g->pid);
1631                         else
1632                                 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1633                 }
1634         }
1635         printk("\n\n");
1636         if (read_trylock(&tasklist_lock)) {
1637                 do_each_thread (g, t) {
1638                         printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1639                         show_stack(t, NULL);
1640                 } while_each_thread (g, t);
1641                 read_unlock(&tasklist_lock);
1642         }
1643         /* FIXME: This will not restore zapped printk locks. */
1644         RESTORE_LOGLEVEL(console_loglevel);
1645         return NOTIFY_DONE;
1646 }
1647 
1648 /*
1649  * C portion of the OS INIT handler
1650  *
1651  * Called from ia64_os_init_dispatch
1652  *
1653  * Inputs: pointer to pt_regs where processor info was saved.  SAL/OS state for
1654  * this event.  This code is used for both monarch and slave INIT events, see
1655  * sos->monarch.
1656  *
1657  * All INIT events switch to the INIT stack and change the previous process to
1658  * blocked status.  If one of the INIT events is the monarch then we are
1659  * probably processing the nmi button/command.  Use the monarch cpu to dump all
1660  * the processes.  The slave INIT events all spin until the monarch cpu
1661  * returns.  We can also get INIT slave events for MCA, in which case the MCA
1662  * process is the monarch.
1663  */
1664 
1665 void
1666 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1667                   struct ia64_sal_os_state *sos)
1668 {
1669         static atomic_t slaves;
1670         static atomic_t monarchs;
1671         struct task_struct *previous_current;
1672         int cpu = smp_processor_id();
1673         struct ia64_mca_notify_die nd =
1674                 { .sos = sos, .monarch_cpu = &monarch_cpu };
1675 
1676         NOTIFY_INIT(DIE_INIT_ENTER, regs, (long)&nd, 0);
1677 
1678         mprintk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1679                 sos->proc_state_param, cpu, sos->monarch);
1680         salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1681 
1682         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1683         sos->os_status = IA64_INIT_RESUME;
1684 
1685         /* FIXME: Workaround for broken proms that drive all INIT events as
1686          * slaves.  The last slave that enters is promoted to be a monarch.
1687          * Remove this code in September 2006, that gives platforms a year to
1688          * fix their proms and get their customers updated.
1689          */
1690         if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1691                 mprintk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1692                         __func__, cpu);
1693                 atomic_dec(&slaves);
1694                 sos->monarch = 1;
1695         }
1696 
1697         /* FIXME: Workaround for broken proms that drive all INIT events as
1698          * monarchs.  Second and subsequent monarchs are demoted to slaves.
1699          * Remove this code in September 2006, that gives platforms a year to
1700          * fix their proms and get their customers updated.
1701          */
1702         if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1703                 mprintk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1704                                __func__, cpu);
1705                 atomic_dec(&monarchs);
1706                 sos->monarch = 0;
1707         }
1708 
1709         if (!sos->monarch) {
1710                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1711 
1712 #ifdef CONFIG_KEXEC
1713                 while (monarch_cpu == -1 && !atomic_read(&kdump_in_progress))
1714                         udelay(1000);
1715 #else
1716                 while (monarch_cpu == -1)
1717                         cpu_relax();    /* spin until monarch enters */
1718 #endif
1719 
1720                 NOTIFY_INIT(DIE_INIT_SLAVE_ENTER, regs, (long)&nd, 1);
1721                 NOTIFY_INIT(DIE_INIT_SLAVE_PROCESS, regs, (long)&nd, 1);
1722 
1723 #ifdef CONFIG_KEXEC
1724                 while (monarch_cpu != -1 && !atomic_read(&kdump_in_progress))
1725                         udelay(1000);
1726 #else
1727                 while (monarch_cpu != -1)
1728                         cpu_relax();    /* spin until monarch leaves */
1729 #endif
1730 
1731                 NOTIFY_INIT(DIE_INIT_SLAVE_LEAVE, regs, (long)&nd, 1);
1732 
1733                 mprintk("Slave on cpu %d returning to normal service.\n", cpu);
1734                 ia64_set_curr_task(cpu, previous_current);
1735                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1736                 atomic_dec(&slaves);
1737                 return;
1738         }
1739 
1740         monarch_cpu = cpu;
1741         NOTIFY_INIT(DIE_INIT_MONARCH_ENTER, regs, (long)&nd, 1);
1742 
1743         /*
1744          * Wait for a bit.  On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1745          * generated via the BMC's command-line interface, but since the console is on the
1746          * same serial line, the user will need some time to switch out of the BMC before
1747          * the dump begins.
1748          */
1749         mprintk("Delaying for 5 seconds...\n");
1750         udelay(5*1000000);
1751         ia64_wait_for_slaves(cpu, "INIT");
1752         /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1753          * to default_monarch_init_process() above and just print all the
1754          * tasks.
1755          */
1756         NOTIFY_INIT(DIE_INIT_MONARCH_PROCESS, regs, (long)&nd, 1);
1757         NOTIFY_INIT(DIE_INIT_MONARCH_LEAVE, regs, (long)&nd, 1);
1758 
1759         mprintk("\nINIT dump complete.  Monarch on cpu %d returning to normal service.\n", cpu);
1760         atomic_dec(&monarchs);
1761         ia64_set_curr_task(cpu, previous_current);
1762         monarch_cpu = -1;
1763         return;
1764 }
1765 
1766 static int __init
1767 ia64_mca_disable_cpe_polling(char *str)
1768 {
1769         cpe_poll_enabled = 0;
1770         return 1;
1771 }
1772 
1773 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1774 
1775 static struct irqaction cmci_irqaction = {
1776         .handler =      ia64_mca_cmc_int_handler,
1777         .name =         "cmc_hndlr"
1778 };
1779 
1780 static struct irqaction cmcp_irqaction = {
1781         .handler =      ia64_mca_cmc_int_caller,
1782         .name =         "cmc_poll"
1783 };
1784 
1785 static struct irqaction mca_rdzv_irqaction = {
1786         .handler =      ia64_mca_rendez_int_handler,
1787         .name =         "mca_rdzv"
1788 };
1789 
1790 static struct irqaction mca_wkup_irqaction = {
1791         .handler =      ia64_mca_wakeup_int_handler,
1792         .name =         "mca_wkup"
1793 };
1794 
1795 #ifdef CONFIG_ACPI
1796 static struct irqaction mca_cpe_irqaction = {
1797         .handler =      ia64_mca_cpe_int_handler,
1798         .name =         "cpe_hndlr"
1799 };
1800 
1801 static struct irqaction mca_cpep_irqaction = {
1802         .handler =      ia64_mca_cpe_int_caller,
1803         .name =         "cpe_poll"
1804 };
1805 #endif /* CONFIG_ACPI */
1806 
1807 /* Minimal format of the MCA/INIT stacks.  The pseudo processes that run on
1808  * these stacks can never sleep, they cannot return from the kernel to user
1809  * space, they do not appear in a normal ps listing.  So there is no need to
1810  * format most of the fields.
1811  */
1812 
1813 static void
1814 format_mca_init_stack(void *mca_data, unsigned long offset,
1815                 const char *type, int cpu)
1816 {
1817         struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1818         struct thread_info *ti;
1819         memset(p, 0, KERNEL_STACK_SIZE);
1820         ti = task_thread_info(p);
1821         ti->flags = _TIF_MCA_INIT;
1822         ti->preempt_count = 1;
1823         ti->task = p;
1824         ti->cpu = cpu;
1825         p->stack = ti;
1826         p->state = TASK_UNINTERRUPTIBLE;
1827         cpumask_set_cpu(cpu, &p->cpus_allowed);
1828         INIT_LIST_HEAD(&p->tasks);
1829         p->parent = p->real_parent = p->group_leader = p;
1830         INIT_LIST_HEAD(&p->children);
1831         INIT_LIST_HEAD(&p->sibling);
1832         strncpy(p->comm, type, sizeof(p->comm)-1);
1833 }
1834 
1835 /* Caller prevents this from being called after init */
1836 static void * __ref mca_bootmem(void)
1837 {
1838         return __alloc_bootmem(sizeof(struct ia64_mca_cpu),
1839                             KERNEL_STACK_SIZE, 0);
1840 }
1841 
1842 /* Do per-CPU MCA-related initialization.  */
1843 void
1844 ia64_mca_cpu_init(void *cpu_data)
1845 {
1846         void *pal_vaddr;
1847         void *data;
1848         long sz = sizeof(struct ia64_mca_cpu);
1849         int cpu = smp_processor_id();
1850         static int first_time = 1;
1851 
1852         /*
1853          * Structure will already be allocated if cpu has been online,
1854          * then offlined.
1855          */
1856         if (__per_cpu_mca[cpu]) {
1857                 data = __va(__per_cpu_mca[cpu]);
1858         } else {
1859                 if (first_time) {
1860                         data = mca_bootmem();
1861                         first_time = 0;
1862                 } else
1863                         data = (void *)__get_free_pages(GFP_KERNEL,
1864                                                         get_order(sz));
1865                 if (!data)
1866                         panic("Could not allocate MCA memory for cpu %d\n",
1867                                         cpu);
1868         }
1869         format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, mca_stack),
1870                 "MCA", cpu);
1871         format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, init_stack),
1872                 "INIT", cpu);
1873         __this_cpu_write(ia64_mca_data, (__per_cpu_mca[cpu] = __pa(data)));
1874 
1875         /*
1876          * Stash away a copy of the PTE needed to map the per-CPU page.
1877          * We may need it during MCA recovery.
1878          */
1879         __this_cpu_write(ia64_mca_per_cpu_pte,
1880                 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL)));
1881 
1882         /*
1883          * Also, stash away a copy of the PAL address and the PTE
1884          * needed to map it.
1885          */
1886         pal_vaddr = efi_get_pal_addr();
1887         if (!pal_vaddr)
1888                 return;
1889         __this_cpu_write(ia64_mca_pal_base,
1890                 GRANULEROUNDDOWN((unsigned long) pal_vaddr));
1891         __this_cpu_write(ia64_mca_pal_pte, pte_val(mk_pte_phys(__pa(pal_vaddr),
1892                                                               PAGE_KERNEL)));
1893 }
1894 
1895 static int ia64_mca_cpu_online(unsigned int cpu)
1896 {
1897         unsigned long flags;
1898 
1899         local_irq_save(flags);
1900         if (!cmc_polling_enabled)
1901                 ia64_mca_cmc_vector_enable(NULL);
1902         local_irq_restore(flags);
1903         return 0;
1904 }
1905 
1906 /*
1907  * ia64_mca_init
1908  *
1909  *  Do all the system level mca specific initialization.
1910  *
1911  *      1. Register spinloop and wakeup request interrupt vectors
1912  *
1913  *      2. Register OS_MCA handler entry point
1914  *
1915  *      3. Register OS_INIT handler entry point
1916  *
1917  *  4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1918  *
1919  *  Note that this initialization is done very early before some kernel
1920  *  services are available.
1921  *
1922  *  Inputs  :   None
1923  *
1924  *  Outputs :   None
1925  */
1926 void __init
1927 ia64_mca_init(void)
1928 {
1929         ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1930         ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1931         ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1932         int i;
1933         long rc;
1934         struct ia64_sal_retval isrv;
1935         unsigned long timeout = IA64_MCA_RENDEZ_TIMEOUT; /* platform specific */
1936         static struct notifier_block default_init_monarch_nb = {
1937                 .notifier_call = default_monarch_init_process,
1938                 .priority = 0/* we need to notified last */
1939         };
1940 
1941         IA64_MCA_DEBUG("%s: begin\n", __func__);
1942 
1943         /* Clear the Rendez checkin flag for all cpus */
1944         for(i = 0 ; i < NR_CPUS; i++)
1945                 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1946 
1947         /*
1948          * Register the rendezvous spinloop and wakeup mechanism with SAL
1949          */
1950 
1951         /* Register the rendezvous interrupt vector with SAL */
1952         while (1) {
1953                 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1954                                               SAL_MC_PARAM_MECHANISM_INT,
1955                                               IA64_MCA_RENDEZ_VECTOR,
1956                                               timeout,
1957                                               SAL_MC_PARAM_RZ_ALWAYS);
1958                 rc = isrv.status;
1959                 if (rc == 0)
1960                         break;
1961                 if (rc == -2) {
1962                         printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1963                                 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1964                         timeout = isrv.v0;
1965                         NOTIFY_MCA(DIE_MCA_NEW_TIMEOUT, NULL, timeout, 0);
1966                         continue;
1967                 }
1968                 printk(KERN_ERR "Failed to register rendezvous interrupt "
1969                        "with SAL (status %ld)\n", rc);
1970                 return;
1971         }
1972 
1973         /* Register the wakeup interrupt vector with SAL */
1974         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1975                                       SAL_MC_PARAM_MECHANISM_INT,
1976                                       IA64_MCA_WAKEUP_VECTOR,
1977                                       0, 0);
1978         rc = isrv.status;
1979         if (rc) {
1980                 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1981                        "(status %ld)\n", rc);
1982                 return;
1983         }
1984 
1985         IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __func__);
1986 
1987         ia64_mc_info.imi_mca_handler        = ia64_tpa(mca_hldlr_ptr->fp);
1988         /*
1989          * XXX - disable SAL checksum by setting size to 0; should be
1990          *      ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1991          */
1992         ia64_mc_info.imi_mca_handler_size       = 0;
1993 
1994         /* Register the os mca handler with SAL */
1995         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1996                                        ia64_mc_info.imi_mca_handler,
1997                                        ia64_tpa(mca_hldlr_ptr->gp),
1998                                        ia64_mc_info.imi_mca_handler_size,
1999                                        0, 0, 0)))
2000         {
2001                 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
2002                        "(status %ld)\n", rc);
2003                 return;
2004         }
2005 
2006         IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __func__,
2007                        ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
2008 
2009         /*
2010          * XXX - disable SAL checksum by setting size to 0, should be
2011          * size of the actual init handler in mca_asm.S.
2012          */
2013         ia64_mc_info.imi_monarch_init_handler           = ia64_tpa(init_hldlr_ptr_monarch->fp);
2014         ia64_mc_info.imi_monarch_init_handler_size      = 0;
2015         ia64_mc_info.imi_slave_init_handler             = ia64_tpa(init_hldlr_ptr_slave->fp);
2016         ia64_mc_info.imi_slave_init_handler_size        = 0;
2017 
2018         IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __func__,
2019                        ia64_mc_info.imi_monarch_init_handler);
2020 
2021         /* Register the os init handler with SAL */
2022         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
2023                                        ia64_mc_info.imi_monarch_init_handler,
2024                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
2025                                        ia64_mc_info.imi_monarch_init_handler_size,
2026                                        ia64_mc_info.imi_slave_init_handler,
2027                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
2028                                        ia64_mc_info.imi_slave_init_handler_size)))
2029         {
2030                 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
2031                        "(status %ld)\n", rc);
2032                 return;
2033         }
2034         if (register_die_notifier(&default_init_monarch_nb)) {
2035                 printk(KERN_ERR "Failed to register default monarch INIT process\n");
2036                 return;
2037         }
2038 
2039         IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __func__);
2040 
2041         /* Initialize the areas set aside by the OS to buffer the
2042          * platform/processor error states for MCA/INIT/CMC
2043          * handling.
2044          */
2045         ia64_log_init(SAL_INFO_TYPE_MCA);
2046         ia64_log_init(SAL_INFO_TYPE_INIT);
2047         ia64_log_init(SAL_INFO_TYPE_CMC);
2048         ia64_log_init(SAL_INFO_TYPE_CPE);
2049 
2050         mca_init = 1;
2051         printk(KERN_INFO "MCA related initialization done\n");
2052 }
2053 
2054 
2055 /*
2056  * These pieces cannot be done in ia64_mca_init() because it is called before
2057  * early_irq_init() which would wipe out our percpu irq registrations. But we
2058  * cannot leave them until ia64_mca_late_init() because by then all the other
2059  * processors have been brought online and have set their own CMC vectors to
2060  * point at a non-existant action. Called from arch_early_irq_init().
2061  */
2062 void __init ia64_mca_irq_init(void)
2063 {
2064         /*
2065          *  Configure the CMCI/P vector and handler. Interrupts for CMC are
2066          *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
2067          */
2068         register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
2069         register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
2070         ia64_mca_cmc_vector_setup();       /* Setup vector on BSP */
2071 
2072         /* Setup the MCA rendezvous interrupt vector */
2073         register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
2074 
2075         /* Setup the MCA wakeup interrupt vector */
2076         register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
2077 
2078 #ifdef CONFIG_ACPI
2079         /* Setup the CPEI/P handler */
2080         register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
2081 #endif
2082 }
2083 
2084 /*
2085  * ia64_mca_late_init
2086  *
2087  *      Opportunity to setup things that require initialization later
2088  *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
2089  *      platform doesn't support an interrupt driven mechanism.
2090  *
2091  *  Inputs  :   None
2092  *  Outputs :   Status
2093  */
2094 static int __init
2095 ia64_mca_late_init(void)
2096 {
2097         if (!mca_init)
2098                 return 0;
2099 
2100         /* Setup the CMCI/P vector and handler */
2101         setup_timer(&cmc_poll_timer, ia64_mca_cmc_poll, 0UL);
2102 
2103         /* Unmask/enable the vector */
2104         cmc_polling_enabled = 0;
2105         cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "ia64/mca:online",
2106                           ia64_mca_cpu_online, NULL);
2107         IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __func__);
2108 
2109 #ifdef CONFIG_ACPI
2110         /* Setup the CPEI/P vector and handler */
2111         cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
2112         setup_timer(&cpe_poll_timer, ia64_mca_cpe_poll, 0UL);
2113 
2114         {
2115                 unsigned int irq;
2116 
2117                 if (cpe_vector >= 0) {
2118                         /* If platform supports CPEI, enable the irq. */
2119                         irq = local_vector_to_irq(cpe_vector);
2120                         if (irq > 0) {
2121                                 cpe_poll_enabled = 0;
2122                                 irq_set_status_flags(irq, IRQ_PER_CPU);
2123                                 setup_irq(irq, &mca_cpe_irqaction);
2124                                 ia64_cpe_irq = irq;
2125                                 ia64_mca_register_cpev(cpe_vector);
2126                                 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n",
2127                                         __func__);
2128                                 return 0;
2129                         }
2130                         printk(KERN_ERR "%s: Failed to find irq for CPE "
2131                                         "interrupt handler, vector %d\n",
2132                                         __func__, cpe_vector);
2133                 }
2134                 /* If platform doesn't support CPEI, get the timer going. */
2135                 if (cpe_poll_enabled) {
2136                         ia64_mca_cpe_poll(0UL);
2137                         IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __func__);
2138                 }
2139         }
2140 #endif
2141 
2142         return 0;
2143 }
2144 
2145 device_initcall(ia64_mca_late_init);
2146 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp