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Linux/arch/m68k/coldfire/m520x.c

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  1 /***************************************************************************/
  2 
  3 /*
  4  *  m520x.c  -- platform support for ColdFire 520x based boards
  5  *
  6  *  Copyright (C) 2005,      Freescale (www.freescale.com)
  7  *  Copyright (C) 2005,      Intec Automation (mike@steroidmicros.com)
  8  *  Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
  9  *  Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
 10  */
 11 
 12 /***************************************************************************/
 13 
 14 #include <linux/kernel.h>
 15 #include <linux/param.h>
 16 #include <linux/init.h>
 17 #include <linux/io.h>
 18 #include <asm/machdep.h>
 19 #include <asm/coldfire.h>
 20 #include <asm/mcfsim.h>
 21 #include <asm/mcfuart.h>
 22 #include <asm/mcfclk.h>
 23 
 24 /***************************************************************************/
 25 
 26 DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
 27 DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
 28 DEFINE_CLK(0, "edma", 17, MCF_CLK);
 29 DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
 30 DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
 31 DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
 32 DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
 33 DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
 34 DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
 35 DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
 36 DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
 37 DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
 38 DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
 39 DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
 40 
 41 DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
 42 DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
 43 DEFINE_CLK(0, "mcfeport.0", 34, MCF_CLK);
 44 DEFINE_CLK(0, "mcfwdt.0", 35, MCF_CLK);
 45 DEFINE_CLK(0, "pll.0", 36, MCF_CLK);
 46 DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
 47 DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
 48 DEFINE_CLK(0, "sdram.0", 42, MCF_CLK);
 49 
 50 struct clk *mcf_clks[] = {
 51         &__clk_0_2, /* flexbus */
 52         &__clk_0_12, /* fec.0 */
 53         &__clk_0_17, /* edma */
 54         &__clk_0_18, /* intc.0 */
 55         &__clk_0_21, /* iack.0 */
 56         &__clk_0_22, /* mcfi2c.0 */
 57         &__clk_0_23, /* mcfqspi.0 */
 58         &__clk_0_24, /* mcfuart.0 */
 59         &__clk_0_25, /* mcfuart.1 */
 60         &__clk_0_26, /* mcfuart.2 */
 61         &__clk_0_28, /* mcftmr.0 */
 62         &__clk_0_29, /* mcftmr.1 */
 63         &__clk_0_30, /* mcftmr.2 */
 64         &__clk_0_31, /* mcftmr.3 */
 65 
 66         &__clk_0_32, /* mcfpit.0 */
 67         &__clk_0_33, /* mcfpit.1 */
 68         &__clk_0_34, /* mcfeport.0 */
 69         &__clk_0_35, /* mcfwdt.0 */
 70         &__clk_0_36, /* pll.0 */
 71         &__clk_0_40, /* sys.0 */
 72         &__clk_0_41, /* gpio.0 */
 73         &__clk_0_42, /* sdram.0 */
 74 NULL,
 75 };
 76 
 77 static struct clk * const enable_clks[] __initconst = {
 78         &__clk_0_2, /* flexbus */
 79         &__clk_0_18, /* intc.0 */
 80         &__clk_0_21, /* iack.0 */
 81         &__clk_0_24, /* mcfuart.0 */
 82         &__clk_0_25, /* mcfuart.1 */
 83         &__clk_0_26, /* mcfuart.2 */
 84 
 85         &__clk_0_32, /* mcfpit.0 */
 86         &__clk_0_33, /* mcfpit.1 */
 87         &__clk_0_34, /* mcfeport.0 */
 88         &__clk_0_36, /* pll.0 */
 89         &__clk_0_40, /* sys.0 */
 90         &__clk_0_41, /* gpio.0 */
 91         &__clk_0_42, /* sdram.0 */
 92 };
 93 
 94 static struct clk * const disable_clks[] __initconst = {
 95         &__clk_0_12, /* fec.0 */
 96         &__clk_0_17, /* edma */
 97         &__clk_0_22, /* mcfi2c.0 */
 98         &__clk_0_23, /* mcfqspi.0 */
 99         &__clk_0_28, /* mcftmr.0 */
100         &__clk_0_29, /* mcftmr.1 */
101         &__clk_0_30, /* mcftmr.2 */
102         &__clk_0_31, /* mcftmr.3 */
103         &__clk_0_35, /* mcfwdt.0 */
104 };
105 
106 
107 static void __init m520x_clk_init(void)
108 {
109         unsigned i;
110 
111         /* make sure these clocks are enabled */
112         for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
113                 __clk_init_enabled(enable_clks[i]);
114         /* make sure these clocks are disabled */
115         for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
116                 __clk_init_disabled(disable_clks[i]);
117 }
118 
119 /***************************************************************************/
120 
121 static void __init m520x_qspi_init(void)
122 {
123 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
124         u16 par;
125         /* setup Port QS for QSPI with gpio CS control */
126         writeb(0x3f, MCF_GPIO_PAR_QSPI);
127         /* make U1CTS and U2RTS gpio for cs_control */
128         par = readw(MCF_GPIO_PAR_UART);
129         par &= 0x00ff;
130         writew(par, MCF_GPIO_PAR_UART);
131 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
132 }
133 
134 /***************************************************************************/
135 
136 static void __init m520x_uarts_init(void)
137 {
138         u16 par;
139         u8 par2;
140 
141         /* UART0 and UART1 GPIO pin setup */
142         par = readw(MCF_GPIO_PAR_UART);
143         par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
144         par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
145         writew(par, MCF_GPIO_PAR_UART);
146 
147         /* UART1 GPIO pin setup */
148         par2 = readb(MCF_GPIO_PAR_FECI2C);
149         par2 &= ~0x0F;
150         par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
151                 MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
152         writeb(par2, MCF_GPIO_PAR_FECI2C);
153 }
154 
155 /***************************************************************************/
156 
157 static void __init m520x_fec_init(void)
158 {
159         u8 v;
160 
161         /* Set multi-function pins to ethernet mode */
162         v = readb(MCF_GPIO_PAR_FEC);
163         writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
164 
165         v = readb(MCF_GPIO_PAR_FECI2C);
166         writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
167 }
168 
169 /***************************************************************************/
170 
171 void __init config_BSP(char *commandp, int size)
172 {
173         mach_sched_init = hw_timer_init;
174         m520x_clk_init();
175         m520x_uarts_init();
176         m520x_fec_init();
177         m520x_qspi_init();
178 }
179 
180 /***************************************************************************/
181 

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