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Linux/arch/m68k/coldfire/m525x.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 /***************************************************************************/
  3 
  4 /*
  5  *      525x.c  -- platform support for ColdFire 525x based boards
  6  *
  7  *      Copyright (C) 2012, Steven King <sfking@fdwdc.com>
  8  */
  9 
 10 /***************************************************************************/
 11 
 12 #include <linux/kernel.h>
 13 #include <linux/param.h>
 14 #include <linux/init.h>
 15 #include <linux/io.h>
 16 #include <linux/platform_device.h>
 17 #include <asm/machdep.h>
 18 #include <asm/coldfire.h>
 19 #include <asm/mcfsim.h>
 20 #include <asm/mcfclk.h>
 21 
 22 /***************************************************************************/
 23 
 24 DEFINE_CLK(pll, "pll.0", MCF_CLK);
 25 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
 26 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
 27 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
 28 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
 29 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
 30 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
 31 DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
 32 DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
 33 
 34 struct clk *mcf_clks[] = {
 35         &clk_pll,
 36         &clk_sys,
 37         &clk_mcftmr0,
 38         &clk_mcftmr1,
 39         &clk_mcfuart0,
 40         &clk_mcfuart1,
 41         &clk_mcfqspi0,
 42         &clk_mcfi2c0,
 43         &clk_mcfi2c1,
 44         NULL
 45 };
 46 
 47 /***************************************************************************/
 48 
 49 static void __init m525x_qspi_init(void)
 50 {
 51 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
 52         /* set the GPIO function for the qspi cs gpios */
 53         /* FIXME: replace with pinmux/pinctl support */
 54         u32 f = readl(MCFSIM2_GPIOFUNC);
 55         f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
 56         writel(f, MCFSIM2_GPIOFUNC);
 57 
 58         /* QSPI irq setup */
 59         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
 60                MCFSIM_QSPIICR);
 61         mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
 62 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
 63 }
 64 
 65 static void __init m525x_i2c_init(void)
 66 {
 67 #if IS_ENABLED(CONFIG_I2C_IMX)
 68         u32 r;
 69 
 70         /* first I2C controller uses regular irq setup */
 71         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
 72                MCFSIM_I2CICR);
 73         mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
 74 
 75         /* second I2C controller is completely different */
 76         r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
 77         r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
 78         r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
 79         writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
 80 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
 81 }
 82 
 83 /***************************************************************************/
 84 
 85 void __init config_BSP(char *commandp, int size)
 86 {
 87         mach_sched_init = hw_timer_init;
 88 
 89         m525x_qspi_init();
 90         m525x_i2c_init();
 91 }
 92 
 93 /***************************************************************************/
 94 

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