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Linux/arch/m68k/coldfire/m54xx.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 /***************************************************************************/
  3 
  4 /*
  5  *      m54xx.c  -- platform support for ColdFire 54xx based boards
  6  *
  7  *      Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
  8  */
  9 
 10 /***************************************************************************/
 11 
 12 #include <linux/kernel.h>
 13 #include <linux/param.h>
 14 #include <linux/init.h>
 15 #include <linux/interrupt.h>
 16 #include <linux/io.h>
 17 #include <linux/mm.h>
 18 #include <linux/clk.h>
 19 #include <linux/memblock.h>
 20 #include <asm/pgalloc.h>
 21 #include <asm/machdep.h>
 22 #include <asm/coldfire.h>
 23 #include <asm/m54xxsim.h>
 24 #include <asm/mcfuart.h>
 25 #include <asm/mcfclk.h>
 26 #include <asm/m54xxgpt.h>
 27 #ifdef CONFIG_MMU
 28 #include <asm/mmu_context.h>
 29 #endif
 30 
 31 /***************************************************************************/
 32 
 33 DEFINE_CLK(pll, "pll.0", MCF_CLK);
 34 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
 35 DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK);
 36 DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK);
 37 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
 38 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
 39 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
 40 DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
 41 DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
 42 
 43 struct clk *mcf_clks[] = {
 44         &clk_pll,
 45         &clk_sys,
 46         &clk_mcfslt0,
 47         &clk_mcfslt1,
 48         &clk_mcfuart0,
 49         &clk_mcfuart1,
 50         &clk_mcfuart2,
 51         &clk_mcfuart3,
 52         &clk_mcfi2c0,
 53         NULL
 54 };
 55 
 56 /***************************************************************************/
 57 
 58 static void __init m54xx_uarts_init(void)
 59 {
 60         /* enable io pins */
 61         __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
 62         __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
 63                 MCFGPIO_PAR_PSC1);
 64         __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
 65                 MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
 66         __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
 67 }
 68 
 69 /***************************************************************************/
 70 
 71 static void __init m54xx_i2c_init(void)
 72 {
 73 #if IS_ENABLED(CONFIG_I2C_IMX)
 74         u32 r;
 75 
 76         /* set the fec/i2c/irq pin assignment register for i2c */
 77         r = readl(MCF_PAR_FECI2CIRQ);
 78         r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
 79         writel(r, MCF_PAR_FECI2CIRQ);
 80 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
 81 }
 82 
 83 /***************************************************************************/
 84 
 85 static void mcf54xx_reset(void)
 86 {
 87         /* disable interrupts and enable the watchdog */
 88         asm("movew #0x2700, %sr\n");
 89         __raw_writel(0, MCF_GPT_GMS0);
 90         __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
 91         __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
 92                 MCF_GPT_GMS0);
 93 }
 94 
 95 /***************************************************************************/
 96 
 97 void __init config_BSP(char *commandp, int size)
 98 {
 99         mach_reset = mcf54xx_reset;
100         mach_sched_init = hw_timer_init;
101         m54xx_uarts_init();
102         m54xx_i2c_init();
103 }
104 
105 /***************************************************************************/
106 

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