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Linux/arch/m68k/mm/memory.c

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  1 /*
  2  *  linux/arch/m68k/mm/memory.c
  3  *
  4  *  Copyright (C) 1995  Hamish Macdonald
  5  */
  6 
  7 #include <linux/config.h>
  8 #include <linux/mm.h>
  9 #include <linux/kernel.h>
 10 #include <linux/string.h>
 11 #include <linux/types.h>
 12 #include <linux/slab.h>
 13 #include <linux/init.h>
 14 #include <linux/pagemap.h>
 15 
 16 #include <asm/setup.h>
 17 #include <asm/segment.h>
 18 #include <asm/page.h>
 19 #include <asm/pgalloc.h>
 20 #include <asm/system.h>
 21 #include <asm/traps.h>
 22 #include <asm/machdep.h>
 23 
 24 struct pgtable_cache_struct quicklists;
 25 
 26 /* ++andreas: {get,free}_pointer_table rewritten to use unused fields from
 27    struct page instead of separately kmalloced struct.  Stolen from
 28    arch/sparc/mm/srmmu.c ... */
 29 
 30 typedef struct list_head ptable_desc;
 31 static LIST_HEAD(ptable_list);
 32 
 33 #define PD_PTABLE(page) ((ptable_desc *)virt_to_page(page))
 34 #define PD_PAGE(ptable) (list_entry(ptable, struct page, list))
 35 #define PD_MARKBITS(dp) (*(unsigned char *)&PD_PAGE(dp)->index)
 36 
 37 #define PTABLE_SIZE (PTRS_PER_PMD * sizeof(pmd_t))
 38 
 39 void __init init_pointer_table(unsigned long ptable)
 40 {
 41         ptable_desc *dp;
 42         unsigned long page = ptable & PAGE_MASK;
 43         unsigned char mask = 1 << ((ptable - page)/PTABLE_SIZE);
 44 
 45         dp = PD_PTABLE(page);
 46         if (!(PD_MARKBITS(dp) & mask)) {
 47                 PD_MARKBITS(dp) = 0xff;
 48                 list_add(dp, &ptable_list);
 49         }
 50 
 51         PD_MARKBITS(dp) &= ~mask;
 52 #ifdef DEBUG
 53         printk("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp));
 54 #endif
 55 
 56         /* unreserve the page so it's possible to free that page */
 57         PD_PAGE(dp)->flags &= ~(1 << PG_reserved);
 58         atomic_set(&PD_PAGE(dp)->count, 1);
 59 
 60         return;
 61 }
 62 
 63 pmd_t *get_pointer_table (void)
 64 {
 65         ptable_desc *dp = ptable_list.next;
 66         unsigned char mask = PD_MARKBITS (dp);
 67         unsigned char tmp;
 68         unsigned int off;
 69 
 70         /*
 71          * For a pointer table for a user process address space, a
 72          * table is taken from a page allocated for the purpose.  Each
 73          * page can hold 8 pointer tables.  The page is remapped in
 74          * virtual address space to be noncacheable.
 75          */
 76         if (mask == 0) {
 77                 unsigned long page;
 78                 ptable_desc *new;
 79 
 80                 if (!(page = get_free_page (GFP_KERNEL)))
 81                         return 0;
 82 
 83                 flush_tlb_kernel_page(page);
 84                 nocache_page (page);
 85 
 86                 new = PD_PTABLE(page);
 87                 PD_MARKBITS(new) = 0xfe;
 88                 list_add_tail(new, dp);
 89 
 90                 return (pmd_t *)page;
 91         }
 92 
 93         for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += PTABLE_SIZE)
 94                 ;
 95         PD_MARKBITS(dp) = mask & ~tmp;
 96         if (!PD_MARKBITS(dp)) {
 97                 /* move to end of list */
 98                 list_del(dp);
 99                 list_add_tail(dp, &ptable_list);
100         }
101         return (pmd_t *) (page_address(PD_PAGE(dp)) + off);
102 }
103 
104 int free_pointer_table (pmd_t *ptable)
105 {
106         ptable_desc *dp;
107         unsigned long page = (unsigned long)ptable & PAGE_MASK;
108         unsigned char mask = 1 << (((unsigned long)ptable - page)/PTABLE_SIZE);
109 
110         dp = PD_PTABLE(page);
111         if (PD_MARKBITS (dp) & mask)
112                 panic ("table already free!");
113 
114         PD_MARKBITS (dp) |= mask;
115 
116         if (PD_MARKBITS(dp) == 0xff) {
117                 /* all tables in page are free, free page */
118                 list_del(dp);
119                 cache_page (page);
120                 free_page (page);
121                 return 1;
122         } else if (ptable_list.next != dp) {
123                 /*
124                  * move this descriptor to the front of the list, since
125                  * it has one or more free tables.
126                  */
127                 list_del(dp);
128                 list_add(dp, &ptable_list);
129         }
130         return 0;
131 }
132 
133 #if DEBUG_INVALID_PTOV
134 int mm_inv_cnt = 5;
135 #endif
136 
137 #ifndef CONFIG_SINGLE_MEMORY_CHUNK
138 /*
139  * The following two routines map from a physical address to a kernel
140  * virtual address and vice versa.
141  */
142 unsigned long mm_vtop(unsigned long vaddr)
143 {
144         int i=0;
145         unsigned long voff = (unsigned long)vaddr - PAGE_OFFSET;
146 
147         do {
148                 if (voff < m68k_memory[i].size) {
149 #ifdef DEBUGPV
150                         printk ("VTOP(%p)=%lx\n", vaddr,
151                                 m68k_memory[i].addr + voff);
152 #endif
153                         return m68k_memory[i].addr + voff;
154                 }
155                 voff -= m68k_memory[i].size;
156         } while (++i < m68k_num_memory);
157 
158         /* As a special case allow `__pa(high_memory)'.  */
159         if (voff == 0)
160                 return m68k_memory[i-1].addr + m68k_memory[i-1].size;
161 
162         return -1;
163 }
164 #endif
165 
166 #ifndef CONFIG_SINGLE_MEMORY_CHUNK
167 unsigned long mm_ptov (unsigned long paddr)
168 {
169         int i = 0;
170         unsigned long poff, voff = PAGE_OFFSET;
171 
172         do {
173                 poff = paddr - m68k_memory[i].addr;
174                 if (poff < m68k_memory[i].size) {
175 #ifdef DEBUGPV
176                         printk ("PTOV(%lx)=%lx\n", paddr, poff + voff);
177 #endif
178                         return poff + voff;
179                 }
180                 voff += m68k_memory[i].size;
181         } while (++i < m68k_num_memory);
182 
183 #if DEBUG_INVALID_PTOV
184         if (mm_inv_cnt > 0) {
185                 mm_inv_cnt--;
186                 printk("Invalid use of phys_to_virt(0x%lx) at 0x%p!\n",
187                         paddr, __builtin_return_address(0));
188         }
189 #endif
190         return -1;
191 }
192 #endif
193 
194 /* invalidate page in both caches */
195 static inline void clear040(unsigned long paddr)
196 {
197         asm volatile (
198                 "nop\n\t"
199                 ".chip 68040\n\t"
200                 "cinvp %%bc,(%0)\n\t"
201                 ".chip 68k"
202                 : : "a" (paddr));
203 }
204 
205 /* invalidate page in i-cache */
206 static inline void cleari040(unsigned long paddr)
207 {
208         asm volatile (
209                 "nop\n\t"
210                 ".chip 68040\n\t"
211                 "cinvp %%ic,(%0)\n\t"
212                 ".chip 68k"
213                 : : "a" (paddr));
214 }
215 
216 /* push page in both caches */
217 /* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
218 static inline void push040(unsigned long paddr)
219 {
220         asm volatile (
221                 "nop\n\t"
222                 ".chip 68040\n\t"
223                 "cpushp %%bc,(%0)\n\t"
224                 ".chip 68k"
225                 : : "a" (paddr));
226 }
227 
228 /* push and invalidate page in both caches, must disable ints
229  * to avoid invalidating valid data */
230 static inline void pushcl040(unsigned long paddr)
231 {
232         unsigned long flags;
233 
234         local_irq_save(flags);
235         push040(paddr);
236         if (CPU_IS_060)
237                 clear040(paddr);
238         local_irq_restore(flags);
239 }
240 
241 /*
242  * 040: Hit every page containing an address in the range paddr..paddr+len-1.
243  * (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
244  * Hit every page until there is a page or less to go. Hit the next page,
245  * and the one after that if the range hits it.
246  */
247 /* ++roman: A little bit more care is required here: The CINVP instruction
248  * invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
249  * and the end of the region must be treated differently if they are not
250  * exactly at the beginning or end of a page boundary. Else, maybe too much
251  * data becomes invalidated and thus lost forever. CPUSHP does what we need:
252  * it invalidates the page after pushing dirty data to memory. (Thanks to Jes
253  * for discovering the problem!)
254  */
255 /* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
256  * the DPI bit in the CACR; would it cause problems with temporarily changing
257  * this?). So we have to push first and then additionally to invalidate.
258  */
259 
260 
261 /*
262  * cache_clear() semantics: Clear any cache entries for the area in question,
263  * without writing back dirty entries first. This is useful if the data will
264  * be overwritten anyway, e.g. by DMA to memory. The range is defined by a
265  * _physical_ address.
266  */
267 
268 void cache_clear (unsigned long paddr, int len)
269 {
270     if (CPU_IS_040_OR_060) {
271         int tmp;
272 
273         /*
274          * We need special treatment for the first page, in case it
275          * is not page-aligned. Page align the addresses to work
276          * around bug I17 in the 68060.
277          */
278         if ((tmp = -paddr & (PAGE_SIZE - 1))) {
279             pushcl040(paddr & PAGE_MASK);
280             if ((len -= tmp) <= 0)
281                 return;
282             paddr += tmp;
283         }
284         tmp = PAGE_SIZE;
285         paddr &= PAGE_MASK;
286         while ((len -= tmp) >= 0) {
287             clear040(paddr);
288             paddr += tmp;
289         }
290         if ((len += tmp))
291             /* a page boundary gets crossed at the end */
292             pushcl040(paddr);
293     }
294     else /* 68030 or 68020 */
295         asm volatile ("movec %/cacr,%/d0\n\t"
296                       "oriw %0,%/d0\n\t"
297                       "movec %/d0,%/cacr"
298                       : : "i" (FLUSH_I_AND_D)
299                       : "d0");
300 #ifdef CONFIG_M68K_L2_CACHE
301     if(mach_l2_flush)
302         mach_l2_flush(0);
303 #endif
304 }
305 
306 
307 /*
308  * cache_push() semantics: Write back any dirty cache data in the given area,
309  * and invalidate the range in the instruction cache. It needs not (but may)
310  * invalidate those entries also in the data cache. The range is defined by a
311  * _physical_ address.
312  */
313 
314 void cache_push (unsigned long paddr, int len)
315 {
316     if (CPU_IS_040_OR_060) {
317         int tmp = PAGE_SIZE;
318 
319         /*
320          * on 68040 or 68060, push cache lines for pages in the range;
321          * on the '040 this also invalidates the pushed lines, but not on
322          * the '060!
323          */
324         len += paddr & (PAGE_SIZE - 1);
325 
326         /*
327          * Work around bug I17 in the 68060 affecting some instruction
328          * lines not being invalidated properly.
329          */
330         paddr &= PAGE_MASK;
331 
332         do {
333             push040(paddr);
334             paddr += tmp;
335         } while ((len -= tmp) > 0);
336     }
337     /*
338      * 68030/68020 have no writeback cache. On the other hand,
339      * cache_push is actually a superset of cache_clear (the lines
340      * get written back and invalidated), so we should make sure
341      * to perform the corresponding actions. After all, this is getting
342      * called in places where we've just loaded code, or whatever, so
343      * flushing the icache is appropriate; flushing the dcache shouldn't
344      * be required.
345      */
346     else /* 68030 or 68020 */
347         asm volatile ("movec %/cacr,%/d0\n\t"
348                       "oriw %0,%/d0\n\t"
349                       "movec %/d0,%/cacr"
350                       : : "i" (FLUSH_I)
351                       : "d0");
352 #ifdef CONFIG_M68K_L2_CACHE
353     if(mach_l2_flush)
354         mach_l2_flush(1);
355 #endif
356 }
357 
358 
359 #ifndef CONFIG_SINGLE_MEMORY_CHUNK
360 int mm_end_of_chunk (unsigned long addr, int len)
361 {
362         int i;
363 
364         for (i = 0; i < m68k_num_memory; i++)
365                 if (m68k_memory[i].addr + m68k_memory[i].size == addr + len)
366                         return 1;
367         return 0;
368 }
369 #endif
370 

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