1 /***************************************************************************/
2
3 /*
4 * linux/arch/m68knommu/platform/5272/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
8 */
9
10 /***************************************************************************/
11
12 #include <linux/kernel.h>
13 #include <linux/param.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/phy.h>
17 #include <linux/phy_fixed.h>
18 #include <asm/machdep.h>
19 #include <asm/coldfire.h>
20 #include <asm/mcfsim.h>
21 #include <asm/mcfuart.h>
22 #include <asm/mcfclk.h>
23
24 /***************************************************************************/
25
26 /*
27 * Some platforms need software versions of the GPIO data registers.
28 */
29 unsigned short ppdata;
30 unsigned char ledbank = 0xff;
31
32 /***************************************************************************/
33
34 DEFINE_CLK(pll, "pll.0", MCF_CLK);
35 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
36 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
37 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
38 DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
39 DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
40 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
41 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
42 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
43
44 struct clk *mcf_clks[] = {
45 &clk_pll,
46 &clk_sys,
47 &clk_mcftmr0,
48 &clk_mcftmr1,
49 &clk_mcftmr2,
50 &clk_mcftmr3,
51 &clk_mcfuart0,
52 &clk_mcfuart1,
53 &clk_fec0,
54 NULL
55 };
56
57 /***************************************************************************/
58
59 static void __init m5272_uarts_init(void)
60 {
61 u32 v;
62
63 /* Enable the output lines for the serial ports */
64 v = readl(MCFSIM_PBCNT);
65 v = (v & ~0x000000ff) | 0x00000055;
66 writel(v, MCFSIM_PBCNT);
67
68 v = readl(MCFSIM_PDCNT);
69 v = (v & ~0x000003fc) | 0x000002a8;
70 writel(v, MCFSIM_PDCNT);
71 }
72
73 /***************************************************************************/
74
75 static void m5272_cpu_reset(void)
76 {
77 local_irq_disable();
78 /* Set watchdog to reset, and enabled */
79 __raw_writew(0, MCFSIM_WIRR);
80 __raw_writew(1, MCFSIM_WRRR);
81 __raw_writew(0, MCFSIM_WCR);
82 for (;;)
83 /* wait for watchdog to timeout */;
84 }
85
86 /***************************************************************************/
87
88 void __init config_BSP(char *commandp, int size)
89 {
90 #if defined (CONFIG_MOD5272)
91 /* Set base of device vectors to be 64 */
92 writeb(0x40, MCFSIM_PIVR);
93 #endif
94
95 #if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
96 /* Copy command line from FLASH to local buffer... */
97 memcpy(commandp, (char *) 0xf0004000, size);
98 commandp[size-1] = 0;
99 #elif defined(CONFIG_CANCam)
100 /* Copy command line from FLASH to local buffer... */
101 memcpy(commandp, (char *) 0xf0010000, size);
102 commandp[size-1] = 0;
103 #endif
104
105 mach_reset = m5272_cpu_reset;
106 mach_sched_init = hw_timer_init;
107 }
108
109 /***************************************************************************/
110
111 /*
112 * Some 5272 based boards have the FEC ethernet diectly connected to
113 * an ethernet switch. In this case we need to use the fixed phy type,
114 * and we need to declare it early in boot.
115 */
116 static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
117 .link = 1,
118 .speed = 100,
119 .duplex = 0,
120 };
121
122 /***************************************************************************/
123
124 static int __init init_BSP(void)
125 {
126 m5272_uarts_init();
127 fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
128 return 0;
129 }
130
131 arch_initcall(init_BSP);
132
133 /***************************************************************************/
134
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