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TOMOYO Linux Cross Reference
Linux/arch/microblaze/include/asm/pgtable.h

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  1 /*
  2  * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
  3  * Copyright (C) 2008-2009 PetaLogix
  4  * Copyright (C) 2006 Atmark Techno, Inc.
  5  *
  6  * This file is subject to the terms and conditions of the GNU General Public
  7  * License. See the file "COPYING" in the main directory of this archive
  8  * for more details.
  9  */
 10 
 11 #ifndef _ASM_MICROBLAZE_PGTABLE_H
 12 #define _ASM_MICROBLAZE_PGTABLE_H
 13 
 14 #include <asm/setup.h>
 15 
 16 #ifndef __ASSEMBLY__
 17 extern int mem_init_done;
 18 #endif
 19 
 20 #ifndef CONFIG_MMU
 21 
 22 #define pgd_present(pgd)        (1) /* pages are always present on non MMU */
 23 #define pgd_none(pgd)           (0)
 24 #define pgd_bad(pgd)            (0)
 25 #define pgd_clear(pgdp)
 26 #define kern_addr_valid(addr)   (1)
 27 #define pmd_offset(a, b)        ((void *) 0)
 28 
 29 #define PAGE_NONE               __pgprot(0) /* these mean nothing to non MMU */
 30 #define PAGE_SHARED             __pgprot(0) /* these mean nothing to non MMU */
 31 #define PAGE_COPY               __pgprot(0) /* these mean nothing to non MMU */
 32 #define PAGE_READONLY           __pgprot(0) /* these mean nothing to non MMU */
 33 #define PAGE_KERNEL             __pgprot(0) /* these mean nothing to non MMU */
 34 
 35 #define pgprot_noncached(x)     (x)
 36 
 37 #define __swp_type(x)           (0)
 38 #define __swp_offset(x)         (0)
 39 #define __swp_entry(typ, off)   ((swp_entry_t) { ((typ) | ((off) << 7)) })
 40 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 41 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
 42 
 43 #define ZERO_PAGE(vaddr)        ({ BUG(); NULL; })
 44 
 45 #define swapper_pg_dir ((pgd_t *) NULL)
 46 
 47 #define pgtable_cache_init()    do {} while (0)
 48 
 49 #define arch_enter_lazy_cpu_mode()      do {} while (0)
 50 
 51 #define pgprot_noncached_wc(prot)       prot
 52 
 53 /*
 54  * All 32bit addresses are effectively valid for vmalloc...
 55  * Sort of meaningless for non-VM targets.
 56  */
 57 #define VMALLOC_START   0
 58 #define VMALLOC_END     0xffffffff
 59 
 60 #else /* CONFIG_MMU */
 61 
 62 #include <asm-generic/4level-fixup.h>
 63 
 64 #define __PAGETABLE_PMD_FOLDED
 65 
 66 #ifdef __KERNEL__
 67 #ifndef __ASSEMBLY__
 68 
 69 #include <linux/sched.h>
 70 #include <linux/threads.h>
 71 #include <asm/processor.h>              /* For TASK_SIZE */
 72 #include <asm/mmu.h>
 73 #include <asm/page.h>
 74 
 75 #define FIRST_USER_ADDRESS      0UL
 76 
 77 extern unsigned long va_to_phys(unsigned long address);
 78 extern pte_t *va_to_pte(unsigned long address);
 79 
 80 /*
 81  * The following only work if pte_present() is true.
 82  * Undefined behaviour if not..
 83  */
 84 
 85 static inline int pte_special(pte_t pte)        { return 0; }
 86 
 87 static inline pte_t pte_mkspecial(pte_t pte)    { return pte; }
 88 
 89 /* Start and end of the vmalloc area. */
 90 /* Make sure to map the vmalloc area above the pinned kernel memory area
 91    of 32Mb.  */
 92 #define VMALLOC_START   (CONFIG_KERNEL_START + CONFIG_LOWMEM_SIZE)
 93 #define VMALLOC_END     ioremap_bot
 94 
 95 #endif /* __ASSEMBLY__ */
 96 
 97 /*
 98  * Macro to mark a page protection value as "uncacheable".
 99  */
100 
101 #define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \
102                                                         _PAGE_WRITETHRU)
103 
104 #define pgprot_noncached(prot) \
105                         (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
106                                         _PAGE_NO_CACHE | _PAGE_GUARDED))
107 
108 #define pgprot_noncached_wc(prot) \
109                          (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
110                                                         _PAGE_NO_CACHE))
111 
112 /*
113  * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash
114  * table containing PTEs, together with a set of 16 segment registers, to
115  * define the virtual to physical address mapping.
116  *
117  * We use the hash table as an extended TLB, i.e. a cache of currently
118  * active mappings.  We maintain a two-level page table tree, much
119  * like that used by the i386, for the sake of the Linux memory
120  * management code.  Low-level assembler code in hashtable.S
121  * (procedure hash_page) is responsible for extracting ptes from the
122  * tree and putting them into the hash table when necessary, and
123  * updating the accessed and modified bits in the page table tree.
124  */
125 
126 /*
127  * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
128  * instruction and data sides share a unified, 64-entry, semi-associative
129  * TLB which is maintained totally under software control. In addition, the
130  * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
131  * TLB which serves as a first level to the shared TLB. These two TLBs are
132  * known as the UTLB and ITLB, respectively (see "mmu.h" for definitions).
133  */
134 
135 /*
136  * The normal case is that PTEs are 32-bits and we have a 1-page
137  * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
138  *
139  */
140 
141 /* PMD_SHIFT determines the size of the area mapped by the PTE pages */
142 #define PMD_SHIFT       (PAGE_SHIFT + PTE_SHIFT)
143 #define PMD_SIZE        (1UL << PMD_SHIFT)
144 #define PMD_MASK        (~(PMD_SIZE-1))
145 
146 /* PGDIR_SHIFT determines what a top-level page table entry can map */
147 #define PGDIR_SHIFT     PMD_SHIFT
148 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
149 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
150 
151 /*
152  * entries per page directory level: our page-table tree is two-level, so
153  * we don't really have any PMD directory.
154  */
155 #define PTRS_PER_PTE    (1 << PTE_SHIFT)
156 #define PTRS_PER_PMD    1
157 #define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
158 
159 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
160 #define FIRST_USER_PGD_NR       0
161 
162 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
163 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
164 
165 #define pte_ERROR(e) \
166         printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \
167                 __FILE__, __LINE__, pte_val(e))
168 #define pmd_ERROR(e) \
169         printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \
170                 __FILE__, __LINE__, pmd_val(e))
171 #define pgd_ERROR(e) \
172         printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
173                 __FILE__, __LINE__, pgd_val(e))
174 
175 /*
176  * Bits in a linux-style PTE.  These match the bits in the
177  * (hardware-defined) PTE as closely as possible.
178  */
179 
180 /* There are several potential gotchas here.  The hardware TLBLO
181  * field looks like this:
182  *
183  * 0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
184  * RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
185  *
186  * Where possible we make the Linux PTE bits match up with this
187  *
188  * - bits 20 and 21 must be cleared, because we use 4k pages (4xx can
189  * support down to 1k pages), this is done in the TLBMiss exception
190  * handler.
191  * - We use only zones 0 (for kernel pages) and 1 (for user pages)
192  * of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
193  * miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
194  * zone.
195  * - PRESENT *must* be in the bottom two bits because swap cache
196  * entries use the top 30 bits.  Because 4xx doesn't support SMP
197  * anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
198  * is cleared in the TLB miss handler before the TLB entry is loaded.
199  * - All other bits of the PTE are loaded into TLBLO without
200  *  * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
201  * software PTE bits.  We actually use use bits 21, 24, 25, and
202  * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
203  * PRESENT.
204  */
205 
206 /* Definitions for MicroBlaze. */
207 #define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
208 #define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
209 #define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
210 #define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
211 #define _PAGE_USER      0x010   /* matches one of the zone permission bits */
212 #define _PAGE_RW        0x040   /* software: Writes permitted */
213 #define _PAGE_DIRTY     0x080   /* software: dirty page */
214 #define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
215 #define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
216 #define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
217 #define _PMD_PRESENT    PAGE_MASK
218 
219 /*
220  * Some bits are unused...
221  */
222 #ifndef _PAGE_HASHPTE
223 #define _PAGE_HASHPTE   0
224 #endif
225 #ifndef _PTE_NONE_MASK
226 #define _PTE_NONE_MASK  0
227 #endif
228 #ifndef _PAGE_SHARED
229 #define _PAGE_SHARED    0
230 #endif
231 #ifndef _PAGE_EXEC
232 #define _PAGE_EXEC      0
233 #endif
234 
235 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
236 
237 /*
238  * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
239  * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
240  * to have it in the Linux PTE, and in fact the bit could be reused for
241  * another purpose.  -- paulus.
242  */
243 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED)
244 #define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
245 
246 #define _PAGE_KERNEL \
247         (_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC)
248 
249 #define _PAGE_IO        (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
250 
251 #define PAGE_NONE       __pgprot(_PAGE_BASE)
252 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
253 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
254 #define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
255 #define PAGE_SHARED_X \
256                 __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
257 #define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
258 #define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
259 
260 #define PAGE_KERNEL     __pgprot(_PAGE_KERNEL)
261 #define PAGE_KERNEL_RO  __pgprot(_PAGE_BASE | _PAGE_SHARED)
262 #define PAGE_KERNEL_CI  __pgprot(_PAGE_IO)
263 
264 /*
265  * We consider execute permission the same as read.
266  * Also, write permissions imply read permissions.
267  */
268 #define __P000  PAGE_NONE
269 #define __P001  PAGE_READONLY_X
270 #define __P010  PAGE_COPY
271 #define __P011  PAGE_COPY_X
272 #define __P100  PAGE_READONLY
273 #define __P101  PAGE_READONLY_X
274 #define __P110  PAGE_COPY
275 #define __P111  PAGE_COPY_X
276 
277 #define __S000  PAGE_NONE
278 #define __S001  PAGE_READONLY_X
279 #define __S010  PAGE_SHARED
280 #define __S011  PAGE_SHARED_X
281 #define __S100  PAGE_READONLY
282 #define __S101  PAGE_READONLY_X
283 #define __S110  PAGE_SHARED
284 #define __S111  PAGE_SHARED_X
285 
286 #ifndef __ASSEMBLY__
287 /*
288  * ZERO_PAGE is a global shared page that is always zero: used
289  * for zero-mapped memory areas etc..
290  */
291 extern unsigned long empty_zero_page[1024];
292 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
293 
294 #endif /* __ASSEMBLY__ */
295 
296 #define pte_none(pte)           ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
297 #define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
298 #define pte_clear(mm, addr, ptep) \
299         do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
300 
301 #define pmd_none(pmd)           (!pmd_val(pmd))
302 #define pmd_bad(pmd)            ((pmd_val(pmd) & _PMD_PRESENT) == 0)
303 #define pmd_present(pmd)        ((pmd_val(pmd) & _PMD_PRESENT) != 0)
304 #define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
305 
306 #define pte_page(x)             (mem_map + (unsigned long) \
307                                 ((pte_val(x) - memory_start) >> PAGE_SHIFT))
308 #define PFN_SHIFT_OFFSET        (PAGE_SHIFT)
309 
310 #define pte_pfn(x)              (pte_val(x) >> PFN_SHIFT_OFFSET)
311 
312 #define pfn_pte(pfn, prot) \
313         __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) | pgprot_val(prot))
314 
315 #ifndef __ASSEMBLY__
316 /*
317  * The "pgd_xxx()" functions here are trivial for a folded two-level
318  * setup: the pgd is never bad, and a pmd always exists (as it's folded
319  * into the pgd entry)
320  */
321 static inline int pgd_none(pgd_t pgd)           { return 0; }
322 static inline int pgd_bad(pgd_t pgd)            { return 0; }
323 static inline int pgd_present(pgd_t pgd)        { return 1; }
324 #define pgd_clear(xp)                           do { } while (0)
325 #define pgd_page(pgd) \
326         ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
327 
328 /*
329  * The following only work if pte_present() is true.
330  * Undefined behaviour if not..
331  */
332 static inline int pte_read(pte_t pte)  { return pte_val(pte) & _PAGE_USER; }
333 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
334 static inline int pte_exec(pte_t pte)  { return pte_val(pte) & _PAGE_EXEC; }
335 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
336 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
337 
338 static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
339 static inline void pte_cache(pte_t pte)   { pte_val(pte) &= ~_PAGE_NO_CACHE; }
340 
341 static inline pte_t pte_rdprotect(pte_t pte) \
342                 { pte_val(pte) &= ~_PAGE_USER; return pte; }
343 static inline pte_t pte_wrprotect(pte_t pte) \
344         { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
345 static inline pte_t pte_exprotect(pte_t pte) \
346         { pte_val(pte) &= ~_PAGE_EXEC; return pte; }
347 static inline pte_t pte_mkclean(pte_t pte) \
348         { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
349 static inline pte_t pte_mkold(pte_t pte) \
350         { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
351 
352 static inline pte_t pte_mkread(pte_t pte) \
353         { pte_val(pte) |= _PAGE_USER; return pte; }
354 static inline pte_t pte_mkexec(pte_t pte) \
355         { pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
356 static inline pte_t pte_mkwrite(pte_t pte) \
357         { pte_val(pte) |= _PAGE_RW; return pte; }
358 static inline pte_t pte_mkdirty(pte_t pte) \
359         { pte_val(pte) |= _PAGE_DIRTY; return pte; }
360 static inline pte_t pte_mkyoung(pte_t pte) \
361         { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
362 
363 /*
364  * Conversion functions: convert a page and protection to a page entry,
365  * and a page entry and page directory to the page they refer to.
366  */
367 
368 static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot)
369 {
370         pte_t pte;
371         pte_val(pte) = physpage | pgprot_val(pgprot);
372         return pte;
373 }
374 
375 #define mk_pte(page, pgprot) \
376 ({                                                                         \
377         pte_t pte;                                                         \
378         pte_val(pte) = (((page - mem_map) << PAGE_SHIFT) + memory_start) |  \
379                         pgprot_val(pgprot);                                \
380         pte;                                                               \
381 })
382 
383 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
384 {
385         pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
386         return pte;
387 }
388 
389 /*
390  * Atomic PTE updates.
391  *
392  * pte_update clears and sets bit atomically, and returns
393  * the old pte value.
394  * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant
395  * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits.
396  */
397 static inline unsigned long pte_update(pte_t *p, unsigned long clr,
398                                 unsigned long set)
399 {
400         unsigned long flags, old, tmp;
401 
402         raw_local_irq_save(flags);
403 
404         __asm__ __volatile__(   "lw     %0, %2, r0      \n"
405                                 "andn   %1, %0, %3      \n"
406                                 "or     %1, %1, %4      \n"
407                                 "sw     %1, %2, r0      \n"
408                         : "=&r" (old), "=&r" (tmp)
409                         : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set)
410                         : "cc");
411 
412         raw_local_irq_restore(flags);
413 
414         return old;
415 }
416 
417 /*
418  * set_pte stores a linux PTE into the linux page table.
419  */
420 static inline void set_pte(struct mm_struct *mm, unsigned long addr,
421                 pte_t *ptep, pte_t pte)
422 {
423         *ptep = pte;
424 }
425 
426 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
427                 pte_t *ptep, pte_t pte)
428 {
429         *ptep = pte;
430 }
431 
432 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
433 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
434                 unsigned long address, pte_t *ptep)
435 {
436         return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0;
437 }
438 
439 static inline int ptep_test_and_clear_dirty(struct mm_struct *mm,
440                 unsigned long addr, pte_t *ptep)
441 {
442         return (pte_update(ptep, \
443                 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
444 }
445 
446 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
447 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
448                 unsigned long addr, pte_t *ptep)
449 {
450         return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
451 }
452 
453 /*static inline void ptep_set_wrprotect(struct mm_struct *mm,
454                 unsigned long addr, pte_t *ptep)
455 {
456         pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
457 }*/
458 
459 static inline void ptep_mkdirty(struct mm_struct *mm,
460                 unsigned long addr, pte_t *ptep)
461 {
462         pte_update(ptep, 0, _PAGE_DIRTY);
463 }
464 
465 /*#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)*/
466 
467 /* Convert pmd entry to page */
468 /* our pmd entry is an effective address of pte table*/
469 /* returns effective address of the pmd entry*/
470 #define pmd_page_kernel(pmd)    ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
471 
472 /* returns struct *page of the pmd entry*/
473 #define pmd_page(pmd)   (pfn_to_page(__pa(pmd_val(pmd)) >> PAGE_SHIFT))
474 
475 /* to find an entry in a kernel page-table-directory */
476 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
477 
478 /* to find an entry in a page-table-directory */
479 #define pgd_index(address)       ((address) >> PGDIR_SHIFT)
480 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
481 
482 /* Find an entry in the second-level page table.. */
483 static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
484 {
485         return (pmd_t *) dir;
486 }
487 
488 /* Find an entry in the third-level page table.. */
489 #define pte_index(address)              \
490         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
491 #define pte_offset_kernel(dir, addr)    \
492         ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr))
493 #define pte_offset_map(dir, addr)               \
494         ((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr))
495 
496 #define pte_unmap(pte)          kunmap_atomic(pte)
497 
498 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
499 
500 /*
501  * Encode and decode a swap entry.
502  * Note that the bits we use in a PTE for representing a swap entry
503  * must not include the _PAGE_PRESENT bit, or the _PAGE_HASHPTE bit
504  * (if used).  -- paulus
505  */
506 #define __swp_type(entry)               ((entry).val & 0x3f)
507 #define __swp_offset(entry)     ((entry).val >> 6)
508 #define __swp_entry(type, offset) \
509                 ((swp_entry_t) { (type) | ((offset) << 6) })
510 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 })
511 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val << 2 })
512 
513 extern unsigned long iopa(unsigned long addr);
514 
515 /* Values for nocacheflag and cmode */
516 /* These are not used by the APUS kernel_map, but prevents
517  * compilation errors.
518  */
519 #define IOMAP_FULL_CACHING      0
520 #define IOMAP_NOCACHE_SER       1
521 #define IOMAP_NOCACHE_NONSER    2
522 #define IOMAP_NO_COPYBACK       3
523 
524 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
525 #define kern_addr_valid(addr)   (1)
526 
527 /*
528  * No page table caches to initialise
529  */
530 #define pgtable_cache_init()    do { } while (0)
531 
532 void do_page_fault(struct pt_regs *regs, unsigned long address,
533                    unsigned long error_code);
534 
535 void mapin_ram(void);
536 int map_page(unsigned long va, phys_addr_t pa, int flags);
537 
538 extern int mem_init_done;
539 
540 asmlinkage void __init mmu_init(void);
541 
542 void __init *early_get_page(void);
543 
544 #endif /* __ASSEMBLY__ */
545 #endif /* __KERNEL__ */
546 
547 #endif /* CONFIG_MMU */
548 
549 #ifndef __ASSEMBLY__
550 #include <asm-generic/pgtable.h>
551 
552 extern unsigned long ioremap_bot, ioremap_base;
553 
554 void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle);
555 void consistent_free(size_t size, void *vaddr);
556 void consistent_sync(void *vaddr, size_t size, int direction);
557 void consistent_sync_page(struct page *page, unsigned long offset,
558         size_t size, int direction);
559 unsigned long consistent_virt_to_pfn(void *vaddr);
560 
561 void setup_memory(void);
562 #endif /* __ASSEMBLY__ */
563 
564 #endif /* _ASM_MICROBLAZE_PGTABLE_H */
565 

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