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Linux/arch/microblaze/pci/pci-common.c

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  1 // SPDX-License-Identifier: GPL-2.0-or-later
  2 /*
  3  * Contains common pci routines for ALL ppc platform
  4  * (based on pci_32.c and pci_64.c)
  5  *
  6  * Port for PPC64 David Engebretsen, IBM Corp.
  7  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
  8  *
  9  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
 10  *   Rework, based on alpha PCI code.
 11  *
 12  * Common pmac/prep/chrp pci routines. -- Cort
 13  */
 14 
 15 #include <linux/kernel.h>
 16 #include <linux/pci.h>
 17 #include <linux/string.h>
 18 #include <linux/init.h>
 19 #include <linux/memblock.h>
 20 #include <linux/mm.h>
 21 #include <linux/shmem_fs.h>
 22 #include <linux/list.h>
 23 #include <linux/syscalls.h>
 24 #include <linux/irq.h>
 25 #include <linux/vmalloc.h>
 26 #include <linux/slab.h>
 27 #include <linux/of.h>
 28 #include <linux/of_address.h>
 29 #include <linux/of_irq.h>
 30 #include <linux/of_pci.h>
 31 #include <linux/export.h>
 32 
 33 #include <asm/processor.h>
 34 #include <linux/io.h>
 35 #include <asm/pci-bridge.h>
 36 #include <asm/byteorder.h>
 37 
 38 static DEFINE_SPINLOCK(hose_spinlock);
 39 LIST_HEAD(hose_list);
 40 
 41 /* XXX kill that some day ... */
 42 static int global_phb_number;           /* Global phb counter */
 43 
 44 /* ISA Memory physical address */
 45 resource_size_t isa_mem_base;
 46 
 47 unsigned long isa_io_base;
 48 EXPORT_SYMBOL(isa_io_base);
 49 
 50 static int pci_bus_count;
 51 
 52 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
 53 {
 54         struct pci_controller *phb;
 55 
 56         phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
 57         if (!phb)
 58                 return NULL;
 59         spin_lock(&hose_spinlock);
 60         phb->global_number = global_phb_number++;
 61         list_add_tail(&phb->list_node, &hose_list);
 62         spin_unlock(&hose_spinlock);
 63         phb->dn = dev;
 64         phb->is_dynamic = mem_init_done;
 65         return phb;
 66 }
 67 
 68 void pcibios_free_controller(struct pci_controller *phb)
 69 {
 70         spin_lock(&hose_spinlock);
 71         list_del(&phb->list_node);
 72         spin_unlock(&hose_spinlock);
 73 
 74         if (phb->is_dynamic)
 75                 kfree(phb);
 76 }
 77 
 78 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
 79 {
 80         return resource_size(&hose->io_resource);
 81 }
 82 
 83 int pcibios_vaddr_is_ioport(void __iomem *address)
 84 {
 85         int ret = 0;
 86         struct pci_controller *hose;
 87         resource_size_t size;
 88 
 89         spin_lock(&hose_spinlock);
 90         list_for_each_entry(hose, &hose_list, list_node) {
 91                 size = pcibios_io_size(hose);
 92                 if (address >= hose->io_base_virt &&
 93                     address < (hose->io_base_virt + size)) {
 94                         ret = 1;
 95                         break;
 96                 }
 97         }
 98         spin_unlock(&hose_spinlock);
 99         return ret;
100 }
101 
102 unsigned long pci_address_to_pio(phys_addr_t address)
103 {
104         struct pci_controller *hose;
105         resource_size_t size;
106         unsigned long ret = ~0;
107 
108         spin_lock(&hose_spinlock);
109         list_for_each_entry(hose, &hose_list, list_node) {
110                 size = pcibios_io_size(hose);
111                 if (address >= hose->io_base_phys &&
112                     address < (hose->io_base_phys + size)) {
113                         unsigned long base =
114                                 (unsigned long)hose->io_base_virt - _IO_BASE;
115                         ret = base + (address - hose->io_base_phys);
116                         break;
117                 }
118         }
119         spin_unlock(&hose_spinlock);
120 
121         return ret;
122 }
123 EXPORT_SYMBOL_GPL(pci_address_to_pio);
124 
125 /* This routine is meant to be used early during boot, when the
126  * PCI bus numbers have not yet been assigned, and you need to
127  * issue PCI config cycles to an OF device.
128  * It could also be used to "fix" RTAS config cycles if you want
129  * to set pci_assign_all_buses to 1 and still use RTAS for PCI
130  * config cycles.
131  */
132 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
133 {
134         while (node) {
135                 struct pci_controller *hose, *tmp;
136                 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
137                         if (hose->dn == node)
138                                 return hose;
139                 node = node->parent;
140         }
141         return NULL;
142 }
143 
144 void pcibios_set_master(struct pci_dev *dev)
145 {
146         /* No special bus mastering setup handling */
147 }
148 
149 /*
150  * Platform support for /proc/bus/pci/X/Y mmap()s.
151  */
152 
153 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
154 {
155         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
156         resource_size_t ioaddr = pci_resource_start(pdev, bar);
157 
158         if (!hose)
159                 return -EINVAL;         /* should never happen */
160 
161         /* Convert to an offset within this PCI controller */
162         ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
163 
164         vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
165         return 0;
166 }
167 
168 /*
169  * This one is used by /dev/mem and fbdev who have no clue about the
170  * PCI device, it tries to find the PCI device first and calls the
171  * above routine
172  */
173 pgprot_t pci_phys_mem_access_prot(struct file *file,
174                                   unsigned long pfn,
175                                   unsigned long size,
176                                   pgprot_t prot)
177 {
178         struct pci_dev *pdev = NULL;
179         struct resource *found = NULL;
180         resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
181         int i;
182 
183         if (page_is_ram(pfn))
184                 return prot;
185 
186         prot = pgprot_noncached(prot);
187         for_each_pci_dev(pdev) {
188                 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
189                         struct resource *rp = &pdev->resource[i];
190                         int flags = rp->flags;
191 
192                         /* Active and same type? */
193                         if ((flags & IORESOURCE_MEM) == 0)
194                                 continue;
195                         /* In the range of this resource? */
196                         if (offset < (rp->start & PAGE_MASK) ||
197                             offset > rp->end)
198                                 continue;
199                         found = rp;
200                         break;
201                 }
202                 if (found)
203                         break;
204         }
205         if (found) {
206                 if (found->flags & IORESOURCE_PREFETCH)
207                         prot = pgprot_noncached_wc(prot);
208                 pci_dev_put(pdev);
209         }
210 
211         pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
212                  (unsigned long long)offset, pgprot_val(prot));
213 
214         return prot;
215 }
216 
217 /* This provides legacy IO read access on a bus */
218 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
219 {
220         unsigned long offset;
221         struct pci_controller *hose = pci_bus_to_host(bus);
222         struct resource *rp = &hose->io_resource;
223         void __iomem *addr;
224 
225         /* Check if port can be supported by that bus. We only check
226          * the ranges of the PHB though, not the bus itself as the rules
227          * for forwarding legacy cycles down bridges are not our problem
228          * here. So if the host bridge supports it, we do it.
229          */
230         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
231         offset += port;
232 
233         if (!(rp->flags & IORESOURCE_IO))
234                 return -ENXIO;
235         if (offset < rp->start || (offset + size) > rp->end)
236                 return -ENXIO;
237         addr = hose->io_base_virt + port;
238 
239         switch (size) {
240         case 1:
241                 *((u8 *)val) = in_8(addr);
242                 return 1;
243         case 2:
244                 if (port & 1)
245                         return -EINVAL;
246                 *((u16 *)val) = in_le16(addr);
247                 return 2;
248         case 4:
249                 if (port & 3)
250                         return -EINVAL;
251                 *((u32 *)val) = in_le32(addr);
252                 return 4;
253         }
254         return -EINVAL;
255 }
256 
257 /* This provides legacy IO write access on a bus */
258 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
259 {
260         unsigned long offset;
261         struct pci_controller *hose = pci_bus_to_host(bus);
262         struct resource *rp = &hose->io_resource;
263         void __iomem *addr;
264 
265         /* Check if port can be supported by that bus. We only check
266          * the ranges of the PHB though, not the bus itself as the rules
267          * for forwarding legacy cycles down bridges are not our problem
268          * here. So if the host bridge supports it, we do it.
269          */
270         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
271         offset += port;
272 
273         if (!(rp->flags & IORESOURCE_IO))
274                 return -ENXIO;
275         if (offset < rp->start || (offset + size) > rp->end)
276                 return -ENXIO;
277         addr = hose->io_base_virt + port;
278 
279         /* WARNING: The generic code is idiotic. It gets passed a pointer
280          * to what can be a 1, 2 or 4 byte quantity and always reads that
281          * as a u32, which means that we have to correct the location of
282          * the data read within those 32 bits for size 1 and 2
283          */
284         switch (size) {
285         case 1:
286                 out_8(addr, val >> 24);
287                 return 1;
288         case 2:
289                 if (port & 1)
290                         return -EINVAL;
291                 out_le16(addr, val >> 16);
292                 return 2;
293         case 4:
294                 if (port & 3)
295                         return -EINVAL;
296                 out_le32(addr, val);
297                 return 4;
298         }
299         return -EINVAL;
300 }
301 
302 /* This provides legacy IO or memory mmap access on a bus */
303 int pci_mmap_legacy_page_range(struct pci_bus *bus,
304                                struct vm_area_struct *vma,
305                                enum pci_mmap_state mmap_state)
306 {
307         struct pci_controller *hose = pci_bus_to_host(bus);
308         resource_size_t offset =
309                 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
310         resource_size_t size = vma->vm_end - vma->vm_start;
311         struct resource *rp;
312 
313         pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
314                  pci_domain_nr(bus), bus->number,
315                  mmap_state == pci_mmap_mem ? "MEM" : "IO",
316                  (unsigned long long)offset,
317                  (unsigned long long)(offset + size - 1));
318 
319         if (mmap_state == pci_mmap_mem) {
320                 /* Hack alert !
321                  *
322                  * Because X is lame and can fail starting if it gets an error
323                  * trying to mmap legacy_mem (instead of just moving on without
324                  * legacy memory access) we fake it here by giving it anonymous
325                  * memory, effectively behaving just like /dev/zero
326                  */
327                 if ((offset + size) > hose->isa_mem_size) {
328                         pr_debug("Process %s (pid:%d) mapped non-existing PCI",
329                                 current->comm, current->pid);
330                         pr_debug("legacy memory for 0%04x:%02x\n",
331                                 pci_domain_nr(bus), bus->number);
332                         if (vma->vm_flags & VM_SHARED)
333                                 return shmem_zero_setup(vma);
334                         return 0;
335                 }
336                 offset += hose->isa_mem_phys;
337         } else {
338                 unsigned long io_offset = (unsigned long)hose->io_base_virt -
339                                                                 _IO_BASE;
340                 unsigned long roffset = offset + io_offset;
341                 rp = &hose->io_resource;
342                 if (!(rp->flags & IORESOURCE_IO))
343                         return -ENXIO;
344                 if (roffset < rp->start || (roffset + size) > rp->end)
345                         return -ENXIO;
346                 offset += hose->io_base_phys;
347         }
348         pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
349 
350         vma->vm_pgoff = offset >> PAGE_SHIFT;
351         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
352         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
353                                vma->vm_end - vma->vm_start,
354                                vma->vm_page_prot);
355 }
356 
357 void pci_resource_to_user(const struct pci_dev *dev, int bar,
358                           const struct resource *rsrc,
359                           resource_size_t *start, resource_size_t *end)
360 {
361         struct pci_bus_region region;
362 
363         if (rsrc->flags & IORESOURCE_IO) {
364                 pcibios_resource_to_bus(dev->bus, &region,
365                                         (struct resource *) rsrc);
366                 *start = region.start;
367                 *end = region.end;
368                 return;
369         }
370 
371         /* We pass a CPU physical address to userland for MMIO instead of a
372          * BAR value because X is lame and expects to be able to use that
373          * to pass to /dev/mem!
374          *
375          * That means we may have 64-bit values where some apps only expect
376          * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
377          */
378         *start = rsrc->start;
379         *end = rsrc->end;
380 }
381 
382 /**
383  * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
384  * @hose: newly allocated pci_controller to be setup
385  * @dev: device node of the host bridge
386  * @primary: set if primary bus (32 bits only, soon to be deprecated)
387  *
388  * This function will parse the "ranges" property of a PCI host bridge device
389  * node and setup the resource mapping of a pci controller based on its
390  * content.
391  *
392  * Life would be boring if it wasn't for a few issues that we have to deal
393  * with here:
394  *
395  *   - We can only cope with one IO space range and up to 3 Memory space
396  *     ranges. However, some machines (thanks Apple !) tend to split their
397  *     space into lots of small contiguous ranges. So we have to coalesce.
398  *
399  *   - We can only cope with all memory ranges having the same offset
400  *     between CPU addresses and PCI addresses. Unfortunately, some bridges
401  *     are setup for a large 1:1 mapping along with a small "window" which
402  *     maps PCI address 0 to some arbitrary high address of the CPU space in
403  *     order to give access to the ISA memory hole.
404  *     The way out of here that I've chosen for now is to always set the
405  *     offset based on the first resource found, then override it if we
406  *     have a different offset and the previous was set by an ISA hole.
407  *
408  *   - Some busses have IO space not starting at 0, which causes trouble with
409  *     the way we do our IO resource renumbering. The code somewhat deals with
410  *     it for 64 bits but I would expect problems on 32 bits.
411  *
412  *   - Some 32 bits platforms such as 4xx can have physical space larger than
413  *     32 bits so we need to use 64 bits values for the parsing
414  */
415 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
416                                   struct device_node *dev, int primary)
417 {
418         int memno = 0, isa_hole = -1;
419         unsigned long long isa_mb = 0;
420         struct resource *res;
421         struct of_pci_range range;
422         struct of_pci_range_parser parser;
423 
424         pr_info("PCI host bridge %pOF %s ranges:\n",
425                dev, primary ? "(primary)" : "");
426 
427         /* Check for ranges property */
428         if (of_pci_range_parser_init(&parser, dev))
429                 return;
430 
431         pr_debug("Parsing ranges property...\n");
432         for_each_of_pci_range(&parser, &range) {
433                 /* Read next ranges element */
434 
435                 /* If we failed translation or got a zero-sized region
436                  * (some FW try to feed us with non sensical zero sized regions
437                  * such as power3 which look like some kind of attempt
438                  * at exposing the VGA memory hole)
439                  */
440                 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
441                         continue;
442 
443                 /* Act based on address space type */
444                 res = NULL;
445                 switch (range.flags & IORESOURCE_TYPE_BITS) {
446                 case IORESOURCE_IO:
447                         pr_info("  IO 0x%016llx..0x%016llx -> 0x%016llx\n",
448                                 range.cpu_addr, range.cpu_addr + range.size - 1,
449                                 range.pci_addr);
450 
451                         /* We support only one IO range */
452                         if (hose->pci_io_size) {
453                                 pr_info(" \\--> Skipped (too many) !\n");
454                                 continue;
455                         }
456                         /* On 32 bits, limit I/O space to 16MB */
457                         if (range.size > 0x01000000)
458                                 range.size = 0x01000000;
459 
460                         /* 32 bits needs to map IOs here */
461                         hose->io_base_virt = ioremap(range.cpu_addr,
462                                                 range.size);
463 
464                         /* Expect trouble if pci_addr is not 0 */
465                         if (primary)
466                                 isa_io_base =
467                                         (unsigned long)hose->io_base_virt;
468                         /* pci_io_size and io_base_phys always represent IO
469                          * space starting at 0 so we factor in pci_addr
470                          */
471                         hose->pci_io_size = range.pci_addr + range.size;
472                         hose->io_base_phys = range.cpu_addr - range.pci_addr;
473 
474                         /* Build resource */
475                         res = &hose->io_resource;
476                         range.cpu_addr = range.pci_addr;
477 
478                         break;
479                 case IORESOURCE_MEM:
480                         pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
481                                 range.cpu_addr, range.cpu_addr + range.size - 1,
482                                 range.pci_addr,
483                                 (range.flags & IORESOURCE_PREFETCH) ?
484                                 "Prefetch" : "");
485 
486                         /* We support only 3 memory ranges */
487                         if (memno >= 3) {
488                                 pr_info(" \\--> Skipped (too many) !\n");
489                                 continue;
490                         }
491                         /* Handles ISA memory hole space here */
492                         if (range.pci_addr == 0) {
493                                 isa_mb = range.cpu_addr;
494                                 isa_hole = memno;
495                                 if (primary || isa_mem_base == 0)
496                                         isa_mem_base = range.cpu_addr;
497                                 hose->isa_mem_phys = range.cpu_addr;
498                                 hose->isa_mem_size = range.size;
499                         }
500 
501                         /* We get the PCI/Mem offset from the first range or
502                          * the, current one if the offset came from an ISA
503                          * hole. If they don't match, bugger.
504                          */
505                         if (memno == 0 ||
506                             (isa_hole >= 0 && range.pci_addr != 0 &&
507                              hose->pci_mem_offset == isa_mb))
508                                 hose->pci_mem_offset = range.cpu_addr -
509                                                         range.pci_addr;
510                         else if (range.pci_addr != 0 &&
511                                  hose->pci_mem_offset != range.cpu_addr -
512                                                         range.pci_addr) {
513                                 pr_info(" \\--> Skipped (offset mismatch) !\n");
514                                 continue;
515                         }
516 
517                         /* Build resource */
518                         res = &hose->mem_resources[memno++];
519                         break;
520                 }
521                 if (res != NULL) {
522                         res->name = dev->full_name;
523                         res->flags = range.flags;
524                         res->start = range.cpu_addr;
525                         res->end = range.cpu_addr + range.size - 1;
526                         res->parent = res->child = res->sibling = NULL;
527                 }
528         }
529 
530         /* If there's an ISA hole and the pci_mem_offset is -not- matching
531          * the ISA hole offset, then we need to remove the ISA hole from
532          * the resource list for that brige
533          */
534         if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
535                 unsigned int next = isa_hole + 1;
536                 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
537                 if (next < memno)
538                         memmove(&hose->mem_resources[isa_hole],
539                                 &hose->mem_resources[next],
540                                 sizeof(struct resource) * (memno - next));
541                 hose->mem_resources[--memno].flags = 0;
542         }
543 }
544 
545 /* Display the domain number in /proc */
546 int pci_proc_domain(struct pci_bus *bus)
547 {
548         return pci_domain_nr(bus);
549 }
550 
551 /* This header fixup will do the resource fixup for all devices as they are
552  * probed, but not for bridge ranges
553  */
554 static void pcibios_fixup_resources(struct pci_dev *dev)
555 {
556         struct pci_controller *hose = pci_bus_to_host(dev->bus);
557         int i;
558 
559         if (!hose) {
560                 pr_err("No host bridge for PCI dev %s !\n",
561                        pci_name(dev));
562                 return;
563         }
564         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
565                 struct resource *res = dev->resource + i;
566                 if (!res->flags)
567                         continue;
568                 if (res->start == 0) {
569                         pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
570                                  pci_name(dev), i,
571                                  (unsigned long long)res->start,
572                                  (unsigned long long)res->end,
573                                  (unsigned int)res->flags);
574                         pr_debug("is unassigned\n");
575                         res->end -= res->start;
576                         res->start = 0;
577                         res->flags |= IORESOURCE_UNSET;
578                         continue;
579                 }
580 
581                 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
582                          pci_name(dev), i,
583                          (unsigned long long)res->start,
584                          (unsigned long long)res->end,
585                          (unsigned int)res->flags);
586         }
587 }
588 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
589 
590 int pcibios_device_add(struct pci_dev *dev)
591 {
592         dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
593 
594         return 0;
595 }
596 
597 /*
598  * Reparent resource children of pr that conflict with res
599  * under res, and make res replace those children.
600  */
601 static int __init reparent_resources(struct resource *parent,
602                                      struct resource *res)
603 {
604         struct resource *p, **pp;
605         struct resource **firstpp = NULL;
606 
607         for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
608                 if (p->end < res->start)
609                         continue;
610                 if (res->end < p->start)
611                         break;
612                 if (p->start < res->start || p->end > res->end)
613                         return -1;      /* not completely contained */
614                 if (firstpp == NULL)
615                         firstpp = pp;
616         }
617         if (firstpp == NULL)
618                 return -1;      /* didn't find any conflicting entries? */
619         res->parent = parent;
620         res->child = *firstpp;
621         res->sibling = *pp;
622         *firstpp = res;
623         *pp = NULL;
624         for (p = res->child; p != NULL; p = p->sibling) {
625                 p->parent = res;
626                 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
627                          p->name,
628                          (unsigned long long)p->start,
629                          (unsigned long long)p->end, res->name);
630         }
631         return 0;
632 }
633 
634 /*
635  *  Handle resources of PCI devices.  If the world were perfect, we could
636  *  just allocate all the resource regions and do nothing more.  It isn't.
637  *  On the other hand, we cannot just re-allocate all devices, as it would
638  *  require us to know lots of host bridge internals.  So we attempt to
639  *  keep as much of the original configuration as possible, but tweak it
640  *  when it's found to be wrong.
641  *
642  *  Known BIOS problems we have to work around:
643  *      - I/O or memory regions not configured
644  *      - regions configured, but not enabled in the command register
645  *      - bogus I/O addresses above 64K used
646  *      - expansion ROMs left enabled (this may sound harmless, but given
647  *        the fact the PCI specs explicitly allow address decoders to be
648  *        shared between expansion ROMs and other resource regions, it's
649  *        at least dangerous)
650  *
651  *  Our solution:
652  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
653  *          This gives us fixed barriers on where we can allocate.
654  *      (2) Allocate resources for all enabled devices.  If there is
655  *          a collision, just mark the resource as unallocated. Also
656  *          disable expansion ROMs during this step.
657  *      (3) Try to allocate resources for disabled devices.  If the
658  *          resources were assigned correctly, everything goes well,
659  *          if they weren't, they won't disturb allocation of other
660  *          resources.
661  *      (4) Assign new addresses to resources which were either
662  *          not configured at all or misconfigured.  If explicitly
663  *          requested by the user, configure expansion ROM address
664  *          as well.
665  */
666 
667 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
668 {
669         struct pci_bus *b;
670         int i;
671         struct resource *res, *pr;
672 
673         pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
674                  pci_domain_nr(bus), bus->number);
675 
676         pci_bus_for_each_resource(bus, res, i) {
677                 if (!res || !res->flags
678                     || res->start > res->end || res->parent)
679                         continue;
680                 if (bus->parent == NULL)
681                         pr = (res->flags & IORESOURCE_IO) ?
682                                 &ioport_resource : &iomem_resource;
683                 else {
684                         /* Don't bother with non-root busses when
685                          * re-assigning all resources. We clear the
686                          * resource flags as if they were colliding
687                          * and as such ensure proper re-allocation
688                          * later.
689                          */
690                         pr = pci_find_parent_resource(bus->self, res);
691                         if (pr == res) {
692                                 /* this happens when the generic PCI
693                                  * code (wrongly) decides that this
694                                  * bridge is transparent  -- paulus
695                                  */
696                                 continue;
697                         }
698                 }
699 
700                 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
701                          bus->self ? pci_name(bus->self) : "PHB",
702                          bus->number, i,
703                          (unsigned long long)res->start,
704                          (unsigned long long)res->end);
705                 pr_debug("[0x%x], parent %p (%s)\n",
706                          (unsigned int)res->flags,
707                          pr, (pr && pr->name) ? pr->name : "nil");
708 
709                 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
710                         struct pci_dev *dev = bus->self;
711 
712                         if (request_resource(pr, res) == 0)
713                                 continue;
714                         /*
715                          * Must be a conflict with an existing entry.
716                          * Move that entry (or entries) under the
717                          * bridge resource and try again.
718                          */
719                         if (reparent_resources(pr, res) == 0)
720                                 continue;
721 
722                         if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
723                             pci_claim_bridge_resource(dev,
724                                                  i + PCI_BRIDGE_RESOURCES) == 0)
725                                 continue;
726 
727                 }
728                 pr_warn("PCI: Cannot allocate resource region ");
729                 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
730                 res->start = res->end = 0;
731                 res->flags = 0;
732         }
733 
734         list_for_each_entry(b, &bus->children, node)
735                 pcibios_allocate_bus_resources(b);
736 }
737 
738 static inline void alloc_resource(struct pci_dev *dev, int idx)
739 {
740         struct resource *pr, *r = &dev->resource[idx];
741 
742         pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
743                  pci_name(dev), idx,
744                  (unsigned long long)r->start,
745                  (unsigned long long)r->end,
746                  (unsigned int)r->flags);
747 
748         pr = pci_find_parent_resource(dev, r);
749         if (!pr || (pr->flags & IORESOURCE_UNSET) ||
750             request_resource(pr, r) < 0) {
751                 pr_warn("PCI: Cannot allocate resource region %d ", idx);
752                 pr_cont("of device %s, will remap\n", pci_name(dev));
753                 if (pr)
754                         pr_debug("PCI:  parent is %p: %016llx-%016llx [%x]\n",
755                                  pr,
756                                  (unsigned long long)pr->start,
757                                  (unsigned long long)pr->end,
758                                  (unsigned int)pr->flags);
759                 /* We'll assign a new address later */
760                 r->flags |= IORESOURCE_UNSET;
761                 r->end -= r->start;
762                 r->start = 0;
763         }
764 }
765 
766 static void __init pcibios_allocate_resources(int pass)
767 {
768         struct pci_dev *dev = NULL;
769         int idx, disabled;
770         u16 command;
771         struct resource *r;
772 
773         for_each_pci_dev(dev) {
774                 pci_read_config_word(dev, PCI_COMMAND, &command);
775                 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
776                         r = &dev->resource[idx];
777                         if (r->parent)          /* Already allocated */
778                                 continue;
779                         if (!r->flags || (r->flags & IORESOURCE_UNSET))
780                                 continue;       /* Not assigned at all */
781                         /* We only allocate ROMs on pass 1 just in case they
782                          * have been screwed up by firmware
783                          */
784                         if (idx == PCI_ROM_RESOURCE)
785                                 disabled = 1;
786                         if (r->flags & IORESOURCE_IO)
787                                 disabled = !(command & PCI_COMMAND_IO);
788                         else
789                                 disabled = !(command & PCI_COMMAND_MEMORY);
790                         if (pass == disabled)
791                                 alloc_resource(dev, idx);
792                 }
793                 if (pass)
794                         continue;
795                 r = &dev->resource[PCI_ROM_RESOURCE];
796                 if (r->flags) {
797                         /* Turn the ROM off, leave the resource region,
798                          * but keep it unregistered.
799                          */
800                         u32 reg;
801                         pci_read_config_dword(dev, dev->rom_base_reg, &reg);
802                         if (reg & PCI_ROM_ADDRESS_ENABLE) {
803                                 pr_debug("PCI: Switching off ROM of %s\n",
804                                          pci_name(dev));
805                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
806                                 pci_write_config_dword(dev, dev->rom_base_reg,
807                                                 reg & ~PCI_ROM_ADDRESS_ENABLE);
808                         }
809                 }
810         }
811 }
812 
813 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
814 {
815         struct pci_controller *hose = pci_bus_to_host(bus);
816         resource_size_t offset;
817         struct resource *res, *pres;
818         int i;
819 
820         pr_debug("Reserving legacy ranges for domain %04x\n",
821                                                         pci_domain_nr(bus));
822 
823         /* Check for IO */
824         if (!(hose->io_resource.flags & IORESOURCE_IO))
825                 goto no_io;
826         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
827         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
828         BUG_ON(res == NULL);
829         res->name = "Legacy IO";
830         res->flags = IORESOURCE_IO;
831         res->start = offset;
832         res->end = (offset + 0xfff) & 0xfffffffful;
833         pr_debug("Candidate legacy IO: %pR\n", res);
834         if (request_resource(&hose->io_resource, res)) {
835                 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
836                        pci_domain_nr(bus), bus->number, res);
837                 kfree(res);
838         }
839 
840  no_io:
841         /* Check for memory */
842         offset = hose->pci_mem_offset;
843         pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
844         for (i = 0; i < 3; i++) {
845                 pres = &hose->mem_resources[i];
846                 if (!(pres->flags & IORESOURCE_MEM))
847                         continue;
848                 pr_debug("hose mem res: %pR\n", pres);
849                 if ((pres->start - offset) <= 0xa0000 &&
850                     (pres->end - offset) >= 0xbffff)
851                         break;
852         }
853         if (i >= 3)
854                 return;
855         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
856         BUG_ON(res == NULL);
857         res->name = "Legacy VGA memory";
858         res->flags = IORESOURCE_MEM;
859         res->start = 0xa0000 + offset;
860         res->end = 0xbffff + offset;
861         pr_debug("Candidate VGA memory: %pR\n", res);
862         if (request_resource(pres, res)) {
863                 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
864                        pci_domain_nr(bus), bus->number, res);
865                 kfree(res);
866         }
867 }
868 
869 void __init pcibios_resource_survey(void)
870 {
871         struct pci_bus *b;
872 
873         /* Allocate and assign resources. If we re-assign everything, then
874          * we skip the allocate phase
875          */
876         list_for_each_entry(b, &pci_root_buses, node)
877                 pcibios_allocate_bus_resources(b);
878 
879         pcibios_allocate_resources(0);
880         pcibios_allocate_resources(1);
881 
882         /* Before we start assigning unassigned resource, we try to reserve
883          * the low IO area and the VGA memory area if they intersect the
884          * bus available resources to avoid allocating things on top of them
885          */
886         list_for_each_entry(b, &pci_root_buses, node)
887                 pcibios_reserve_legacy_regions(b);
888 
889         /* Now proceed to assigning things that were left unassigned */
890         pr_debug("PCI: Assigning unassigned resources...\n");
891         pci_assign_unassigned_resources();
892 }
893 
894 static void pcibios_setup_phb_resources(struct pci_controller *hose,
895                                         struct list_head *resources)
896 {
897         unsigned long io_offset;
898         struct resource *res;
899         int i;
900 
901         /* Hookup PHB IO resource */
902         res = &hose->io_resource;
903 
904         /* Fixup IO space offset */
905         io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
906         res->start = (res->start + io_offset) & 0xffffffffu;
907         res->end = (res->end + io_offset) & 0xffffffffu;
908 
909         if (!res->flags) {
910                 pr_warn("PCI: I/O resource not set for host ");
911                 pr_cont("bridge %pOF (domain %d)\n",
912                         hose->dn, hose->global_number);
913                 /* Workaround for lack of IO resource only on 32-bit */
914                 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
915                 res->end = res->start + IO_SPACE_LIMIT;
916                 res->flags = IORESOURCE_IO;
917         }
918         pci_add_resource_offset(resources, res,
919                 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
920 
921         pr_debug("PCI: PHB IO resource    = %016llx-%016llx [%lx]\n",
922                  (unsigned long long)res->start,
923                  (unsigned long long)res->end,
924                  (unsigned long)res->flags);
925 
926         /* Hookup PHB Memory resources */
927         for (i = 0; i < 3; ++i) {
928                 res = &hose->mem_resources[i];
929                 if (!res->flags) {
930                         if (i > 0)
931                                 continue;
932                         pr_err("PCI: Memory resource 0 not set for ");
933                         pr_cont("host bridge %pOF (domain %d)\n",
934                                 hose->dn, hose->global_number);
935 
936                         /* Workaround for lack of MEM resource only on 32-bit */
937                         res->start = hose->pci_mem_offset;
938                         res->end = (resource_size_t)-1LL;
939                         res->flags = IORESOURCE_MEM;
940 
941                 }
942                 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
943 
944                 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
945                         i, (unsigned long long)res->start,
946                         (unsigned long long)res->end,
947                         (unsigned long)res->flags);
948         }
949 
950         pr_debug("PCI: PHB MEM offset     = %016llx\n",
951                  (unsigned long long)hose->pci_mem_offset);
952         pr_debug("PCI: PHB IO  offset     = %08lx\n",
953                  (unsigned long)hose->io_base_virt - _IO_BASE);
954 }
955 
956 static void pcibios_scan_phb(struct pci_controller *hose)
957 {
958         LIST_HEAD(resources);
959         struct pci_bus *bus;
960         struct device_node *node = hose->dn;
961 
962         pr_debug("PCI: Scanning PHB %pOF\n", node);
963 
964         pcibios_setup_phb_resources(hose, &resources);
965 
966         bus = pci_scan_root_bus(hose->parent, hose->first_busno,
967                                 hose->ops, hose, &resources);
968         if (bus == NULL) {
969                 pr_err("Failed to create bus for PCI domain %04x\n",
970                        hose->global_number);
971                 pci_free_resource_list(&resources);
972                 return;
973         }
974         bus->busn_res.start = hose->first_busno;
975         hose->bus = bus;
976 
977         hose->last_busno = bus->busn_res.end;
978 }
979 
980 static int __init pcibios_init(void)
981 {
982         struct pci_controller *hose, *tmp;
983         int next_busno = 0;
984 
985         pr_info("PCI: Probing PCI hardware\n");
986 
987         /* Scan all of the recorded PCI controllers.  */
988         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
989                 hose->last_busno = 0xff;
990                 pcibios_scan_phb(hose);
991                 if (next_busno <= hose->last_busno)
992                         next_busno = hose->last_busno + 1;
993         }
994         pci_bus_count = next_busno;
995 
996         /* Call common code to handle resource allocation */
997         pcibios_resource_survey();
998         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
999                 if (hose->bus)
1000                         pci_bus_add_devices(hose->bus);
1001         }
1002 
1003         return 0;
1004 }
1005 
1006 subsys_initcall(pcibios_init);
1007 
1008 static struct pci_controller *pci_bus_to_hose(int bus)
1009 {
1010         struct pci_controller *hose, *tmp;
1011 
1012         list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1013                 if (bus >= hose->first_busno && bus <= hose->last_busno)
1014                         return hose;
1015         return NULL;
1016 }
1017 
1018 /* Provide information on locations of various I/O regions in physical
1019  * memory.  Do this on a per-card basis so that we choose the right
1020  * root bridge.
1021  * Note that the returned IO or memory base is a physical address
1022  */
1023 
1024 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1025 {
1026         struct pci_controller *hose;
1027         long result = -EOPNOTSUPP;
1028 
1029         hose = pci_bus_to_hose(bus);
1030         if (!hose)
1031                 return -ENODEV;
1032 
1033         switch (which) {
1034         case IOBASE_BRIDGE_NUMBER:
1035                 return (long)hose->first_busno;
1036         case IOBASE_MEMORY:
1037                 return (long)hose->pci_mem_offset;
1038         case IOBASE_IO:
1039                 return (long)hose->io_base_phys;
1040         case IOBASE_ISA_IO:
1041                 return (long)isa_io_base;
1042         case IOBASE_ISA_MEM:
1043                 return (long)isa_mem_base;
1044         }
1045 
1046         return result;
1047 }
1048 
1049 /*
1050  * Null PCI config access functions, for the case when we can't
1051  * find a hose.
1052  */
1053 #define NULL_PCI_OP(rw, size, type)                                     \
1054 static int                                                              \
1055 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)    \
1056 {                                                                       \
1057         return PCIBIOS_DEVICE_NOT_FOUND;                                \
1058 }
1059 
1060 static int
1061 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1062                  int len, u32 *val)
1063 {
1064         return PCIBIOS_DEVICE_NOT_FOUND;
1065 }
1066 
1067 static int
1068 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1069                   int len, u32 val)
1070 {
1071         return PCIBIOS_DEVICE_NOT_FOUND;
1072 }
1073 
1074 static struct pci_ops null_pci_ops = {
1075         .read = null_read_config,
1076         .write = null_write_config,
1077 };
1078 
1079 /*
1080  * These functions are used early on before PCI scanning is done
1081  * and all of the pci_dev and pci_bus structures have been created.
1082  */
1083 static struct pci_bus *
1084 fake_pci_bus(struct pci_controller *hose, int busnr)
1085 {
1086         static struct pci_bus bus;
1087 
1088         if (!hose)
1089                 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1090 
1091         bus.number = busnr;
1092         bus.sysdata = hose;
1093         bus.ops = hose ? hose->ops : &null_pci_ops;
1094         return &bus;
1095 }
1096 
1097 #define EARLY_PCI_OP(rw, size, type)                                    \
1098 int early_##rw##_config_##size(struct pci_controller *hose, int bus,    \
1099                                int devfn, int offset, type value)       \
1100 {                                                                       \
1101         return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),    \
1102                                             devfn, offset, value);      \
1103 }
1104 
1105 EARLY_PCI_OP(read, byte, u8 *)
1106 EARLY_PCI_OP(read, word, u16 *)
1107 EARLY_PCI_OP(read, dword, u32 *)
1108 EARLY_PCI_OP(write, byte, u8)
1109 EARLY_PCI_OP(write, word, u16)
1110 EARLY_PCI_OP(write, dword, u32)
1111 
1112 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1113                           int cap)
1114 {
1115         return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1116 }
1117 

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