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TOMOYO Linux Cross Reference
Linux/arch/microblaze/pci/pci-common.c

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  1 /*
  2  * Contains common pci routines for ALL ppc platform
  3  * (based on pci_32.c and pci_64.c)
  4  *
  5  * Port for PPC64 David Engebretsen, IBM Corp.
  6  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
  7  *
  8  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
  9  *   Rework, based on alpha PCI code.
 10  *
 11  * Common pmac/prep/chrp pci routines. -- Cort
 12  *
 13  * This program is free software; you can redistribute it and/or
 14  * modify it under the terms of the GNU General Public License
 15  * as published by the Free Software Foundation; either version
 16  * 2 of the License, or (at your option) any later version.
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/pci.h>
 21 #include <linux/string.h>
 22 #include <linux/init.h>
 23 #include <linux/bootmem.h>
 24 #include <linux/mm.h>
 25 #include <linux/list.h>
 26 #include <linux/syscalls.h>
 27 #include <linux/irq.h>
 28 #include <linux/vmalloc.h>
 29 #include <linux/slab.h>
 30 #include <linux/of.h>
 31 #include <linux/of_address.h>
 32 #include <linux/of_pci.h>
 33 
 34 #include <asm/processor.h>
 35 #include <asm/io.h>
 36 #include <asm/pci-bridge.h>
 37 #include <asm/byteorder.h>
 38 
 39 static DEFINE_SPINLOCK(hose_spinlock);
 40 LIST_HEAD(hose_list);
 41 
 42 /* XXX kill that some day ... */
 43 static int global_phb_number;           /* Global phb counter */
 44 
 45 /* ISA Memory physical address */
 46 resource_size_t isa_mem_base;
 47 
 48 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
 49 unsigned int pci_flags;
 50 
 51 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
 52 
 53 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
 54 {
 55         pci_dma_ops = dma_ops;
 56 }
 57 
 58 struct dma_map_ops *get_pci_dma_ops(void)
 59 {
 60         return pci_dma_ops;
 61 }
 62 EXPORT_SYMBOL(get_pci_dma_ops);
 63 
 64 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
 65 {
 66         struct pci_controller *phb;
 67 
 68         phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
 69         if (!phb)
 70                 return NULL;
 71         spin_lock(&hose_spinlock);
 72         phb->global_number = global_phb_number++;
 73         list_add_tail(&phb->list_node, &hose_list);
 74         spin_unlock(&hose_spinlock);
 75         phb->dn = dev;
 76         phb->is_dynamic = mem_init_done;
 77         return phb;
 78 }
 79 
 80 void pcibios_free_controller(struct pci_controller *phb)
 81 {
 82         spin_lock(&hose_spinlock);
 83         list_del(&phb->list_node);
 84         spin_unlock(&hose_spinlock);
 85 
 86         if (phb->is_dynamic)
 87                 kfree(phb);
 88 }
 89 
 90 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
 91 {
 92         return hose->io_resource.end - hose->io_resource.start + 1;
 93 }
 94 
 95 int pcibios_vaddr_is_ioport(void __iomem *address)
 96 {
 97         int ret = 0;
 98         struct pci_controller *hose;
 99         resource_size_t size;
100 
101         spin_lock(&hose_spinlock);
102         list_for_each_entry(hose, &hose_list, list_node) {
103                 size = pcibios_io_size(hose);
104                 if (address >= hose->io_base_virt &&
105                     address < (hose->io_base_virt + size)) {
106                         ret = 1;
107                         break;
108                 }
109         }
110         spin_unlock(&hose_spinlock);
111         return ret;
112 }
113 
114 unsigned long pci_address_to_pio(phys_addr_t address)
115 {
116         struct pci_controller *hose;
117         resource_size_t size;
118         unsigned long ret = ~0;
119 
120         spin_lock(&hose_spinlock);
121         list_for_each_entry(hose, &hose_list, list_node) {
122                 size = pcibios_io_size(hose);
123                 if (address >= hose->io_base_phys &&
124                     address < (hose->io_base_phys + size)) {
125                         unsigned long base =
126                                 (unsigned long)hose->io_base_virt - _IO_BASE;
127                         ret = base + (address - hose->io_base_phys);
128                         break;
129                 }
130         }
131         spin_unlock(&hose_spinlock);
132 
133         return ret;
134 }
135 EXPORT_SYMBOL_GPL(pci_address_to_pio);
136 
137 /*
138  * Return the domain number for this bus.
139  */
140 int pci_domain_nr(struct pci_bus *bus)
141 {
142         struct pci_controller *hose = pci_bus_to_host(bus);
143 
144         return hose->global_number;
145 }
146 EXPORT_SYMBOL(pci_domain_nr);
147 
148 /* This routine is meant to be used early during boot, when the
149  * PCI bus numbers have not yet been assigned, and you need to
150  * issue PCI config cycles to an OF device.
151  * It could also be used to "fix" RTAS config cycles if you want
152  * to set pci_assign_all_buses to 1 and still use RTAS for PCI
153  * config cycles.
154  */
155 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
156 {
157         while (node) {
158                 struct pci_controller *hose, *tmp;
159                 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
160                         if (hose->dn == node)
161                                 return hose;
162                 node = node->parent;
163         }
164         return NULL;
165 }
166 
167 static ssize_t pci_show_devspec(struct device *dev,
168                 struct device_attribute *attr, char *buf)
169 {
170         struct pci_dev *pdev;
171         struct device_node *np;
172 
173         pdev = to_pci_dev(dev);
174         np = pci_device_to_OF_node(pdev);
175         if (np == NULL || np->full_name == NULL)
176                 return 0;
177         return sprintf(buf, "%s", np->full_name);
178 }
179 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
180 
181 /* Add sysfs properties */
182 int pcibios_add_platform_entries(struct pci_dev *pdev)
183 {
184         return device_create_file(&pdev->dev, &dev_attr_devspec);
185 }
186 
187 char __devinit *pcibios_setup(char *str)
188 {
189         return str;
190 }
191 
192 /*
193  * Reads the interrupt pin to determine if interrupt is use by card.
194  * If the interrupt is used, then gets the interrupt line from the
195  * openfirmware and sets it in the pci_dev and pci_config line.
196  */
197 int pci_read_irq_line(struct pci_dev *pci_dev)
198 {
199         struct of_irq oirq;
200         unsigned int virq;
201 
202         /* The current device-tree that iSeries generates from the HV
203          * PCI informations doesn't contain proper interrupt routing,
204          * and all the fallback would do is print out crap, so we
205          * don't attempt to resolve the interrupts here at all, some
206          * iSeries specific fixup does it.
207          *
208          * In the long run, we will hopefully fix the generated device-tree
209          * instead.
210          */
211         pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
212 
213 #ifdef DEBUG
214         memset(&oirq, 0xff, sizeof(oirq));
215 #endif
216         /* Try to get a mapping from the device-tree */
217         if (of_irq_map_pci(pci_dev, &oirq)) {
218                 u8 line, pin;
219 
220                 /* If that fails, lets fallback to what is in the config
221                  * space and map that through the default controller. We
222                  * also set the type to level low since that's what PCI
223                  * interrupts are. If your platform does differently, then
224                  * either provide a proper interrupt tree or don't use this
225                  * function.
226                  */
227                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
228                         return -1;
229                 if (pin == 0)
230                         return -1;
231                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
232                     line == 0xff || line == 0) {
233                         return -1;
234                 }
235                 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
236                          line, pin);
237 
238                 virq = irq_create_mapping(NULL, line);
239                 if (virq != NO_IRQ)
240                         irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
241         } else {
242                 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
243                          oirq.size, oirq.specifier[0], oirq.specifier[1],
244                          oirq.controller ? oirq.controller->full_name :
245                          "<default>");
246 
247                 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
248                                              oirq.size);
249         }
250         if (virq == NO_IRQ) {
251                 pr_debug(" Failed to map !\n");
252                 return -1;
253         }
254 
255         pr_debug(" Mapped to linux irq %d\n", virq);
256 
257         pci_dev->irq = virq;
258 
259         return 0;
260 }
261 EXPORT_SYMBOL(pci_read_irq_line);
262 
263 /*
264  * Platform support for /proc/bus/pci/X/Y mmap()s,
265  * modelled on the sparc64 implementation by Dave Miller.
266  *  -- paulus.
267  */
268 
269 /*
270  * Adjust vm_pgoff of VMA such that it is the physical page offset
271  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
272  *
273  * Basically, the user finds the base address for his device which he wishes
274  * to mmap.  They read the 32-bit value from the config space base register,
275  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
276  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
277  *
278  * Returns negative error code on failure, zero on success.
279  */
280 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
281                                                resource_size_t *offset,
282                                                enum pci_mmap_state mmap_state)
283 {
284         struct pci_controller *hose = pci_bus_to_host(dev->bus);
285         unsigned long io_offset = 0;
286         int i, res_bit;
287 
288         if (hose == 0)
289                 return NULL;            /* should never happen */
290 
291         /* If memory, add on the PCI bridge address offset */
292         if (mmap_state == pci_mmap_mem) {
293 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
294                 *offset += hose->pci_mem_offset;
295 #endif
296                 res_bit = IORESOURCE_MEM;
297         } else {
298                 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
299                 *offset += io_offset;
300                 res_bit = IORESOURCE_IO;
301         }
302 
303         /*
304          * Check that the offset requested corresponds to one of the
305          * resources of the device.
306          */
307         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
308                 struct resource *rp = &dev->resource[i];
309                 int flags = rp->flags;
310 
311                 /* treat ROM as memory (should be already) */
312                 if (i == PCI_ROM_RESOURCE)
313                         flags |= IORESOURCE_MEM;
314 
315                 /* Active and same type? */
316                 if ((flags & res_bit) == 0)
317                         continue;
318 
319                 /* In the range of this resource? */
320                 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
321                         continue;
322 
323                 /* found it! construct the final physical address */
324                 if (mmap_state == pci_mmap_io)
325                         *offset += hose->io_base_phys - io_offset;
326                 return rp;
327         }
328 
329         return NULL;
330 }
331 
332 /*
333  * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
334  * device mapping.
335  */
336 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
337                                       pgprot_t protection,
338                                       enum pci_mmap_state mmap_state,
339                                       int write_combine)
340 {
341         pgprot_t prot = protection;
342 
343         /* Write combine is always 0 on non-memory space mappings. On
344          * memory space, if the user didn't pass 1, we check for a
345          * "prefetchable" resource. This is a bit hackish, but we use
346          * this to workaround the inability of /sysfs to provide a write
347          * combine bit
348          */
349         if (mmap_state != pci_mmap_mem)
350                 write_combine = 0;
351         else if (write_combine == 0) {
352                 if (rp->flags & IORESOURCE_PREFETCH)
353                         write_combine = 1;
354         }
355 
356         return pgprot_noncached(prot);
357 }
358 
359 /*
360  * This one is used by /dev/mem and fbdev who have no clue about the
361  * PCI device, it tries to find the PCI device first and calls the
362  * above routine
363  */
364 pgprot_t pci_phys_mem_access_prot(struct file *file,
365                                   unsigned long pfn,
366                                   unsigned long size,
367                                   pgprot_t prot)
368 {
369         struct pci_dev *pdev = NULL;
370         struct resource *found = NULL;
371         resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
372         int i;
373 
374         if (page_is_ram(pfn))
375                 return prot;
376 
377         prot = pgprot_noncached(prot);
378         for_each_pci_dev(pdev) {
379                 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
380                         struct resource *rp = &pdev->resource[i];
381                         int flags = rp->flags;
382 
383                         /* Active and same type? */
384                         if ((flags & IORESOURCE_MEM) == 0)
385                                 continue;
386                         /* In the range of this resource? */
387                         if (offset < (rp->start & PAGE_MASK) ||
388                             offset > rp->end)
389                                 continue;
390                         found = rp;
391                         break;
392                 }
393                 if (found)
394                         break;
395         }
396         if (found) {
397                 if (found->flags & IORESOURCE_PREFETCH)
398                         prot = pgprot_noncached_wc(prot);
399                 pci_dev_put(pdev);
400         }
401 
402         pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
403                  (unsigned long long)offset, pgprot_val(prot));
404 
405         return prot;
406 }
407 
408 /*
409  * Perform the actual remap of the pages for a PCI device mapping, as
410  * appropriate for this architecture.  The region in the process to map
411  * is described by vm_start and vm_end members of VMA, the base physical
412  * address is found in vm_pgoff.
413  * The pci device structure is provided so that architectures may make mapping
414  * decisions on a per-device or per-bus basis.
415  *
416  * Returns a negative error code on failure, zero on success.
417  */
418 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
419                         enum pci_mmap_state mmap_state, int write_combine)
420 {
421         resource_size_t offset =
422                 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
423         struct resource *rp;
424         int ret;
425 
426         rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
427         if (rp == NULL)
428                 return -EINVAL;
429 
430         vma->vm_pgoff = offset >> PAGE_SHIFT;
431         vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
432                                                   vma->vm_page_prot,
433                                                   mmap_state, write_combine);
434 
435         ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
436                                vma->vm_end - vma->vm_start, vma->vm_page_prot);
437 
438         return ret;
439 }
440 
441 /* This provides legacy IO read access on a bus */
442 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
443 {
444         unsigned long offset;
445         struct pci_controller *hose = pci_bus_to_host(bus);
446         struct resource *rp = &hose->io_resource;
447         void __iomem *addr;
448 
449         /* Check if port can be supported by that bus. We only check
450          * the ranges of the PHB though, not the bus itself as the rules
451          * for forwarding legacy cycles down bridges are not our problem
452          * here. So if the host bridge supports it, we do it.
453          */
454         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
455         offset += port;
456 
457         if (!(rp->flags & IORESOURCE_IO))
458                 return -ENXIO;
459         if (offset < rp->start || (offset + size) > rp->end)
460                 return -ENXIO;
461         addr = hose->io_base_virt + port;
462 
463         switch (size) {
464         case 1:
465                 *((u8 *)val) = in_8(addr);
466                 return 1;
467         case 2:
468                 if (port & 1)
469                         return -EINVAL;
470                 *((u16 *)val) = in_le16(addr);
471                 return 2;
472         case 4:
473                 if (port & 3)
474                         return -EINVAL;
475                 *((u32 *)val) = in_le32(addr);
476                 return 4;
477         }
478         return -EINVAL;
479 }
480 
481 /* This provides legacy IO write access on a bus */
482 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
483 {
484         unsigned long offset;
485         struct pci_controller *hose = pci_bus_to_host(bus);
486         struct resource *rp = &hose->io_resource;
487         void __iomem *addr;
488 
489         /* Check if port can be supported by that bus. We only check
490          * the ranges of the PHB though, not the bus itself as the rules
491          * for forwarding legacy cycles down bridges are not our problem
492          * here. So if the host bridge supports it, we do it.
493          */
494         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
495         offset += port;
496 
497         if (!(rp->flags & IORESOURCE_IO))
498                 return -ENXIO;
499         if (offset < rp->start || (offset + size) > rp->end)
500                 return -ENXIO;
501         addr = hose->io_base_virt + port;
502 
503         /* WARNING: The generic code is idiotic. It gets passed a pointer
504          * to what can be a 1, 2 or 4 byte quantity and always reads that
505          * as a u32, which means that we have to correct the location of
506          * the data read within those 32 bits for size 1 and 2
507          */
508         switch (size) {
509         case 1:
510                 out_8(addr, val >> 24);
511                 return 1;
512         case 2:
513                 if (port & 1)
514                         return -EINVAL;
515                 out_le16(addr, val >> 16);
516                 return 2;
517         case 4:
518                 if (port & 3)
519                         return -EINVAL;
520                 out_le32(addr, val);
521                 return 4;
522         }
523         return -EINVAL;
524 }
525 
526 /* This provides legacy IO or memory mmap access on a bus */
527 int pci_mmap_legacy_page_range(struct pci_bus *bus,
528                                struct vm_area_struct *vma,
529                                enum pci_mmap_state mmap_state)
530 {
531         struct pci_controller *hose = pci_bus_to_host(bus);
532         resource_size_t offset =
533                 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
534         resource_size_t size = vma->vm_end - vma->vm_start;
535         struct resource *rp;
536 
537         pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
538                  pci_domain_nr(bus), bus->number,
539                  mmap_state == pci_mmap_mem ? "MEM" : "IO",
540                  (unsigned long long)offset,
541                  (unsigned long long)(offset + size - 1));
542 
543         if (mmap_state == pci_mmap_mem) {
544                 /* Hack alert !
545                  *
546                  * Because X is lame and can fail starting if it gets an error
547                  * trying to mmap legacy_mem (instead of just moving on without
548                  * legacy memory access) we fake it here by giving it anonymous
549                  * memory, effectively behaving just like /dev/zero
550                  */
551                 if ((offset + size) > hose->isa_mem_size) {
552 #ifdef CONFIG_MMU
553                         printk(KERN_DEBUG
554                                 "Process %s (pid:%d) mapped non-existing PCI"
555                                 "legacy memory for 0%04x:%02x\n",
556                                 current->comm, current->pid, pci_domain_nr(bus),
557                                                                 bus->number);
558 #endif
559                         if (vma->vm_flags & VM_SHARED)
560                                 return shmem_zero_setup(vma);
561                         return 0;
562                 }
563                 offset += hose->isa_mem_phys;
564         } else {
565                 unsigned long io_offset = (unsigned long)hose->io_base_virt - \
566                                                                 _IO_BASE;
567                 unsigned long roffset = offset + io_offset;
568                 rp = &hose->io_resource;
569                 if (!(rp->flags & IORESOURCE_IO))
570                         return -ENXIO;
571                 if (roffset < rp->start || (roffset + size) > rp->end)
572                         return -ENXIO;
573                 offset += hose->io_base_phys;
574         }
575         pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
576 
577         vma->vm_pgoff = offset >> PAGE_SHIFT;
578         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
579         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
580                                vma->vm_end - vma->vm_start,
581                                vma->vm_page_prot);
582 }
583 
584 void pci_resource_to_user(const struct pci_dev *dev, int bar,
585                           const struct resource *rsrc,
586                           resource_size_t *start, resource_size_t *end)
587 {
588         struct pci_controller *hose = pci_bus_to_host(dev->bus);
589         resource_size_t offset = 0;
590 
591         if (hose == NULL)
592                 return;
593 
594         if (rsrc->flags & IORESOURCE_IO)
595                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
596 
597         /* We pass a fully fixed up address to userland for MMIO instead of
598          * a BAR value because X is lame and expects to be able to use that
599          * to pass to /dev/mem !
600          *
601          * That means that we'll have potentially 64 bits values where some
602          * userland apps only expect 32 (like X itself since it thinks only
603          * Sparc has 64 bits MMIO) but if we don't do that, we break it on
604          * 32 bits CHRPs :-(
605          *
606          * Hopefully, the sysfs insterface is immune to that gunk. Once X
607          * has been fixed (and the fix spread enough), we can re-enable the
608          * 2 lines below and pass down a BAR value to userland. In that case
609          * we'll also have to re-enable the matching code in
610          * __pci_mmap_make_offset().
611          *
612          * BenH.
613          */
614 #if 0
615         else if (rsrc->flags & IORESOURCE_MEM)
616                 offset = hose->pci_mem_offset;
617 #endif
618 
619         *start = rsrc->start - offset;
620         *end = rsrc->end - offset;
621 }
622 
623 /**
624  * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
625  * @hose: newly allocated pci_controller to be setup
626  * @dev: device node of the host bridge
627  * @primary: set if primary bus (32 bits only, soon to be deprecated)
628  *
629  * This function will parse the "ranges" property of a PCI host bridge device
630  * node and setup the resource mapping of a pci controller based on its
631  * content.
632  *
633  * Life would be boring if it wasn't for a few issues that we have to deal
634  * with here:
635  *
636  *   - We can only cope with one IO space range and up to 3 Memory space
637  *     ranges. However, some machines (thanks Apple !) tend to split their
638  *     space into lots of small contiguous ranges. So we have to coalesce.
639  *
640  *   - We can only cope with all memory ranges having the same offset
641  *     between CPU addresses and PCI addresses. Unfortunately, some bridges
642  *     are setup for a large 1:1 mapping along with a small "window" which
643  *     maps PCI address 0 to some arbitrary high address of the CPU space in
644  *     order to give access to the ISA memory hole.
645  *     The way out of here that I've chosen for now is to always set the
646  *     offset based on the first resource found, then override it if we
647  *     have a different offset and the previous was set by an ISA hole.
648  *
649  *   - Some busses have IO space not starting at 0, which causes trouble with
650  *     the way we do our IO resource renumbering. The code somewhat deals with
651  *     it for 64 bits but I would expect problems on 32 bits.
652  *
653  *   - Some 32 bits platforms such as 4xx can have physical space larger than
654  *     32 bits so we need to use 64 bits values for the parsing
655  */
656 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
657                                             struct device_node *dev,
658                                             int primary)
659 {
660         const u32 *ranges;
661         int rlen;
662         int pna = of_n_addr_cells(dev);
663         int np = pna + 5;
664         int memno = 0, isa_hole = -1;
665         u32 pci_space;
666         unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
667         unsigned long long isa_mb = 0;
668         struct resource *res;
669 
670         printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
671                dev->full_name, primary ? "(primary)" : "");
672 
673         /* Get ranges property */
674         ranges = of_get_property(dev, "ranges", &rlen);
675         if (ranges == NULL)
676                 return;
677 
678         /* Parse it */
679         pr_debug("Parsing ranges property...\n");
680         while ((rlen -= np * 4) >= 0) {
681                 /* Read next ranges element */
682                 pci_space = ranges[0];
683                 pci_addr = of_read_number(ranges + 1, 2);
684                 cpu_addr = of_translate_address(dev, ranges + 3);
685                 size = of_read_number(ranges + pna + 3, 2);
686 
687                 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx "
688                                 "cpu_addr:0x%016llx size:0x%016llx\n",
689                                         pci_space, pci_addr, cpu_addr, size);
690 
691                 ranges += np;
692 
693                 /* If we failed translation or got a zero-sized region
694                  * (some FW try to feed us with non sensical zero sized regions
695                  * such as power3 which look like some kind of attempt
696                  * at exposing the VGA memory hole)
697                  */
698                 if (cpu_addr == OF_BAD_ADDR || size == 0)
699                         continue;
700 
701                 /* Now consume following elements while they are contiguous */
702                 for (; rlen >= np * sizeof(u32);
703                      ranges += np, rlen -= np * 4) {
704                         if (ranges[0] != pci_space)
705                                 break;
706                         pci_next = of_read_number(ranges + 1, 2);
707                         cpu_next = of_translate_address(dev, ranges + 3);
708                         if (pci_next != pci_addr + size ||
709                             cpu_next != cpu_addr + size)
710                                 break;
711                         size += of_read_number(ranges + pna + 3, 2);
712                 }
713 
714                 /* Act based on address space type */
715                 res = NULL;
716                 switch ((pci_space >> 24) & 0x3) {
717                 case 1:         /* PCI IO space */
718                         printk(KERN_INFO
719                                "  IO 0x%016llx..0x%016llx -> 0x%016llx\n",
720                                cpu_addr, cpu_addr + size - 1, pci_addr);
721 
722                         /* We support only one IO range */
723                         if (hose->pci_io_size) {
724                                 printk(KERN_INFO
725                                        " \\--> Skipped (too many) !\n");
726                                 continue;
727                         }
728                         /* On 32 bits, limit I/O space to 16MB */
729                         if (size > 0x01000000)
730                                 size = 0x01000000;
731 
732                         /* 32 bits needs to map IOs here */
733                         hose->io_base_virt = ioremap(cpu_addr, size);
734 
735                         /* Expect trouble if pci_addr is not 0 */
736                         if (primary)
737                                 isa_io_base =
738                                         (unsigned long)hose->io_base_virt;
739                         /* pci_io_size and io_base_phys always represent IO
740                          * space starting at 0 so we factor in pci_addr
741                          */
742                         hose->pci_io_size = pci_addr + size;
743                         hose->io_base_phys = cpu_addr - pci_addr;
744 
745                         /* Build resource */
746                         res = &hose->io_resource;
747                         res->flags = IORESOURCE_IO;
748                         res->start = pci_addr;
749                         break;
750                 case 2:         /* PCI Memory space */
751                 case 3:         /* PCI 64 bits Memory space */
752                         printk(KERN_INFO
753                                " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
754                                cpu_addr, cpu_addr + size - 1, pci_addr,
755                                (pci_space & 0x40000000) ? "Prefetch" : "");
756 
757                         /* We support only 3 memory ranges */
758                         if (memno >= 3) {
759                                 printk(KERN_INFO
760                                        " \\--> Skipped (too many) !\n");
761                                 continue;
762                         }
763                         /* Handles ISA memory hole space here */
764                         if (pci_addr == 0) {
765                                 isa_mb = cpu_addr;
766                                 isa_hole = memno;
767                                 if (primary || isa_mem_base == 0)
768                                         isa_mem_base = cpu_addr;
769                                 hose->isa_mem_phys = cpu_addr;
770                                 hose->isa_mem_size = size;
771                         }
772 
773                         /* We get the PCI/Mem offset from the first range or
774                          * the, current one if the offset came from an ISA
775                          * hole. If they don't match, bugger.
776                          */
777                         if (memno == 0 ||
778                             (isa_hole >= 0 && pci_addr != 0 &&
779                              hose->pci_mem_offset == isa_mb))
780                                 hose->pci_mem_offset = cpu_addr - pci_addr;
781                         else if (pci_addr != 0 &&
782                                  hose->pci_mem_offset != cpu_addr - pci_addr) {
783                                 printk(KERN_INFO
784                                        " \\--> Skipped (offset mismatch) !\n");
785                                 continue;
786                         }
787 
788                         /* Build resource */
789                         res = &hose->mem_resources[memno++];
790                         res->flags = IORESOURCE_MEM;
791                         if (pci_space & 0x40000000)
792                                 res->flags |= IORESOURCE_PREFETCH;
793                         res->start = cpu_addr;
794                         break;
795                 }
796                 if (res != NULL) {
797                         res->name = dev->full_name;
798                         res->end = res->start + size - 1;
799                         res->parent = NULL;
800                         res->sibling = NULL;
801                         res->child = NULL;
802                 }
803         }
804 
805         /* If there's an ISA hole and the pci_mem_offset is -not- matching
806          * the ISA hole offset, then we need to remove the ISA hole from
807          * the resource list for that brige
808          */
809         if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
810                 unsigned int next = isa_hole + 1;
811                 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
812                 if (next < memno)
813                         memmove(&hose->mem_resources[isa_hole],
814                                 &hose->mem_resources[next],
815                                 sizeof(struct resource) * (memno - next));
816                 hose->mem_resources[--memno].flags = 0;
817         }
818 }
819 
820 /* Decide whether to display the domain number in /proc */
821 int pci_proc_domain(struct pci_bus *bus)
822 {
823         struct pci_controller *hose = pci_bus_to_host(bus);
824 
825         if (!(pci_flags & PCI_ENABLE_PROC_DOMAINS))
826                 return 0;
827         if (pci_flags & PCI_COMPAT_DOMAIN_0)
828                 return hose->global_number != 0;
829         return 1;
830 }
831 
832 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
833                              struct resource *res)
834 {
835         resource_size_t offset = 0, mask = (resource_size_t)-1;
836         struct pci_controller *hose = pci_bus_to_host(dev->bus);
837 
838         if (!hose)
839                 return;
840         if (res->flags & IORESOURCE_IO) {
841                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
842                 mask = 0xffffffffu;
843         } else if (res->flags & IORESOURCE_MEM)
844                 offset = hose->pci_mem_offset;
845 
846         region->start = (res->start - offset) & mask;
847         region->end = (res->end - offset) & mask;
848 }
849 EXPORT_SYMBOL(pcibios_resource_to_bus);
850 
851 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
852                              struct pci_bus_region *region)
853 {
854         resource_size_t offset = 0, mask = (resource_size_t)-1;
855         struct pci_controller *hose = pci_bus_to_host(dev->bus);
856 
857         if (!hose)
858                 return;
859         if (res->flags & IORESOURCE_IO) {
860                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
861                 mask = 0xffffffffu;
862         } else if (res->flags & IORESOURCE_MEM)
863                 offset = hose->pci_mem_offset;
864         res->start = (region->start + offset) & mask;
865         res->end = (region->end + offset) & mask;
866 }
867 EXPORT_SYMBOL(pcibios_bus_to_resource);
868 
869 /* Fixup a bus resource into a linux resource */
870 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
871 {
872         struct pci_controller *hose = pci_bus_to_host(dev->bus);
873         resource_size_t offset = 0, mask = (resource_size_t)-1;
874 
875         if (res->flags & IORESOURCE_IO) {
876                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
877                 mask = 0xffffffffu;
878         } else if (res->flags & IORESOURCE_MEM)
879                 offset = hose->pci_mem_offset;
880 
881         res->start = (res->start + offset) & mask;
882         res->end = (res->end + offset) & mask;
883 }
884 
885 /* This header fixup will do the resource fixup for all devices as they are
886  * probed, but not for bridge ranges
887  */
888 static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
889 {
890         struct pci_controller *hose = pci_bus_to_host(dev->bus);
891         int i;
892 
893         if (!hose) {
894                 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
895                        pci_name(dev));
896                 return;
897         }
898         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
899                 struct resource *res = dev->resource + i;
900                 if (!res->flags)
901                         continue;
902                 /* On platforms that have PCI_PROBE_ONLY set, we don't
903                  * consider 0 as an unassigned BAR value. It's technically
904                  * a valid value, but linux doesn't like it... so when we can
905                  * re-assign things, we do so, but if we can't, we keep it
906                  * around and hope for the best...
907                  */
908                 if (res->start == 0 && !(pci_flags & PCI_PROBE_ONLY)) {
909                         pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
910                                                         "is unassigned\n",
911                                  pci_name(dev), i,
912                                  (unsigned long long)res->start,
913                                  (unsigned long long)res->end,
914                                  (unsigned int)res->flags);
915                         res->end -= res->start;
916                         res->start = 0;
917                         res->flags |= IORESOURCE_UNSET;
918                         continue;
919                 }
920 
921                 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
922                          pci_name(dev), i,
923                          (unsigned long long)res->start,\
924                          (unsigned long long)res->end,
925                          (unsigned int)res->flags);
926 
927                 fixup_resource(res, dev);
928 
929                 pr_debug("PCI:%s            %016llx-%016llx\n",
930                          pci_name(dev),
931                          (unsigned long long)res->start,
932                          (unsigned long long)res->end);
933         }
934 }
935 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
936 
937 /* This function tries to figure out if a bridge resource has been initialized
938  * by the firmware or not. It doesn't have to be absolutely bullet proof, but
939  * things go more smoothly when it gets it right. It should covers cases such
940  * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
941  */
942 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
943                                                            struct resource *res)
944 {
945         struct pci_controller *hose = pci_bus_to_host(bus);
946         struct pci_dev *dev = bus->self;
947         resource_size_t offset;
948         u16 command;
949         int i;
950 
951         /* We don't do anything if PCI_PROBE_ONLY is set */
952         if (pci_flags & PCI_PROBE_ONLY)
953                 return 0;
954 
955         /* Job is a bit different between memory and IO */
956         if (res->flags & IORESOURCE_MEM) {
957                 /* If the BAR is non-0 (res != pci_mem_offset) then it's
958                  * probably been initialized by somebody
959                  */
960                 if (res->start != hose->pci_mem_offset)
961                         return 0;
962 
963                 /* The BAR is 0, let's check if memory decoding is enabled on
964                  * the bridge. If not, we consider it unassigned
965                  */
966                 pci_read_config_word(dev, PCI_COMMAND, &command);
967                 if ((command & PCI_COMMAND_MEMORY) == 0)
968                         return 1;
969 
970                 /* Memory decoding is enabled and the BAR is 0. If any of
971                  * the bridge resources covers that starting address (0 then
972                  * it's good enough for us for memory
973                  */
974                 for (i = 0; i < 3; i++) {
975                         if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
976                            hose->mem_resources[i].start == hose->pci_mem_offset)
977                                 return 0;
978                 }
979 
980                 /* Well, it starts at 0 and we know it will collide so we may as
981                  * well consider it as unassigned. That covers the Apple case.
982                  */
983                 return 1;
984         } else {
985                 /* If the BAR is non-0, then we consider it assigned */
986                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
987                 if (((res->start - offset) & 0xfffffffful) != 0)
988                         return 0;
989 
990                 /* Here, we are a bit different than memory as typically IO
991                  * space starting at low addresses -is- valid. What we do
992                  * instead if that we consider as unassigned anything that
993                  * doesn't have IO enabled in the PCI command register,
994                  * and that's it.
995                  */
996                 pci_read_config_word(dev, PCI_COMMAND, &command);
997                 if (command & PCI_COMMAND_IO)
998                         return 0;
999 
1000                 /* It's starting at 0 and IO is disabled in the bridge, consider
1001                  * it unassigned
1002                  */
1003                 return 1;
1004         }
1005 }
1006 
1007 /* Fixup resources of a PCI<->PCI bridge */
1008 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1009 {
1010         struct resource *res;
1011         int i;
1012 
1013         struct pci_dev *dev = bus->self;
1014 
1015         pci_bus_for_each_resource(bus, res, i) {
1016                 res = bus->resource[i];
1017                 if (!res)
1018                         continue;
1019                 if (!res->flags)
1020                         continue;
1021                 if (i >= 3 && bus->self->transparent)
1022                         continue;
1023 
1024                 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1025                          pci_name(dev), i,
1026                          (unsigned long long)res->start,\
1027                          (unsigned long long)res->end,
1028                          (unsigned int)res->flags);
1029 
1030                 /* Perform fixup */
1031                 fixup_resource(res, dev);
1032 
1033                 /* Try to detect uninitialized P2P bridge resources,
1034                  * and clear them out so they get re-assigned later
1035                  */
1036                 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1037                         res->flags = 0;
1038                         pr_debug("PCI:%s            (unassigned)\n",
1039                                                                 pci_name(dev));
1040                 } else {
1041                         pr_debug("PCI:%s            %016llx-%016llx\n",
1042                                  pci_name(dev),
1043                                  (unsigned long long)res->start,
1044                                  (unsigned long long)res->end);
1045                 }
1046         }
1047 }
1048 
1049 void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
1050 {
1051         /* Fix up the bus resources for P2P bridges */
1052         if (bus->self != NULL)
1053                 pcibios_fixup_bridge(bus);
1054 }
1055 
1056 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1057 {
1058         struct pci_dev *dev;
1059 
1060         pr_debug("PCI: Fixup bus devices %d (%s)\n",
1061                  bus->number, bus->self ? pci_name(bus->self) : "PHB");
1062 
1063         list_for_each_entry(dev, &bus->devices, bus_list) {
1064                 /* Setup OF node pointer in archdata */
1065                 dev->dev.of_node = pci_device_to_OF_node(dev);
1066 
1067                 /* Fixup NUMA node as it may not be setup yet by the generic
1068                  * code and is needed by the DMA init
1069                  */
1070                 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1071 
1072                 /* Hook up default DMA ops */
1073                 set_dma_ops(&dev->dev, pci_dma_ops);
1074                 dev->dev.archdata.dma_data = (void *)PCI_DRAM_OFFSET;
1075 
1076                 /* Read default IRQs and fixup if necessary */
1077                 pci_read_irq_line(dev);
1078         }
1079 }
1080 
1081 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1082 {
1083         /* When called from the generic PCI probe, read PCI<->PCI bridge
1084          * bases. This is -not- called when generating the PCI tree from
1085          * the OF device-tree.
1086          */
1087         if (bus->self != NULL)
1088                 pci_read_bridge_bases(bus);
1089 
1090         /* Now fixup the bus bus */
1091         pcibios_setup_bus_self(bus);
1092 
1093         /* Now fixup devices on that bus */
1094         pcibios_setup_bus_devices(bus);
1095 }
1096 EXPORT_SYMBOL(pcibios_fixup_bus);
1097 
1098 static int skip_isa_ioresource_align(struct pci_dev *dev)
1099 {
1100         if ((pci_flags & PCI_CAN_SKIP_ISA_ALIGN) &&
1101             !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1102                 return 1;
1103         return 0;
1104 }
1105 
1106 /*
1107  * We need to avoid collisions with `mirrored' VGA ports
1108  * and other strange ISA hardware, so we always want the
1109  * addresses to be allocated in the 0x000-0x0ff region
1110  * modulo 0x400.
1111  *
1112  * Why? Because some silly external IO cards only decode
1113  * the low 10 bits of the IO address. The 0x00-0xff region
1114  * is reserved for motherboard devices that decode all 16
1115  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1116  * but we want to try to avoid allocating at 0x2900-0x2bff
1117  * which might have be mirrored at 0x0100-0x03ff..
1118  */
1119 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1120                                 resource_size_t size, resource_size_t align)
1121 {
1122         struct pci_dev *dev = data;
1123         resource_size_t start = res->start;
1124 
1125         if (res->flags & IORESOURCE_IO) {
1126                 if (skip_isa_ioresource_align(dev))
1127                         return start;
1128                 if (start & 0x300)
1129                         start = (start + 0x3ff) & ~0x3ff;
1130         }
1131 
1132         return start;
1133 }
1134 EXPORT_SYMBOL(pcibios_align_resource);
1135 
1136 /*
1137  * Reparent resource children of pr that conflict with res
1138  * under res, and make res replace those children.
1139  */
1140 static int __init reparent_resources(struct resource *parent,
1141                                      struct resource *res)
1142 {
1143         struct resource *p, **pp;
1144         struct resource **firstpp = NULL;
1145 
1146         for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1147                 if (p->end < res->start)
1148                         continue;
1149                 if (res->end < p->start)
1150                         break;
1151                 if (p->start < res->start || p->end > res->end)
1152                         return -1;      /* not completely contained */
1153                 if (firstpp == NULL)
1154                         firstpp = pp;
1155         }
1156         if (firstpp == NULL)
1157                 return -1;      /* didn't find any conflicting entries? */
1158         res->parent = parent;
1159         res->child = *firstpp;
1160         res->sibling = *pp;
1161         *firstpp = res;
1162         *pp = NULL;
1163         for (p = res->child; p != NULL; p = p->sibling) {
1164                 p->parent = res;
1165                 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1166                          p->name,
1167                          (unsigned long long)p->start,
1168                          (unsigned long long)p->end, res->name);
1169         }
1170         return 0;
1171 }
1172 
1173 /*
1174  *  Handle resources of PCI devices.  If the world were perfect, we could
1175  *  just allocate all the resource regions and do nothing more.  It isn't.
1176  *  On the other hand, we cannot just re-allocate all devices, as it would
1177  *  require us to know lots of host bridge internals.  So we attempt to
1178  *  keep as much of the original configuration as possible, but tweak it
1179  *  when it's found to be wrong.
1180  *
1181  *  Known BIOS problems we have to work around:
1182  *      - I/O or memory regions not configured
1183  *      - regions configured, but not enabled in the command register
1184  *      - bogus I/O addresses above 64K used
1185  *      - expansion ROMs left enabled (this may sound harmless, but given
1186  *        the fact the PCI specs explicitly allow address decoders to be
1187  *        shared between expansion ROMs and other resource regions, it's
1188  *        at least dangerous)
1189  *
1190  *  Our solution:
1191  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1192  *          This gives us fixed barriers on where we can allocate.
1193  *      (2) Allocate resources for all enabled devices.  If there is
1194  *          a collision, just mark the resource as unallocated. Also
1195  *          disable expansion ROMs during this step.
1196  *      (3) Try to allocate resources for disabled devices.  If the
1197  *          resources were assigned correctly, everything goes well,
1198  *          if they weren't, they won't disturb allocation of other
1199  *          resources.
1200  *      (4) Assign new addresses to resources which were either
1201  *          not configured at all or misconfigured.  If explicitly
1202  *          requested by the user, configure expansion ROM address
1203  *          as well.
1204  */
1205 
1206 void pcibios_allocate_bus_resources(struct pci_bus *bus)
1207 {
1208         struct pci_bus *b;
1209         int i;
1210         struct resource *res, *pr;
1211 
1212         pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1213                  pci_domain_nr(bus), bus->number);
1214 
1215         pci_bus_for_each_resource(bus, res, i) {
1216                 res = bus->resource[i];
1217                 if (!res || !res->flags
1218                     || res->start > res->end || res->parent)
1219                         continue;
1220                 if (bus->parent == NULL)
1221                         pr = (res->flags & IORESOURCE_IO) ?
1222                                 &ioport_resource : &iomem_resource;
1223                 else {
1224                         /* Don't bother with non-root busses when
1225                          * re-assigning all resources. We clear the
1226                          * resource flags as if they were colliding
1227                          * and as such ensure proper re-allocation
1228                          * later.
1229                          */
1230                         if (pci_flags & PCI_REASSIGN_ALL_RSRC)
1231                                 goto clear_resource;
1232                         pr = pci_find_parent_resource(bus->self, res);
1233                         if (pr == res) {
1234                                 /* this happens when the generic PCI
1235                                  * code (wrongly) decides that this
1236                                  * bridge is transparent  -- paulus
1237                                  */
1238                                 continue;
1239                         }
1240                 }
1241 
1242                 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1243                          "[0x%x], parent %p (%s)\n",
1244                          bus->self ? pci_name(bus->self) : "PHB",
1245                          bus->number, i,
1246                          (unsigned long long)res->start,
1247                          (unsigned long long)res->end,
1248                          (unsigned int)res->flags,
1249                          pr, (pr && pr->name) ? pr->name : "nil");
1250 
1251                 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1252                         if (request_resource(pr, res) == 0)
1253                                 continue;
1254                         /*
1255                          * Must be a conflict with an existing entry.
1256                          * Move that entry (or entries) under the
1257                          * bridge resource and try again.
1258                          */
1259                         if (reparent_resources(pr, res) == 0)
1260                                 continue;
1261                 }
1262                 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1263                        "%d of PCI bridge %d, will remap\n", i, bus->number);
1264 clear_resource:
1265                 res->start = res->end = 0;
1266                 res->flags = 0;
1267         }
1268 
1269         list_for_each_entry(b, &bus->children, node)
1270                 pcibios_allocate_bus_resources(b);
1271 }
1272 
1273 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1274 {
1275         struct resource *pr, *r = &dev->resource[idx];
1276 
1277         pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1278                  pci_name(dev), idx,
1279                  (unsigned long long)r->start,
1280                  (unsigned long long)r->end,
1281                  (unsigned int)r->flags);
1282 
1283         pr = pci_find_parent_resource(dev, r);
1284         if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1285             request_resource(pr, r) < 0) {
1286                 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1287                        " of device %s, will remap\n", idx, pci_name(dev));
1288                 if (pr)
1289                         pr_debug("PCI:  parent is %p: %016llx-%016llx [%x]\n",
1290                                  pr,
1291                                  (unsigned long long)pr->start,
1292                                  (unsigned long long)pr->end,
1293                                  (unsigned int)pr->flags);
1294                 /* We'll assign a new address later */
1295                 r->flags |= IORESOURCE_UNSET;
1296                 r->end -= r->start;
1297                 r->start = 0;
1298         }
1299 }
1300 
1301 static void __init pcibios_allocate_resources(int pass)
1302 {
1303         struct pci_dev *dev = NULL;
1304         int idx, disabled;
1305         u16 command;
1306         struct resource *r;
1307 
1308         for_each_pci_dev(dev) {
1309                 pci_read_config_word(dev, PCI_COMMAND, &command);
1310                 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1311                         r = &dev->resource[idx];
1312                         if (r->parent)          /* Already allocated */
1313                                 continue;
1314                         if (!r->flags || (r->flags & IORESOURCE_UNSET))
1315                                 continue;       /* Not assigned at all */
1316                         /* We only allocate ROMs on pass 1 just in case they
1317                          * have been screwed up by firmware
1318                          */
1319                         if (idx == PCI_ROM_RESOURCE)
1320                                 disabled = 1;
1321                         if (r->flags & IORESOURCE_IO)
1322                                 disabled = !(command & PCI_COMMAND_IO);
1323                         else
1324                                 disabled = !(command & PCI_COMMAND_MEMORY);
1325                         if (pass == disabled)
1326                                 alloc_resource(dev, idx);
1327                 }
1328                 if (pass)
1329                         continue;
1330                 r = &dev->resource[PCI_ROM_RESOURCE];
1331                 if (r->flags) {
1332                         /* Turn the ROM off, leave the resource region,
1333                          * but keep it unregistered.
1334                          */
1335                         u32 reg;
1336                         pci_read_config_dword(dev, dev->rom_base_reg, &reg);
1337                         if (reg & PCI_ROM_ADDRESS_ENABLE) {
1338                                 pr_debug("PCI: Switching off ROM of %s\n",
1339                                          pci_name(dev));
1340                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
1341                                 pci_write_config_dword(dev, dev->rom_base_reg,
1342                                                 reg & ~PCI_ROM_ADDRESS_ENABLE);
1343                         }
1344                 }
1345         }
1346 }
1347 
1348 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1349 {
1350         struct pci_controller *hose = pci_bus_to_host(bus);
1351         resource_size_t offset;
1352         struct resource *res, *pres;
1353         int i;
1354 
1355         pr_debug("Reserving legacy ranges for domain %04x\n",
1356                                                         pci_domain_nr(bus));
1357 
1358         /* Check for IO */
1359         if (!(hose->io_resource.flags & IORESOURCE_IO))
1360                 goto no_io;
1361         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1362         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1363         BUG_ON(res == NULL);
1364         res->name = "Legacy IO";
1365         res->flags = IORESOURCE_IO;
1366         res->start = offset;
1367         res->end = (offset + 0xfff) & 0xfffffffful;
1368         pr_debug("Candidate legacy IO: %pR\n", res);
1369         if (request_resource(&hose->io_resource, res)) {
1370                 printk(KERN_DEBUG
1371                        "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1372                        pci_domain_nr(bus), bus->number, res);
1373                 kfree(res);
1374         }
1375 
1376  no_io:
1377         /* Check for memory */
1378         offset = hose->pci_mem_offset;
1379         pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1380         for (i = 0; i < 3; i++) {
1381                 pres = &hose->mem_resources[i];
1382                 if (!(pres->flags & IORESOURCE_MEM))
1383                         continue;
1384                 pr_debug("hose mem res: %pR\n", pres);
1385                 if ((pres->start - offset) <= 0xa0000 &&
1386                     (pres->end - offset) >= 0xbffff)
1387                         break;
1388         }
1389         if (i >= 3)
1390                 return;
1391         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1392         BUG_ON(res == NULL);
1393         res->name = "Legacy VGA memory";
1394         res->flags = IORESOURCE_MEM;
1395         res->start = 0xa0000 + offset;
1396         res->end = 0xbffff + offset;
1397         pr_debug("Candidate VGA memory: %pR\n", res);
1398         if (request_resource(pres, res)) {
1399                 printk(KERN_DEBUG
1400                        "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1401                        pci_domain_nr(bus), bus->number, res);
1402                 kfree(res);
1403         }
1404 }
1405 
1406 void __init pcibios_resource_survey(void)
1407 {
1408         struct pci_bus *b;
1409 
1410         /* Allocate and assign resources. If we re-assign everything, then
1411          * we skip the allocate phase
1412          */
1413         list_for_each_entry(b, &pci_root_buses, node)
1414                 pcibios_allocate_bus_resources(b);
1415 
1416         if (!(pci_flags & PCI_REASSIGN_ALL_RSRC)) {
1417                 pcibios_allocate_resources(0);
1418                 pcibios_allocate_resources(1);
1419         }
1420 
1421         /* Before we start assigning unassigned resource, we try to reserve
1422          * the low IO area and the VGA memory area if they intersect the
1423          * bus available resources to avoid allocating things on top of them
1424          */
1425         if (!(pci_flags & PCI_PROBE_ONLY)) {
1426                 list_for_each_entry(b, &pci_root_buses, node)
1427                         pcibios_reserve_legacy_regions(b);
1428         }
1429 
1430         /* Now, if the platform didn't decide to blindly trust the firmware,
1431          * we proceed to assigning things that were left unassigned
1432          */
1433         if (!(pci_flags & PCI_PROBE_ONLY)) {
1434                 pr_debug("PCI: Assigning unassigned resources...\n");
1435                 pci_assign_unassigned_resources();
1436         }
1437 }
1438 
1439 #ifdef CONFIG_HOTPLUG
1440 
1441 /* This is used by the PCI hotplug driver to allocate resource
1442  * of newly plugged busses. We can try to consolidate with the
1443  * rest of the code later, for now, keep it as-is as our main
1444  * resource allocation function doesn't deal with sub-trees yet.
1445  */
1446 void __devinit pcibios_claim_one_bus(struct pci_bus *bus)
1447 {
1448         struct pci_dev *dev;
1449         struct pci_bus *child_bus;
1450 
1451         list_for_each_entry(dev, &bus->devices, bus_list) {
1452                 int i;
1453 
1454                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1455                         struct resource *r = &dev->resource[i];
1456 
1457                         if (r->parent || !r->start || !r->flags)
1458                                 continue;
1459 
1460                         pr_debug("PCI: Claiming %s: "
1461                                  "Resource %d: %016llx..%016llx [%x]\n",
1462                                  pci_name(dev), i,
1463                                  (unsigned long long)r->start,
1464                                  (unsigned long long)r->end,
1465                                  (unsigned int)r->flags);
1466 
1467                         pci_claim_resource(dev, i);
1468                 }
1469         }
1470 
1471         list_for_each_entry(child_bus, &bus->children, node)
1472                 pcibios_claim_one_bus(child_bus);
1473 }
1474 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1475 
1476 
1477 /* pcibios_finish_adding_to_bus
1478  *
1479  * This is to be called by the hotplug code after devices have been
1480  * added to a bus, this include calling it for a PHB that is just
1481  * being added
1482  */
1483 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1484 {
1485         pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1486                  pci_domain_nr(bus), bus->number);
1487 
1488         /* Allocate bus and devices resources */
1489         pcibios_allocate_bus_resources(bus);
1490         pcibios_claim_one_bus(bus);
1491 
1492         /* Add new devices to global lists.  Register in proc, sysfs. */
1493         pci_bus_add_devices(bus);
1494 
1495         /* Fixup EEH */
1496         /* eeh_add_device_tree_late(bus); */
1497 }
1498 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1499 
1500 #endif /* CONFIG_HOTPLUG */
1501 
1502 int pcibios_enable_device(struct pci_dev *dev, int mask)
1503 {
1504         return pci_enable_resources(dev, mask);
1505 }
1506 
1507 void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1508 {
1509         struct pci_bus *bus = hose->bus;
1510         struct resource *res;
1511         int i;
1512 
1513         /* Hookup PHB IO resource */
1514         bus->resource[0] = res = &hose->io_resource;
1515 
1516         if (!res->flags) {
1517                 printk(KERN_WARNING "PCI: I/O resource not set for host"
1518                        " bridge %s (domain %d)\n",
1519                        hose->dn->full_name, hose->global_number);
1520                 /* Workaround for lack of IO resource only on 32-bit */
1521                 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1522                 res->end = res->start + IO_SPACE_LIMIT;
1523                 res->flags = IORESOURCE_IO;
1524         }
1525 
1526         pr_debug("PCI: PHB IO resource    = %016llx-%016llx [%lx]\n",
1527                  (unsigned long long)res->start,
1528                  (unsigned long long)res->end,
1529                  (unsigned long)res->flags);
1530 
1531         /* Hookup PHB Memory resources */
1532         for (i = 0; i < 3; ++i) {
1533                 res = &hose->mem_resources[i];
1534                 if (!res->flags) {
1535                         if (i > 0)
1536                                 continue;
1537                         printk(KERN_ERR "PCI: Memory resource 0 not set for "
1538                                "host bridge %s (domain %d)\n",
1539                                hose->dn->full_name, hose->global_number);
1540 
1541                         /* Workaround for lack of MEM resource only on 32-bit */
1542                         res->start = hose->pci_mem_offset;
1543                         res->end = (resource_size_t)-1LL;
1544                         res->flags = IORESOURCE_MEM;
1545 
1546                 }
1547                 bus->resource[i+1] = res;
1548 
1549                 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1550                         i, (unsigned long long)res->start,
1551                         (unsigned long long)res->end,
1552                         (unsigned long)res->flags);
1553         }
1554 
1555         pr_debug("PCI: PHB MEM offset     = %016llx\n",
1556                  (unsigned long long)hose->pci_mem_offset);
1557         pr_debug("PCI: PHB IO  offset     = %08lx\n",
1558                  (unsigned long)hose->io_base_virt - _IO_BASE);
1559 }
1560 
1561 /*
1562  * Null PCI config access functions, for the case when we can't
1563  * find a hose.
1564  */
1565 #define NULL_PCI_OP(rw, size, type)                                     \
1566 static int                                                              \
1567 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)    \
1568 {                                                                       \
1569         return PCIBIOS_DEVICE_NOT_FOUND;                                \
1570 }
1571 
1572 static int
1573 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1574                  int len, u32 *val)
1575 {
1576         return PCIBIOS_DEVICE_NOT_FOUND;
1577 }
1578 
1579 static int
1580 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1581                   int len, u32 val)
1582 {
1583         return PCIBIOS_DEVICE_NOT_FOUND;
1584 }
1585 
1586 static struct pci_ops null_pci_ops = {
1587         .read = null_read_config,
1588         .write = null_write_config,
1589 };
1590 
1591 /*
1592  * These functions are used early on before PCI scanning is done
1593  * and all of the pci_dev and pci_bus structures have been created.
1594  */
1595 static struct pci_bus *
1596 fake_pci_bus(struct pci_controller *hose, int busnr)
1597 {
1598         static struct pci_bus bus;
1599 
1600         if (!hose)
1601                 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1602 
1603         bus.number = busnr;
1604         bus.sysdata = hose;
1605         bus.ops = hose ? hose->ops : &null_pci_ops;
1606         return &bus;
1607 }
1608 
1609 #define EARLY_PCI_OP(rw, size, type)                                    \
1610 int early_##rw##_config_##size(struct pci_controller *hose, int bus,    \
1611                                int devfn, int offset, type value)       \
1612 {                                                                       \
1613         return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),    \
1614                                             devfn, offset, value);      \
1615 }
1616 
1617 EARLY_PCI_OP(read, byte, u8 *)
1618 EARLY_PCI_OP(read, word, u16 *)
1619 EARLY_PCI_OP(read, dword, u32 *)
1620 EARLY_PCI_OP(write, byte, u8)
1621 EARLY_PCI_OP(write, word, u16)
1622 EARLY_PCI_OP(write, dword, u32)
1623 
1624 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1625                           int cap)
1626 {
1627         return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1628 }
1629 

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