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TOMOYO Linux Cross Reference
Linux/arch/microblaze/pci/pci-common.c

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  1 /*
  2  * Contains common pci routines for ALL ppc platform
  3  * (based on pci_32.c and pci_64.c)
  4  *
  5  * Port for PPC64 David Engebretsen, IBM Corp.
  6  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
  7  *
  8  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
  9  *   Rework, based on alpha PCI code.
 10  *
 11  * Common pmac/prep/chrp pci routines. -- Cort
 12  *
 13  * This program is free software; you can redistribute it and/or
 14  * modify it under the terms of the GNU General Public License
 15  * as published by the Free Software Foundation; either version
 16  * 2 of the License, or (at your option) any later version.
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/pci.h>
 21 #include <linux/string.h>
 22 #include <linux/init.h>
 23 #include <linux/bootmem.h>
 24 #include <linux/mm.h>
 25 #include <linux/list.h>
 26 #include <linux/syscalls.h>
 27 #include <linux/irq.h>
 28 #include <linux/vmalloc.h>
 29 #include <linux/slab.h>
 30 #include <linux/of.h>
 31 #include <linux/of_address.h>
 32 #include <linux/of_pci.h>
 33 #include <linux/export.h>
 34 
 35 #include <asm/processor.h>
 36 #include <asm/io.h>
 37 #include <asm/pci-bridge.h>
 38 #include <asm/byteorder.h>
 39 
 40 static DEFINE_SPINLOCK(hose_spinlock);
 41 LIST_HEAD(hose_list);
 42 
 43 /* XXX kill that some day ... */
 44 static int global_phb_number;           /* Global phb counter */
 45 
 46 /* ISA Memory physical address */
 47 resource_size_t isa_mem_base;
 48 
 49 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
 50 
 51 unsigned long isa_io_base;
 52 unsigned long pci_dram_offset;
 53 static int pci_bus_count;
 54 
 55 
 56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
 57 {
 58         pci_dma_ops = dma_ops;
 59 }
 60 
 61 struct dma_map_ops *get_pci_dma_ops(void)
 62 {
 63         return pci_dma_ops;
 64 }
 65 EXPORT_SYMBOL(get_pci_dma_ops);
 66 
 67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
 68 {
 69         struct pci_controller *phb;
 70 
 71         phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
 72         if (!phb)
 73                 return NULL;
 74         spin_lock(&hose_spinlock);
 75         phb->global_number = global_phb_number++;
 76         list_add_tail(&phb->list_node, &hose_list);
 77         spin_unlock(&hose_spinlock);
 78         phb->dn = dev;
 79         phb->is_dynamic = mem_init_done;
 80         return phb;
 81 }
 82 
 83 void pcibios_free_controller(struct pci_controller *phb)
 84 {
 85         spin_lock(&hose_spinlock);
 86         list_del(&phb->list_node);
 87         spin_unlock(&hose_spinlock);
 88 
 89         if (phb->is_dynamic)
 90                 kfree(phb);
 91 }
 92 
 93 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
 94 {
 95         return resource_size(&hose->io_resource);
 96 }
 97 
 98 int pcibios_vaddr_is_ioport(void __iomem *address)
 99 {
100         int ret = 0;
101         struct pci_controller *hose;
102         resource_size_t size;
103 
104         spin_lock(&hose_spinlock);
105         list_for_each_entry(hose, &hose_list, list_node) {
106                 size = pcibios_io_size(hose);
107                 if (address >= hose->io_base_virt &&
108                     address < (hose->io_base_virt + size)) {
109                         ret = 1;
110                         break;
111                 }
112         }
113         spin_unlock(&hose_spinlock);
114         return ret;
115 }
116 
117 unsigned long pci_address_to_pio(phys_addr_t address)
118 {
119         struct pci_controller *hose;
120         resource_size_t size;
121         unsigned long ret = ~0;
122 
123         spin_lock(&hose_spinlock);
124         list_for_each_entry(hose, &hose_list, list_node) {
125                 size = pcibios_io_size(hose);
126                 if (address >= hose->io_base_phys &&
127                     address < (hose->io_base_phys + size)) {
128                         unsigned long base =
129                                 (unsigned long)hose->io_base_virt - _IO_BASE;
130                         ret = base + (address - hose->io_base_phys);
131                         break;
132                 }
133         }
134         spin_unlock(&hose_spinlock);
135 
136         return ret;
137 }
138 EXPORT_SYMBOL_GPL(pci_address_to_pio);
139 
140 /*
141  * Return the domain number for this bus.
142  */
143 int pci_domain_nr(struct pci_bus *bus)
144 {
145         struct pci_controller *hose = pci_bus_to_host(bus);
146 
147         return hose->global_number;
148 }
149 EXPORT_SYMBOL(pci_domain_nr);
150 
151 /* This routine is meant to be used early during boot, when the
152  * PCI bus numbers have not yet been assigned, and you need to
153  * issue PCI config cycles to an OF device.
154  * It could also be used to "fix" RTAS config cycles if you want
155  * to set pci_assign_all_buses to 1 and still use RTAS for PCI
156  * config cycles.
157  */
158 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
159 {
160         while (node) {
161                 struct pci_controller *hose, *tmp;
162                 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
163                         if (hose->dn == node)
164                                 return hose;
165                 node = node->parent;
166         }
167         return NULL;
168 }
169 
170 static ssize_t pci_show_devspec(struct device *dev,
171                 struct device_attribute *attr, char *buf)
172 {
173         struct pci_dev *pdev;
174         struct device_node *np;
175 
176         pdev = to_pci_dev(dev);
177         np = pci_device_to_OF_node(pdev);
178         if (np == NULL || np->full_name == NULL)
179                 return 0;
180         return sprintf(buf, "%s", np->full_name);
181 }
182 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
183 
184 /* Add sysfs properties */
185 int pcibios_add_platform_entries(struct pci_dev *pdev)
186 {
187         return device_create_file(&pdev->dev, &dev_attr_devspec);
188 }
189 
190 void pcibios_set_master(struct pci_dev *dev)
191 {
192         /* No special bus mastering setup handling */
193 }
194 
195 /*
196  * Reads the interrupt pin to determine if interrupt is use by card.
197  * If the interrupt is used, then gets the interrupt line from the
198  * openfirmware and sets it in the pci_dev and pci_config line.
199  */
200 int pci_read_irq_line(struct pci_dev *pci_dev)
201 {
202         struct of_irq oirq;
203         unsigned int virq;
204 
205         /* The current device-tree that iSeries generates from the HV
206          * PCI informations doesn't contain proper interrupt routing,
207          * and all the fallback would do is print out crap, so we
208          * don't attempt to resolve the interrupts here at all, some
209          * iSeries specific fixup does it.
210          *
211          * In the long run, we will hopefully fix the generated device-tree
212          * instead.
213          */
214         pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
215 
216 #ifdef DEBUG
217         memset(&oirq, 0xff, sizeof(oirq));
218 #endif
219         /* Try to get a mapping from the device-tree */
220         if (of_irq_map_pci(pci_dev, &oirq)) {
221                 u8 line, pin;
222 
223                 /* If that fails, lets fallback to what is in the config
224                  * space and map that through the default controller. We
225                  * also set the type to level low since that's what PCI
226                  * interrupts are. If your platform does differently, then
227                  * either provide a proper interrupt tree or don't use this
228                  * function.
229                  */
230                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
231                         return -1;
232                 if (pin == 0)
233                         return -1;
234                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
235                     line == 0xff || line == 0) {
236                         return -1;
237                 }
238                 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
239                          line, pin);
240 
241                 virq = irq_create_mapping(NULL, line);
242                 if (virq)
243                         irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
244         } else {
245                 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
246                          oirq.size, oirq.specifier[0], oirq.specifier[1],
247                          of_node_full_name(oirq.controller));
248 
249                 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
250                                              oirq.size);
251         }
252         if (!virq) {
253                 pr_debug(" Failed to map !\n");
254                 return -1;
255         }
256 
257         pr_debug(" Mapped to linux irq %d\n", virq);
258 
259         pci_dev->irq = virq;
260 
261         return 0;
262 }
263 EXPORT_SYMBOL(pci_read_irq_line);
264 
265 /*
266  * Platform support for /proc/bus/pci/X/Y mmap()s,
267  * modelled on the sparc64 implementation by Dave Miller.
268  *  -- paulus.
269  */
270 
271 /*
272  * Adjust vm_pgoff of VMA such that it is the physical page offset
273  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
274  *
275  * Basically, the user finds the base address for his device which he wishes
276  * to mmap.  They read the 32-bit value from the config space base register,
277  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
278  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
279  *
280  * Returns negative error code on failure, zero on success.
281  */
282 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
283                                                resource_size_t *offset,
284                                                enum pci_mmap_state mmap_state)
285 {
286         struct pci_controller *hose = pci_bus_to_host(dev->bus);
287         unsigned long io_offset = 0;
288         int i, res_bit;
289 
290         if (hose == 0)
291                 return NULL;            /* should never happen */
292 
293         /* If memory, add on the PCI bridge address offset */
294         if (mmap_state == pci_mmap_mem) {
295 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
296                 *offset += hose->pci_mem_offset;
297 #endif
298                 res_bit = IORESOURCE_MEM;
299         } else {
300                 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
301                 *offset += io_offset;
302                 res_bit = IORESOURCE_IO;
303         }
304 
305         /*
306          * Check that the offset requested corresponds to one of the
307          * resources of the device.
308          */
309         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
310                 struct resource *rp = &dev->resource[i];
311                 int flags = rp->flags;
312 
313                 /* treat ROM as memory (should be already) */
314                 if (i == PCI_ROM_RESOURCE)
315                         flags |= IORESOURCE_MEM;
316 
317                 /* Active and same type? */
318                 if ((flags & res_bit) == 0)
319                         continue;
320 
321                 /* In the range of this resource? */
322                 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
323                         continue;
324 
325                 /* found it! construct the final physical address */
326                 if (mmap_state == pci_mmap_io)
327                         *offset += hose->io_base_phys - io_offset;
328                 return rp;
329         }
330 
331         return NULL;
332 }
333 
334 /*
335  * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
336  * device mapping.
337  */
338 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
339                                       pgprot_t protection,
340                                       enum pci_mmap_state mmap_state,
341                                       int write_combine)
342 {
343         pgprot_t prot = protection;
344 
345         /* Write combine is always 0 on non-memory space mappings. On
346          * memory space, if the user didn't pass 1, we check for a
347          * "prefetchable" resource. This is a bit hackish, but we use
348          * this to workaround the inability of /sysfs to provide a write
349          * combine bit
350          */
351         if (mmap_state != pci_mmap_mem)
352                 write_combine = 0;
353         else if (write_combine == 0) {
354                 if (rp->flags & IORESOURCE_PREFETCH)
355                         write_combine = 1;
356         }
357 
358         return pgprot_noncached(prot);
359 }
360 
361 /*
362  * This one is used by /dev/mem and fbdev who have no clue about the
363  * PCI device, it tries to find the PCI device first and calls the
364  * above routine
365  */
366 pgprot_t pci_phys_mem_access_prot(struct file *file,
367                                   unsigned long pfn,
368                                   unsigned long size,
369                                   pgprot_t prot)
370 {
371         struct pci_dev *pdev = NULL;
372         struct resource *found = NULL;
373         resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
374         int i;
375 
376         if (page_is_ram(pfn))
377                 return prot;
378 
379         prot = pgprot_noncached(prot);
380         for_each_pci_dev(pdev) {
381                 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
382                         struct resource *rp = &pdev->resource[i];
383                         int flags = rp->flags;
384 
385                         /* Active and same type? */
386                         if ((flags & IORESOURCE_MEM) == 0)
387                                 continue;
388                         /* In the range of this resource? */
389                         if (offset < (rp->start & PAGE_MASK) ||
390                             offset > rp->end)
391                                 continue;
392                         found = rp;
393                         break;
394                 }
395                 if (found)
396                         break;
397         }
398         if (found) {
399                 if (found->flags & IORESOURCE_PREFETCH)
400                         prot = pgprot_noncached_wc(prot);
401                 pci_dev_put(pdev);
402         }
403 
404         pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
405                  (unsigned long long)offset, pgprot_val(prot));
406 
407         return prot;
408 }
409 
410 /*
411  * Perform the actual remap of the pages for a PCI device mapping, as
412  * appropriate for this architecture.  The region in the process to map
413  * is described by vm_start and vm_end members of VMA, the base physical
414  * address is found in vm_pgoff.
415  * The pci device structure is provided so that architectures may make mapping
416  * decisions on a per-device or per-bus basis.
417  *
418  * Returns a negative error code on failure, zero on success.
419  */
420 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
421                         enum pci_mmap_state mmap_state, int write_combine)
422 {
423         resource_size_t offset =
424                 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
425         struct resource *rp;
426         int ret;
427 
428         rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
429         if (rp == NULL)
430                 return -EINVAL;
431 
432         vma->vm_pgoff = offset >> PAGE_SHIFT;
433         vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
434                                                   vma->vm_page_prot,
435                                                   mmap_state, write_combine);
436 
437         ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
438                                vma->vm_end - vma->vm_start, vma->vm_page_prot);
439 
440         return ret;
441 }
442 
443 /* This provides legacy IO read access on a bus */
444 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
445 {
446         unsigned long offset;
447         struct pci_controller *hose = pci_bus_to_host(bus);
448         struct resource *rp = &hose->io_resource;
449         void __iomem *addr;
450 
451         /* Check if port can be supported by that bus. We only check
452          * the ranges of the PHB though, not the bus itself as the rules
453          * for forwarding legacy cycles down bridges are not our problem
454          * here. So if the host bridge supports it, we do it.
455          */
456         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
457         offset += port;
458 
459         if (!(rp->flags & IORESOURCE_IO))
460                 return -ENXIO;
461         if (offset < rp->start || (offset + size) > rp->end)
462                 return -ENXIO;
463         addr = hose->io_base_virt + port;
464 
465         switch (size) {
466         case 1:
467                 *((u8 *)val) = in_8(addr);
468                 return 1;
469         case 2:
470                 if (port & 1)
471                         return -EINVAL;
472                 *((u16 *)val) = in_le16(addr);
473                 return 2;
474         case 4:
475                 if (port & 3)
476                         return -EINVAL;
477                 *((u32 *)val) = in_le32(addr);
478                 return 4;
479         }
480         return -EINVAL;
481 }
482 
483 /* This provides legacy IO write access on a bus */
484 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
485 {
486         unsigned long offset;
487         struct pci_controller *hose = pci_bus_to_host(bus);
488         struct resource *rp = &hose->io_resource;
489         void __iomem *addr;
490 
491         /* Check if port can be supported by that bus. We only check
492          * the ranges of the PHB though, not the bus itself as the rules
493          * for forwarding legacy cycles down bridges are not our problem
494          * here. So if the host bridge supports it, we do it.
495          */
496         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
497         offset += port;
498 
499         if (!(rp->flags & IORESOURCE_IO))
500                 return -ENXIO;
501         if (offset < rp->start || (offset + size) > rp->end)
502                 return -ENXIO;
503         addr = hose->io_base_virt + port;
504 
505         /* WARNING: The generic code is idiotic. It gets passed a pointer
506          * to what can be a 1, 2 or 4 byte quantity and always reads that
507          * as a u32, which means that we have to correct the location of
508          * the data read within those 32 bits for size 1 and 2
509          */
510         switch (size) {
511         case 1:
512                 out_8(addr, val >> 24);
513                 return 1;
514         case 2:
515                 if (port & 1)
516                         return -EINVAL;
517                 out_le16(addr, val >> 16);
518                 return 2;
519         case 4:
520                 if (port & 3)
521                         return -EINVAL;
522                 out_le32(addr, val);
523                 return 4;
524         }
525         return -EINVAL;
526 }
527 
528 /* This provides legacy IO or memory mmap access on a bus */
529 int pci_mmap_legacy_page_range(struct pci_bus *bus,
530                                struct vm_area_struct *vma,
531                                enum pci_mmap_state mmap_state)
532 {
533         struct pci_controller *hose = pci_bus_to_host(bus);
534         resource_size_t offset =
535                 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
536         resource_size_t size = vma->vm_end - vma->vm_start;
537         struct resource *rp;
538 
539         pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
540                  pci_domain_nr(bus), bus->number,
541                  mmap_state == pci_mmap_mem ? "MEM" : "IO",
542                  (unsigned long long)offset,
543                  (unsigned long long)(offset + size - 1));
544 
545         if (mmap_state == pci_mmap_mem) {
546                 /* Hack alert !
547                  *
548                  * Because X is lame and can fail starting if it gets an error
549                  * trying to mmap legacy_mem (instead of just moving on without
550                  * legacy memory access) we fake it here by giving it anonymous
551                  * memory, effectively behaving just like /dev/zero
552                  */
553                 if ((offset + size) > hose->isa_mem_size) {
554 #ifdef CONFIG_MMU
555                         printk(KERN_DEBUG
556                                 "Process %s (pid:%d) mapped non-existing PCI"
557                                 "legacy memory for 0%04x:%02x\n",
558                                 current->comm, current->pid, pci_domain_nr(bus),
559                                                                 bus->number);
560 #endif
561                         if (vma->vm_flags & VM_SHARED)
562                                 return shmem_zero_setup(vma);
563                         return 0;
564                 }
565                 offset += hose->isa_mem_phys;
566         } else {
567                 unsigned long io_offset = (unsigned long)hose->io_base_virt - \
568                                                                 _IO_BASE;
569                 unsigned long roffset = offset + io_offset;
570                 rp = &hose->io_resource;
571                 if (!(rp->flags & IORESOURCE_IO))
572                         return -ENXIO;
573                 if (roffset < rp->start || (roffset + size) > rp->end)
574                         return -ENXIO;
575                 offset += hose->io_base_phys;
576         }
577         pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
578 
579         vma->vm_pgoff = offset >> PAGE_SHIFT;
580         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
581         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
582                                vma->vm_end - vma->vm_start,
583                                vma->vm_page_prot);
584 }
585 
586 void pci_resource_to_user(const struct pci_dev *dev, int bar,
587                           const struct resource *rsrc,
588                           resource_size_t *start, resource_size_t *end)
589 {
590         struct pci_controller *hose = pci_bus_to_host(dev->bus);
591         resource_size_t offset = 0;
592 
593         if (hose == NULL)
594                 return;
595 
596         if (rsrc->flags & IORESOURCE_IO)
597                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
598 
599         /* We pass a fully fixed up address to userland for MMIO instead of
600          * a BAR value because X is lame and expects to be able to use that
601          * to pass to /dev/mem !
602          *
603          * That means that we'll have potentially 64 bits values where some
604          * userland apps only expect 32 (like X itself since it thinks only
605          * Sparc has 64 bits MMIO) but if we don't do that, we break it on
606          * 32 bits CHRPs :-(
607          *
608          * Hopefully, the sysfs insterface is immune to that gunk. Once X
609          * has been fixed (and the fix spread enough), we can re-enable the
610          * 2 lines below and pass down a BAR value to userland. In that case
611          * we'll also have to re-enable the matching code in
612          * __pci_mmap_make_offset().
613          *
614          * BenH.
615          */
616 #if 0
617         else if (rsrc->flags & IORESOURCE_MEM)
618                 offset = hose->pci_mem_offset;
619 #endif
620 
621         *start = rsrc->start - offset;
622         *end = rsrc->end - offset;
623 }
624 
625 /**
626  * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
627  * @hose: newly allocated pci_controller to be setup
628  * @dev: device node of the host bridge
629  * @primary: set if primary bus (32 bits only, soon to be deprecated)
630  *
631  * This function will parse the "ranges" property of a PCI host bridge device
632  * node and setup the resource mapping of a pci controller based on its
633  * content.
634  *
635  * Life would be boring if it wasn't for a few issues that we have to deal
636  * with here:
637  *
638  *   - We can only cope with one IO space range and up to 3 Memory space
639  *     ranges. However, some machines (thanks Apple !) tend to split their
640  *     space into lots of small contiguous ranges. So we have to coalesce.
641  *
642  *   - We can only cope with all memory ranges having the same offset
643  *     between CPU addresses and PCI addresses. Unfortunately, some bridges
644  *     are setup for a large 1:1 mapping along with a small "window" which
645  *     maps PCI address 0 to some arbitrary high address of the CPU space in
646  *     order to give access to the ISA memory hole.
647  *     The way out of here that I've chosen for now is to always set the
648  *     offset based on the first resource found, then override it if we
649  *     have a different offset and the previous was set by an ISA hole.
650  *
651  *   - Some busses have IO space not starting at 0, which causes trouble with
652  *     the way we do our IO resource renumbering. The code somewhat deals with
653  *     it for 64 bits but I would expect problems on 32 bits.
654  *
655  *   - Some 32 bits platforms such as 4xx can have physical space larger than
656  *     32 bits so we need to use 64 bits values for the parsing
657  */
658 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
659                                             struct device_node *dev,
660                                             int primary)
661 {
662         const u32 *ranges;
663         int rlen;
664         int pna = of_n_addr_cells(dev);
665         int np = pna + 5;
666         int memno = 0, isa_hole = -1;
667         u32 pci_space;
668         unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
669         unsigned long long isa_mb = 0;
670         struct resource *res;
671 
672         printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
673                dev->full_name, primary ? "(primary)" : "");
674 
675         /* Get ranges property */
676         ranges = of_get_property(dev, "ranges", &rlen);
677         if (ranges == NULL)
678                 return;
679 
680         /* Parse it */
681         pr_debug("Parsing ranges property...\n");
682         while ((rlen -= np * 4) >= 0) {
683                 /* Read next ranges element */
684                 pci_space = ranges[0];
685                 pci_addr = of_read_number(ranges + 1, 2);
686                 cpu_addr = of_translate_address(dev, ranges + 3);
687                 size = of_read_number(ranges + pna + 3, 2);
688 
689                 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx "
690                                 "cpu_addr:0x%016llx size:0x%016llx\n",
691                                         pci_space, pci_addr, cpu_addr, size);
692 
693                 ranges += np;
694 
695                 /* If we failed translation or got a zero-sized region
696                  * (some FW try to feed us with non sensical zero sized regions
697                  * such as power3 which look like some kind of attempt
698                  * at exposing the VGA memory hole)
699                  */
700                 if (cpu_addr == OF_BAD_ADDR || size == 0)
701                         continue;
702 
703                 /* Now consume following elements while they are contiguous */
704                 for (; rlen >= np * sizeof(u32);
705                      ranges += np, rlen -= np * 4) {
706                         if (ranges[0] != pci_space)
707                                 break;
708                         pci_next = of_read_number(ranges + 1, 2);
709                         cpu_next = of_translate_address(dev, ranges + 3);
710                         if (pci_next != pci_addr + size ||
711                             cpu_next != cpu_addr + size)
712                                 break;
713                         size += of_read_number(ranges + pna + 3, 2);
714                 }
715 
716                 /* Act based on address space type */
717                 res = NULL;
718                 switch ((pci_space >> 24) & 0x3) {
719                 case 1:         /* PCI IO space */
720                         printk(KERN_INFO
721                                "  IO 0x%016llx..0x%016llx -> 0x%016llx\n",
722                                cpu_addr, cpu_addr + size - 1, pci_addr);
723 
724                         /* We support only one IO range */
725                         if (hose->pci_io_size) {
726                                 printk(KERN_INFO
727                                        " \\--> Skipped (too many) !\n");
728                                 continue;
729                         }
730                         /* On 32 bits, limit I/O space to 16MB */
731                         if (size > 0x01000000)
732                                 size = 0x01000000;
733 
734                         /* 32 bits needs to map IOs here */
735                         hose->io_base_virt = ioremap(cpu_addr, size);
736 
737                         /* Expect trouble if pci_addr is not 0 */
738                         if (primary)
739                                 isa_io_base =
740                                         (unsigned long)hose->io_base_virt;
741                         /* pci_io_size and io_base_phys always represent IO
742                          * space starting at 0 so we factor in pci_addr
743                          */
744                         hose->pci_io_size = pci_addr + size;
745                         hose->io_base_phys = cpu_addr - pci_addr;
746 
747                         /* Build resource */
748                         res = &hose->io_resource;
749                         res->flags = IORESOURCE_IO;
750                         res->start = pci_addr;
751                         break;
752                 case 2:         /* PCI Memory space */
753                 case 3:         /* PCI 64 bits Memory space */
754                         printk(KERN_INFO
755                                " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
756                                cpu_addr, cpu_addr + size - 1, pci_addr,
757                                (pci_space & 0x40000000) ? "Prefetch" : "");
758 
759                         /* We support only 3 memory ranges */
760                         if (memno >= 3) {
761                                 printk(KERN_INFO
762                                        " \\--> Skipped (too many) !\n");
763                                 continue;
764                         }
765                         /* Handles ISA memory hole space here */
766                         if (pci_addr == 0) {
767                                 isa_mb = cpu_addr;
768                                 isa_hole = memno;
769                                 if (primary || isa_mem_base == 0)
770                                         isa_mem_base = cpu_addr;
771                                 hose->isa_mem_phys = cpu_addr;
772                                 hose->isa_mem_size = size;
773                         }
774 
775                         /* We get the PCI/Mem offset from the first range or
776                          * the, current one if the offset came from an ISA
777                          * hole. If they don't match, bugger.
778                          */
779                         if (memno == 0 ||
780                             (isa_hole >= 0 && pci_addr != 0 &&
781                              hose->pci_mem_offset == isa_mb))
782                                 hose->pci_mem_offset = cpu_addr - pci_addr;
783                         else if (pci_addr != 0 &&
784                                  hose->pci_mem_offset != cpu_addr - pci_addr) {
785                                 printk(KERN_INFO
786                                        " \\--> Skipped (offset mismatch) !\n");
787                                 continue;
788                         }
789 
790                         /* Build resource */
791                         res = &hose->mem_resources[memno++];
792                         res->flags = IORESOURCE_MEM;
793                         if (pci_space & 0x40000000)
794                                 res->flags |= IORESOURCE_PREFETCH;
795                         res->start = cpu_addr;
796                         break;
797                 }
798                 if (res != NULL) {
799                         res->name = dev->full_name;
800                         res->end = res->start + size - 1;
801                         res->parent = NULL;
802                         res->sibling = NULL;
803                         res->child = NULL;
804                 }
805         }
806 
807         /* If there's an ISA hole and the pci_mem_offset is -not- matching
808          * the ISA hole offset, then we need to remove the ISA hole from
809          * the resource list for that brige
810          */
811         if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
812                 unsigned int next = isa_hole + 1;
813                 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
814                 if (next < memno)
815                         memmove(&hose->mem_resources[isa_hole],
816                                 &hose->mem_resources[next],
817                                 sizeof(struct resource) * (memno - next));
818                 hose->mem_resources[--memno].flags = 0;
819         }
820 }
821 
822 /* Decide whether to display the domain number in /proc */
823 int pci_proc_domain(struct pci_bus *bus)
824 {
825         struct pci_controller *hose = pci_bus_to_host(bus);
826 
827         return 0;
828 }
829 
830 /* This header fixup will do the resource fixup for all devices as they are
831  * probed, but not for bridge ranges
832  */
833 static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
834 {
835         struct pci_controller *hose = pci_bus_to_host(dev->bus);
836         int i;
837 
838         if (!hose) {
839                 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
840                        pci_name(dev));
841                 return;
842         }
843         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
844                 struct resource *res = dev->resource + i;
845                 if (!res->flags)
846                         continue;
847                 if (res->start == 0) {
848                         pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
849                                                         "is unassigned\n",
850                                  pci_name(dev), i,
851                                  (unsigned long long)res->start,
852                                  (unsigned long long)res->end,
853                                  (unsigned int)res->flags);
854                         res->end -= res->start;
855                         res->start = 0;
856                         res->flags |= IORESOURCE_UNSET;
857                         continue;
858                 }
859 
860                 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
861                          pci_name(dev), i,
862                          (unsigned long long)res->start,\
863                          (unsigned long long)res->end,
864                          (unsigned int)res->flags);
865         }
866 }
867 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
868 
869 /* This function tries to figure out if a bridge resource has been initialized
870  * by the firmware or not. It doesn't have to be absolutely bullet proof, but
871  * things go more smoothly when it gets it right. It should covers cases such
872  * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
873  */
874 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
875                                                            struct resource *res)
876 {
877         struct pci_controller *hose = pci_bus_to_host(bus);
878         struct pci_dev *dev = bus->self;
879         resource_size_t offset;
880         u16 command;
881         int i;
882 
883         /* Job is a bit different between memory and IO */
884         if (res->flags & IORESOURCE_MEM) {
885                 /* If the BAR is non-0 (res != pci_mem_offset) then it's
886                  * probably been initialized by somebody
887                  */
888                 if (res->start != hose->pci_mem_offset)
889                         return 0;
890 
891                 /* The BAR is 0, let's check if memory decoding is enabled on
892                  * the bridge. If not, we consider it unassigned
893                  */
894                 pci_read_config_word(dev, PCI_COMMAND, &command);
895                 if ((command & PCI_COMMAND_MEMORY) == 0)
896                         return 1;
897 
898                 /* Memory decoding is enabled and the BAR is 0. If any of
899                  * the bridge resources covers that starting address (0 then
900                  * it's good enough for us for memory
901                  */
902                 for (i = 0; i < 3; i++) {
903                         if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
904                            hose->mem_resources[i].start == hose->pci_mem_offset)
905                                 return 0;
906                 }
907 
908                 /* Well, it starts at 0 and we know it will collide so we may as
909                  * well consider it as unassigned. That covers the Apple case.
910                  */
911                 return 1;
912         } else {
913                 /* If the BAR is non-0, then we consider it assigned */
914                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
915                 if (((res->start - offset) & 0xfffffffful) != 0)
916                         return 0;
917 
918                 /* Here, we are a bit different than memory as typically IO
919                  * space starting at low addresses -is- valid. What we do
920                  * instead if that we consider as unassigned anything that
921                  * doesn't have IO enabled in the PCI command register,
922                  * and that's it.
923                  */
924                 pci_read_config_word(dev, PCI_COMMAND, &command);
925                 if (command & PCI_COMMAND_IO)
926                         return 0;
927 
928                 /* It's starting at 0 and IO is disabled in the bridge, consider
929                  * it unassigned
930                  */
931                 return 1;
932         }
933 }
934 
935 /* Fixup resources of a PCI<->PCI bridge */
936 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
937 {
938         struct resource *res;
939         int i;
940 
941         struct pci_dev *dev = bus->self;
942 
943         pci_bus_for_each_resource(bus, res, i) {
944                 if (!res)
945                         continue;
946                 if (!res->flags)
947                         continue;
948                 if (i >= 3 && bus->self->transparent)
949                         continue;
950 
951                 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
952                          pci_name(dev), i,
953                          (unsigned long long)res->start,\
954                          (unsigned long long)res->end,
955                          (unsigned int)res->flags);
956 
957                 /* Try to detect uninitialized P2P bridge resources,
958                  * and clear them out so they get re-assigned later
959                  */
960                 if (pcibios_uninitialized_bridge_resource(bus, res)) {
961                         res->flags = 0;
962                         pr_debug("PCI:%s            (unassigned)\n",
963                                                                 pci_name(dev));
964                 } else {
965                         pr_debug("PCI:%s            %016llx-%016llx\n",
966                                  pci_name(dev),
967                                  (unsigned long long)res->start,
968                                  (unsigned long long)res->end);
969                 }
970         }
971 }
972 
973 void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
974 {
975         /* Fix up the bus resources for P2P bridges */
976         if (bus->self != NULL)
977                 pcibios_fixup_bridge(bus);
978 }
979 
980 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
981 {
982         struct pci_dev *dev;
983 
984         pr_debug("PCI: Fixup bus devices %d (%s)\n",
985                  bus->number, bus->self ? pci_name(bus->self) : "PHB");
986 
987         list_for_each_entry(dev, &bus->devices, bus_list) {
988                 /* Setup OF node pointer in archdata */
989                 dev->dev.of_node = pci_device_to_OF_node(dev);
990 
991                 /* Fixup NUMA node as it may not be setup yet by the generic
992                  * code and is needed by the DMA init
993                  */
994                 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
995 
996                 /* Hook up default DMA ops */
997                 set_dma_ops(&dev->dev, pci_dma_ops);
998                 dev->dev.archdata.dma_data = (void *)PCI_DRAM_OFFSET;
999 
1000                 /* Read default IRQs and fixup if necessary */
1001                 pci_read_irq_line(dev);
1002         }
1003 }
1004 
1005 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1006 {
1007         /* When called from the generic PCI probe, read PCI<->PCI bridge
1008          * bases. This is -not- called when generating the PCI tree from
1009          * the OF device-tree.
1010          */
1011         if (bus->self != NULL)
1012                 pci_read_bridge_bases(bus);
1013 
1014         /* Now fixup the bus bus */
1015         pcibios_setup_bus_self(bus);
1016 
1017         /* Now fixup devices on that bus */
1018         pcibios_setup_bus_devices(bus);
1019 }
1020 EXPORT_SYMBOL(pcibios_fixup_bus);
1021 
1022 static int skip_isa_ioresource_align(struct pci_dev *dev)
1023 {
1024         return 0;
1025 }
1026 
1027 /*
1028  * We need to avoid collisions with `mirrored' VGA ports
1029  * and other strange ISA hardware, so we always want the
1030  * addresses to be allocated in the 0x000-0x0ff region
1031  * modulo 0x400.
1032  *
1033  * Why? Because some silly external IO cards only decode
1034  * the low 10 bits of the IO address. The 0x00-0xff region
1035  * is reserved for motherboard devices that decode all 16
1036  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1037  * but we want to try to avoid allocating at 0x2900-0x2bff
1038  * which might have be mirrored at 0x0100-0x03ff..
1039  */
1040 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1041                                 resource_size_t size, resource_size_t align)
1042 {
1043         struct pci_dev *dev = data;
1044         resource_size_t start = res->start;
1045 
1046         if (res->flags & IORESOURCE_IO) {
1047                 if (skip_isa_ioresource_align(dev))
1048                         return start;
1049                 if (start & 0x300)
1050                         start = (start + 0x3ff) & ~0x3ff;
1051         }
1052 
1053         return start;
1054 }
1055 EXPORT_SYMBOL(pcibios_align_resource);
1056 
1057 /*
1058  * Reparent resource children of pr that conflict with res
1059  * under res, and make res replace those children.
1060  */
1061 static int __init reparent_resources(struct resource *parent,
1062                                      struct resource *res)
1063 {
1064         struct resource *p, **pp;
1065         struct resource **firstpp = NULL;
1066 
1067         for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1068                 if (p->end < res->start)
1069                         continue;
1070                 if (res->end < p->start)
1071                         break;
1072                 if (p->start < res->start || p->end > res->end)
1073                         return -1;      /* not completely contained */
1074                 if (firstpp == NULL)
1075                         firstpp = pp;
1076         }
1077         if (firstpp == NULL)
1078                 return -1;      /* didn't find any conflicting entries? */
1079         res->parent = parent;
1080         res->child = *firstpp;
1081         res->sibling = *pp;
1082         *firstpp = res;
1083         *pp = NULL;
1084         for (p = res->child; p != NULL; p = p->sibling) {
1085                 p->parent = res;
1086                 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1087                          p->name,
1088                          (unsigned long long)p->start,
1089                          (unsigned long long)p->end, res->name);
1090         }
1091         return 0;
1092 }
1093 
1094 /*
1095  *  Handle resources of PCI devices.  If the world were perfect, we could
1096  *  just allocate all the resource regions and do nothing more.  It isn't.
1097  *  On the other hand, we cannot just re-allocate all devices, as it would
1098  *  require us to know lots of host bridge internals.  So we attempt to
1099  *  keep as much of the original configuration as possible, but tweak it
1100  *  when it's found to be wrong.
1101  *
1102  *  Known BIOS problems we have to work around:
1103  *      - I/O or memory regions not configured
1104  *      - regions configured, but not enabled in the command register
1105  *      - bogus I/O addresses above 64K used
1106  *      - expansion ROMs left enabled (this may sound harmless, but given
1107  *        the fact the PCI specs explicitly allow address decoders to be
1108  *        shared between expansion ROMs and other resource regions, it's
1109  *        at least dangerous)
1110  *
1111  *  Our solution:
1112  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1113  *          This gives us fixed barriers on where we can allocate.
1114  *      (2) Allocate resources for all enabled devices.  If there is
1115  *          a collision, just mark the resource as unallocated. Also
1116  *          disable expansion ROMs during this step.
1117  *      (3) Try to allocate resources for disabled devices.  If the
1118  *          resources were assigned correctly, everything goes well,
1119  *          if they weren't, they won't disturb allocation of other
1120  *          resources.
1121  *      (4) Assign new addresses to resources which were either
1122  *          not configured at all or misconfigured.  If explicitly
1123  *          requested by the user, configure expansion ROM address
1124  *          as well.
1125  */
1126 
1127 void pcibios_allocate_bus_resources(struct pci_bus *bus)
1128 {
1129         struct pci_bus *b;
1130         int i;
1131         struct resource *res, *pr;
1132 
1133         pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1134                  pci_domain_nr(bus), bus->number);
1135 
1136         pci_bus_for_each_resource(bus, res, i) {
1137                 if (!res || !res->flags
1138                     || res->start > res->end || res->parent)
1139                         continue;
1140                 if (bus->parent == NULL)
1141                         pr = (res->flags & IORESOURCE_IO) ?
1142                                 &ioport_resource : &iomem_resource;
1143                 else {
1144                         /* Don't bother with non-root busses when
1145                          * re-assigning all resources. We clear the
1146                          * resource flags as if they were colliding
1147                          * and as such ensure proper re-allocation
1148                          * later.
1149                          */
1150                         pr = pci_find_parent_resource(bus->self, res);
1151                         if (pr == res) {
1152                                 /* this happens when the generic PCI
1153                                  * code (wrongly) decides that this
1154                                  * bridge is transparent  -- paulus
1155                                  */
1156                                 continue;
1157                         }
1158                 }
1159 
1160                 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1161                          "[0x%x], parent %p (%s)\n",
1162                          bus->self ? pci_name(bus->self) : "PHB",
1163                          bus->number, i,
1164                          (unsigned long long)res->start,
1165                          (unsigned long long)res->end,
1166                          (unsigned int)res->flags,
1167                          pr, (pr && pr->name) ? pr->name : "nil");
1168 
1169                 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1170                         if (request_resource(pr, res) == 0)
1171                                 continue;
1172                         /*
1173                          * Must be a conflict with an existing entry.
1174                          * Move that entry (or entries) under the
1175                          * bridge resource and try again.
1176                          */
1177                         if (reparent_resources(pr, res) == 0)
1178                                 continue;
1179                 }
1180                 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1181                        "%d of PCI bridge %d, will remap\n", i, bus->number);
1182 clear_resource:
1183                 res->start = res->end = 0;
1184                 res->flags = 0;
1185         }
1186 
1187         list_for_each_entry(b, &bus->children, node)
1188                 pcibios_allocate_bus_resources(b);
1189 }
1190 
1191 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1192 {
1193         struct resource *pr, *r = &dev->resource[idx];
1194 
1195         pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1196                  pci_name(dev), idx,
1197                  (unsigned long long)r->start,
1198                  (unsigned long long)r->end,
1199                  (unsigned int)r->flags);
1200 
1201         pr = pci_find_parent_resource(dev, r);
1202         if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1203             request_resource(pr, r) < 0) {
1204                 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1205                        " of device %s, will remap\n", idx, pci_name(dev));
1206                 if (pr)
1207                         pr_debug("PCI:  parent is %p: %016llx-%016llx [%x]\n",
1208                                  pr,
1209                                  (unsigned long long)pr->start,
1210                                  (unsigned long long)pr->end,
1211                                  (unsigned int)pr->flags);
1212                 /* We'll assign a new address later */
1213                 r->flags |= IORESOURCE_UNSET;
1214                 r->end -= r->start;
1215                 r->start = 0;
1216         }
1217 }
1218 
1219 static void __init pcibios_allocate_resources(int pass)
1220 {
1221         struct pci_dev *dev = NULL;
1222         int idx, disabled;
1223         u16 command;
1224         struct resource *r;
1225 
1226         for_each_pci_dev(dev) {
1227                 pci_read_config_word(dev, PCI_COMMAND, &command);
1228                 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1229                         r = &dev->resource[idx];
1230                         if (r->parent)          /* Already allocated */
1231                                 continue;
1232                         if (!r->flags || (r->flags & IORESOURCE_UNSET))
1233                                 continue;       /* Not assigned at all */
1234                         /* We only allocate ROMs on pass 1 just in case they
1235                          * have been screwed up by firmware
1236                          */
1237                         if (idx == PCI_ROM_RESOURCE)
1238                                 disabled = 1;
1239                         if (r->flags & IORESOURCE_IO)
1240                                 disabled = !(command & PCI_COMMAND_IO);
1241                         else
1242                                 disabled = !(command & PCI_COMMAND_MEMORY);
1243                         if (pass == disabled)
1244                                 alloc_resource(dev, idx);
1245                 }
1246                 if (pass)
1247                         continue;
1248                 r = &dev->resource[PCI_ROM_RESOURCE];
1249                 if (r->flags) {
1250                         /* Turn the ROM off, leave the resource region,
1251                          * but keep it unregistered.
1252                          */
1253                         u32 reg;
1254                         pci_read_config_dword(dev, dev->rom_base_reg, &reg);
1255                         if (reg & PCI_ROM_ADDRESS_ENABLE) {
1256                                 pr_debug("PCI: Switching off ROM of %s\n",
1257                                          pci_name(dev));
1258                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
1259                                 pci_write_config_dword(dev, dev->rom_base_reg,
1260                                                 reg & ~PCI_ROM_ADDRESS_ENABLE);
1261                         }
1262                 }
1263         }
1264 }
1265 
1266 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1267 {
1268         struct pci_controller *hose = pci_bus_to_host(bus);
1269         resource_size_t offset;
1270         struct resource *res, *pres;
1271         int i;
1272 
1273         pr_debug("Reserving legacy ranges for domain %04x\n",
1274                                                         pci_domain_nr(bus));
1275 
1276         /* Check for IO */
1277         if (!(hose->io_resource.flags & IORESOURCE_IO))
1278                 goto no_io;
1279         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1280         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1281         BUG_ON(res == NULL);
1282         res->name = "Legacy IO";
1283         res->flags = IORESOURCE_IO;
1284         res->start = offset;
1285         res->end = (offset + 0xfff) & 0xfffffffful;
1286         pr_debug("Candidate legacy IO: %pR\n", res);
1287         if (request_resource(&hose->io_resource, res)) {
1288                 printk(KERN_DEBUG
1289                        "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1290                        pci_domain_nr(bus), bus->number, res);
1291                 kfree(res);
1292         }
1293 
1294  no_io:
1295         /* Check for memory */
1296         offset = hose->pci_mem_offset;
1297         pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1298         for (i = 0; i < 3; i++) {
1299                 pres = &hose->mem_resources[i];
1300                 if (!(pres->flags & IORESOURCE_MEM))
1301                         continue;
1302                 pr_debug("hose mem res: %pR\n", pres);
1303                 if ((pres->start - offset) <= 0xa0000 &&
1304                     (pres->end - offset) >= 0xbffff)
1305                         break;
1306         }
1307         if (i >= 3)
1308                 return;
1309         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1310         BUG_ON(res == NULL);
1311         res->name = "Legacy VGA memory";
1312         res->flags = IORESOURCE_MEM;
1313         res->start = 0xa0000 + offset;
1314         res->end = 0xbffff + offset;
1315         pr_debug("Candidate VGA memory: %pR\n", res);
1316         if (request_resource(pres, res)) {
1317                 printk(KERN_DEBUG
1318                        "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1319                        pci_domain_nr(bus), bus->number, res);
1320                 kfree(res);
1321         }
1322 }
1323 
1324 void __init pcibios_resource_survey(void)
1325 {
1326         struct pci_bus *b;
1327 
1328         /* Allocate and assign resources. If we re-assign everything, then
1329          * we skip the allocate phase
1330          */
1331         list_for_each_entry(b, &pci_root_buses, node)
1332                 pcibios_allocate_bus_resources(b);
1333 
1334         pcibios_allocate_resources(0);
1335         pcibios_allocate_resources(1);
1336 
1337         /* Before we start assigning unassigned resource, we try to reserve
1338          * the low IO area and the VGA memory area if they intersect the
1339          * bus available resources to avoid allocating things on top of them
1340          */
1341         list_for_each_entry(b, &pci_root_buses, node)
1342                 pcibios_reserve_legacy_regions(b);
1343 
1344         /* Now proceed to assigning things that were left unassigned */
1345         pr_debug("PCI: Assigning unassigned resources...\n");
1346         pci_assign_unassigned_resources();
1347 }
1348 
1349 #ifdef CONFIG_HOTPLUG
1350 
1351 /* This is used by the PCI hotplug driver to allocate resource
1352  * of newly plugged busses. We can try to consolidate with the
1353  * rest of the code later, for now, keep it as-is as our main
1354  * resource allocation function doesn't deal with sub-trees yet.
1355  */
1356 void __devinit pcibios_claim_one_bus(struct pci_bus *bus)
1357 {
1358         struct pci_dev *dev;
1359         struct pci_bus *child_bus;
1360 
1361         list_for_each_entry(dev, &bus->devices, bus_list) {
1362                 int i;
1363 
1364                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1365                         struct resource *r = &dev->resource[i];
1366 
1367                         if (r->parent || !r->start || !r->flags)
1368                                 continue;
1369 
1370                         pr_debug("PCI: Claiming %s: "
1371                                  "Resource %d: %016llx..%016llx [%x]\n",
1372                                  pci_name(dev), i,
1373                                  (unsigned long long)r->start,
1374                                  (unsigned long long)r->end,
1375                                  (unsigned int)r->flags);
1376 
1377                         pci_claim_resource(dev, i);
1378                 }
1379         }
1380 
1381         list_for_each_entry(child_bus, &bus->children, node)
1382                 pcibios_claim_one_bus(child_bus);
1383 }
1384 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1385 
1386 
1387 /* pcibios_finish_adding_to_bus
1388  *
1389  * This is to be called by the hotplug code after devices have been
1390  * added to a bus, this include calling it for a PHB that is just
1391  * being added
1392  */
1393 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1394 {
1395         pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1396                  pci_domain_nr(bus), bus->number);
1397 
1398         /* Allocate bus and devices resources */
1399         pcibios_allocate_bus_resources(bus);
1400         pcibios_claim_one_bus(bus);
1401 
1402         /* Add new devices to global lists.  Register in proc, sysfs. */
1403         pci_bus_add_devices(bus);
1404 
1405         /* Fixup EEH */
1406         /* eeh_add_device_tree_late(bus); */
1407 }
1408 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1409 
1410 #endif /* CONFIG_HOTPLUG */
1411 
1412 int pcibios_enable_device(struct pci_dev *dev, int mask)
1413 {
1414         return pci_enable_resources(dev, mask);
1415 }
1416 
1417 static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources)
1418 {
1419         unsigned long io_offset;
1420         struct resource *res;
1421         int i;
1422 
1423         /* Hookup PHB IO resource */
1424         res = &hose->io_resource;
1425 
1426         /* Fixup IO space offset */
1427         io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1428         res->start = (res->start + io_offset) & 0xffffffffu;
1429         res->end = (res->end + io_offset) & 0xffffffffu;
1430 
1431         if (!res->flags) {
1432                 printk(KERN_WARNING "PCI: I/O resource not set for host"
1433                        " bridge %s (domain %d)\n",
1434                        hose->dn->full_name, hose->global_number);
1435                 /* Workaround for lack of IO resource only on 32-bit */
1436                 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1437                 res->end = res->start + IO_SPACE_LIMIT;
1438                 res->flags = IORESOURCE_IO;
1439         }
1440         pci_add_resource_offset(resources, res, hose->io_base_virt - _IO_BASE);
1441 
1442         pr_debug("PCI: PHB IO resource    = %016llx-%016llx [%lx]\n",
1443                  (unsigned long long)res->start,
1444                  (unsigned long long)res->end,
1445                  (unsigned long)res->flags);
1446 
1447         /* Hookup PHB Memory resources */
1448         for (i = 0; i < 3; ++i) {
1449                 res = &hose->mem_resources[i];
1450                 if (!res->flags) {
1451                         if (i > 0)
1452                                 continue;
1453                         printk(KERN_ERR "PCI: Memory resource 0 not set for "
1454                                "host bridge %s (domain %d)\n",
1455                                hose->dn->full_name, hose->global_number);
1456 
1457                         /* Workaround for lack of MEM resource only on 32-bit */
1458                         res->start = hose->pci_mem_offset;
1459                         res->end = (resource_size_t)-1LL;
1460                         res->flags = IORESOURCE_MEM;
1461 
1462                 }
1463                 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1464 
1465                 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1466                         i, (unsigned long long)res->start,
1467                         (unsigned long long)res->end,
1468                         (unsigned long)res->flags);
1469         }
1470 
1471         pr_debug("PCI: PHB MEM offset     = %016llx\n",
1472                  (unsigned long long)hose->pci_mem_offset);
1473         pr_debug("PCI: PHB IO  offset     = %08lx\n",
1474                  (unsigned long)hose->io_base_virt - _IO_BASE);
1475 }
1476 
1477 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1478 {
1479         struct pci_controller *hose = bus->sysdata;
1480 
1481         return of_node_get(hose->dn);
1482 }
1483 
1484 static void __devinit pcibios_scan_phb(struct pci_controller *hose)
1485 {
1486         LIST_HEAD(resources);
1487         struct pci_bus *bus;
1488         struct device_node *node = hose->dn;
1489 
1490         pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1491 
1492         pcibios_setup_phb_resources(hose, &resources);
1493 
1494         bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1495                                 hose->ops, hose, &resources);
1496         if (bus == NULL) {
1497                 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
1498                        hose->global_number);
1499                 pci_free_resource_list(&resources);
1500                 return;
1501         }
1502         bus->busn_res.start = hose->first_busno;
1503         hose->bus = bus;
1504 
1505         hose->last_busno = bus->busn_res.end;
1506 }
1507 
1508 static int __init pcibios_init(void)
1509 {
1510         struct pci_controller *hose, *tmp;
1511         int next_busno = 0;
1512 
1513         printk(KERN_INFO "PCI: Probing PCI hardware\n");
1514 
1515         /* Scan all of the recorded PCI controllers.  */
1516         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1517                 hose->last_busno = 0xff;
1518                 pcibios_scan_phb(hose);
1519                 if (next_busno <= hose->last_busno)
1520                         next_busno = hose->last_busno + 1;
1521         }
1522         pci_bus_count = next_busno;
1523 
1524         /* Call common code to handle resource allocation */
1525         pcibios_resource_survey();
1526 
1527         return 0;
1528 }
1529 
1530 subsys_initcall(pcibios_init);
1531 
1532 static struct pci_controller *pci_bus_to_hose(int bus)
1533 {
1534         struct pci_controller *hose, *tmp;
1535 
1536         list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1537                 if (bus >= hose->first_busno && bus <= hose->last_busno)
1538                         return hose;
1539         return NULL;
1540 }
1541 
1542 /* Provide information on locations of various I/O regions in physical
1543  * memory.  Do this on a per-card basis so that we choose the right
1544  * root bridge.
1545  * Note that the returned IO or memory base is a physical address
1546  */
1547 
1548 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1549 {
1550         struct pci_controller *hose;
1551         long result = -EOPNOTSUPP;
1552 
1553         hose = pci_bus_to_hose(bus);
1554         if (!hose)
1555                 return -ENODEV;
1556 
1557         switch (which) {
1558         case IOBASE_BRIDGE_NUMBER:
1559                 return (long)hose->first_busno;
1560         case IOBASE_MEMORY:
1561                 return (long)hose->pci_mem_offset;
1562         case IOBASE_IO:
1563                 return (long)hose->io_base_phys;
1564         case IOBASE_ISA_IO:
1565                 return (long)isa_io_base;
1566         case IOBASE_ISA_MEM:
1567                 return (long)isa_mem_base;
1568         }
1569 
1570         return result;
1571 }
1572 
1573 /*
1574  * Null PCI config access functions, for the case when we can't
1575  * find a hose.
1576  */
1577 #define NULL_PCI_OP(rw, size, type)                                     \
1578 static int                                                              \
1579 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)    \
1580 {                                                                       \
1581         return PCIBIOS_DEVICE_NOT_FOUND;                                \
1582 }
1583 
1584 static int
1585 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1586                  int len, u32 *val)
1587 {
1588         return PCIBIOS_DEVICE_NOT_FOUND;
1589 }
1590 
1591 static int
1592 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1593                   int len, u32 val)
1594 {
1595         return PCIBIOS_DEVICE_NOT_FOUND;
1596 }
1597 
1598 static struct pci_ops null_pci_ops = {
1599         .read = null_read_config,
1600         .write = null_write_config,
1601 };
1602 
1603 /*
1604  * These functions are used early on before PCI scanning is done
1605  * and all of the pci_dev and pci_bus structures have been created.
1606  */
1607 static struct pci_bus *
1608 fake_pci_bus(struct pci_controller *hose, int busnr)
1609 {
1610         static struct pci_bus bus;
1611 
1612         if (!hose)
1613                 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1614 
1615         bus.number = busnr;
1616         bus.sysdata = hose;
1617         bus.ops = hose ? hose->ops : &null_pci_ops;
1618         return &bus;
1619 }
1620 
1621 #define EARLY_PCI_OP(rw, size, type)                                    \
1622 int early_##rw##_config_##size(struct pci_controller *hose, int bus,    \
1623                                int devfn, int offset, type value)       \
1624 {                                                                       \
1625         return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),    \
1626                                             devfn, offset, value);      \
1627 }
1628 
1629 EARLY_PCI_OP(read, byte, u8 *)
1630 EARLY_PCI_OP(read, word, u16 *)
1631 EARLY_PCI_OP(read, dword, u32 *)
1632 EARLY_PCI_OP(write, byte, u8)
1633 EARLY_PCI_OP(write, word, u16)
1634 EARLY_PCI_OP(write, dword, u32)
1635 
1636 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1637                           int cap)
1638 {
1639         return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1640 }
1641 
1642 

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