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Linux/arch/mips/alchemy/common/time.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
  4  *
  5  * Previous incarnations were:
  6  * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
  7  * Copied and modified Carsten Langgaard's time.c
  8  *
  9  * Carsten Langgaard, carstenl@mips.com
 10  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 11  *
 12  * ########################################################################
 13  *
 14  * ########################################################################
 15  *
 16  * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
 17  * databooks).  Firmware/Board init code must enable the counters in the
 18  * counter control register, otherwise the CP0 counter clocksource/event
 19  * will be installed instead (and use of 'wait' instruction is prohibited).
 20  */
 21 
 22 #include <linux/clockchips.h>
 23 #include <linux/clocksource.h>
 24 #include <linux/interrupt.h>
 25 #include <linux/spinlock.h>
 26 
 27 #include <asm/idle.h>
 28 #include <asm/processor.h>
 29 #include <asm/time.h>
 30 #include <asm/mach-au1x00/au1000.h>
 31 
 32 /* 32kHz clock enabled and detected */
 33 #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
 34 
 35 static u64 au1x_counter1_read(struct clocksource *cs)
 36 {
 37         return alchemy_rdsys(AU1000_SYS_RTCREAD);
 38 }
 39 
 40 static struct clocksource au1x_counter1_clocksource = {
 41         .name           = "alchemy-counter1",
 42         .read           = au1x_counter1_read,
 43         .mask           = CLOCKSOURCE_MASK(32),
 44         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 45         .rating         = 1500,
 46 };
 47 
 48 static int au1x_rtcmatch2_set_next_event(unsigned long delta,
 49                                          struct clock_event_device *cd)
 50 {
 51         delta += alchemy_rdsys(AU1000_SYS_RTCREAD);
 52         /* wait for register access */
 53         while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_M21)
 54                 ;
 55         alchemy_wrsys(delta, AU1000_SYS_RTCMATCH2);
 56 
 57         return 0;
 58 }
 59 
 60 static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
 61 {
 62         struct clock_event_device *cd = dev_id;
 63         cd->event_handler(cd);
 64         return IRQ_HANDLED;
 65 }
 66 
 67 static struct clock_event_device au1x_rtcmatch2_clockdev = {
 68         .name           = "rtcmatch2",
 69         .features       = CLOCK_EVT_FEAT_ONESHOT,
 70         .rating         = 1500,
 71         .set_next_event = au1x_rtcmatch2_set_next_event,
 72         .cpumask        = cpu_possible_mask,
 73 };
 74 
 75 static struct irqaction au1x_rtcmatch2_irqaction = {
 76         .handler        = au1x_rtcmatch2_irq,
 77         .flags          = IRQF_TIMER,
 78         .name           = "timer",
 79         .dev_id         = &au1x_rtcmatch2_clockdev,
 80 };
 81 
 82 static int __init alchemy_time_init(unsigned int m2int)
 83 {
 84         struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
 85         unsigned long t;
 86 
 87         au1x_rtcmatch2_clockdev.irq = m2int;
 88 
 89         /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
 90          * has been detected.  If so install the rtcmatch2 clocksource,
 91          * otherwise don't bother.  Note that both bits being set is by
 92          * no means a definite guarantee that the counters actually work
 93          * (the 32S bit seems to be stuck set to 1 once a single clock-
 94          * edge is detected, hence the timeouts).
 95          */
 96         if (CNTR_OK != (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & CNTR_OK))
 97                 goto cntr_err;
 98 
 99         /*
100          * setup counter 1 (RTC) to tick at full speed
101          */
102         t = 0xffffff;
103         while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T1S) && --t)
104                 asm volatile ("nop");
105         if (!t)
106                 goto cntr_err;
107 
108         alchemy_wrsys(0, AU1000_SYS_RTCTRIM);   /* 32.768 kHz */
109 
110         t = 0xffffff;
111         while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
112                 asm volatile ("nop");
113         if (!t)
114                 goto cntr_err;
115         alchemy_wrsys(0, AU1000_SYS_RTCWRITE);
116 
117         t = 0xffffff;
118         while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
119                 asm volatile ("nop");
120         if (!t)
121                 goto cntr_err;
122 
123         /* register counter1 clocksource and event device */
124         clocksource_register_hz(&au1x_counter1_clocksource, 32768);
125 
126         cd->shift = 32;
127         cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
128         cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
129         cd->max_delta_ticks = 0xffffffff;
130         cd->min_delta_ns = clockevent_delta2ns(9, cd);
131         cd->min_delta_ticks = 9;        /* ~0.28ms */
132         clockevents_register_device(cd);
133         setup_irq(m2int, &au1x_rtcmatch2_irqaction);
134 
135         printk(KERN_INFO "Alchemy clocksource installed\n");
136 
137         return 0;
138 
139 cntr_err:
140         return -1;
141 }
142 
143 static int alchemy_m2inttab[] __initdata = {
144         AU1000_RTC_MATCH2_INT,
145         AU1500_RTC_MATCH2_INT,
146         AU1100_RTC_MATCH2_INT,
147         AU1550_RTC_MATCH2_INT,
148         AU1200_RTC_MATCH2_INT,
149         AU1300_RTC_MATCH2_INT,
150 };
151 
152 void __init plat_time_init(void)
153 {
154         int t;
155 
156         t = alchemy_get_cputype();
157         if (t == ALCHEMY_CPU_UNKNOWN ||
158             alchemy_time_init(alchemy_m2inttab[t]))
159                 cpu_wait = NULL;        /* wait doesn't work with r4k timer */
160 }
161 

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