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TOMOYO Linux Cross Reference
Linux/arch/mips/alchemy/devboards/db1000.c

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  1 /*
  2  * DBAu1000/1500/1100 PBAu1100/1500 board support
  3  *
  4  * Copyright 2000, 2008 MontaVista Software Inc.
  5  * Author: MontaVista Software, Inc. <source@mvista.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * This program is distributed in the hope that it will be useful,
 13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15  * GNU General Public License for more details.
 16  *
 17  * You should have received a copy of the GNU General Public License
 18  * along with this program; if not, write to the Free Software
 19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 20  */
 21 
 22 #include <linux/clk.h>
 23 #include <linux/dma-mapping.h>
 24 #include <linux/gpio.h>
 25 #include <linux/gpio/machine.h>
 26 #include <linux/init.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/leds.h>
 29 #include <linux/mmc/host.h>
 30 #include <linux/module.h>
 31 #include <linux/platform_device.h>
 32 #include <linux/pm.h>
 33 #include <linux/spi/spi.h>
 34 #include <linux/spi/spi_gpio.h>
 35 #include <linux/spi/ads7846.h>
 36 #include <asm/mach-au1x00/au1000.h>
 37 #include <asm/mach-au1x00/gpio-au1000.h>
 38 #include <asm/mach-au1x00/au1000_dma.h>
 39 #include <asm/mach-au1x00/au1100_mmc.h>
 40 #include <asm/mach-db1x00/bcsr.h>
 41 #include <asm/reboot.h>
 42 #include <prom.h>
 43 #include "platform.h"
 44 
 45 #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
 46 
 47 const char *get_system_type(void);
 48 
 49 int __init db1000_board_setup(void)
 50 {
 51         /* initialize board register space */
 52         bcsr_init(DB1000_BCSR_PHYS_ADDR,
 53                   DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
 54 
 55         switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
 56         case BCSR_WHOAMI_DB1000:
 57         case BCSR_WHOAMI_DB1500:
 58         case BCSR_WHOAMI_DB1100:
 59         case BCSR_WHOAMI_PB1500:
 60         case BCSR_WHOAMI_PB1500R2:
 61         case BCSR_WHOAMI_PB1100:
 62                 pr_info("AMD Alchemy %s Board\n", get_system_type());
 63                 return 0;
 64         }
 65         return -ENODEV;
 66 }
 67 
 68 static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 69 {
 70         if ((slot < 12) || (slot > 13) || pin == 0)
 71                 return -1;
 72         if (slot == 12)
 73                 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
 74         if (slot == 13) {
 75                 switch (pin) {
 76                 case 1: return AU1500_PCI_INTA;
 77                 case 2: return AU1500_PCI_INTB;
 78                 case 3: return AU1500_PCI_INTC;
 79                 case 4: return AU1500_PCI_INTD;
 80                 }
 81         }
 82         return -1;
 83 }
 84 
 85 static struct resource alchemy_pci_host_res[] = {
 86         [0] = {
 87                 .start  = AU1500_PCI_PHYS_ADDR,
 88                 .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
 89                 .flags  = IORESOURCE_MEM,
 90         },
 91 };
 92 
 93 static struct alchemy_pci_platdata db1500_pci_pd = {
 94         .board_map_irq  = db1500_map_pci_irq,
 95 };
 96 
 97 static struct platform_device db1500_pci_host_dev = {
 98         .dev.platform_data = &db1500_pci_pd,
 99         .name           = "alchemy-pci",
100         .id             = 0,
101         .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
102         .resource       = alchemy_pci_host_res,
103 };
104 
105 int __init db1500_pci_setup(void)
106 {
107         return platform_device_register(&db1500_pci_host_dev);
108 }
109 
110 static struct resource au1100_lcd_resources[] = {
111         [0] = {
112                 .start  = AU1100_LCD_PHYS_ADDR,
113                 .end    = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
114                 .flags  = IORESOURCE_MEM,
115         },
116         [1] = {
117                 .start  = AU1100_LCD_INT,
118                 .end    = AU1100_LCD_INT,
119                 .flags  = IORESOURCE_IRQ,
120         }
121 };
122 
123 static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
124 
125 static struct platform_device au1100_lcd_device = {
126         .name           = "au1100-lcd",
127         .id             = 0,
128         .dev = {
129                 .dma_mask               = &au1100_lcd_dmamask,
130                 .coherent_dma_mask      = DMA_BIT_MASK(32),
131         },
132         .num_resources  = ARRAY_SIZE(au1100_lcd_resources),
133         .resource       = au1100_lcd_resources,
134 };
135 
136 static struct resource alchemy_ac97c_res[] = {
137         [0] = {
138                 .start  = AU1000_AC97_PHYS_ADDR,
139                 .end    = AU1000_AC97_PHYS_ADDR + 0xfff,
140                 .flags  = IORESOURCE_MEM,
141         },
142         [1] = {
143                 .start  = DMA_ID_AC97C_TX,
144                 .end    = DMA_ID_AC97C_TX,
145                 .flags  = IORESOURCE_DMA,
146         },
147         [2] = {
148                 .start  = DMA_ID_AC97C_RX,
149                 .end    = DMA_ID_AC97C_RX,
150                 .flags  = IORESOURCE_DMA,
151         },
152 };
153 
154 static struct platform_device alchemy_ac97c_dev = {
155         .name           = "alchemy-ac97c",
156         .id             = -1,
157         .resource       = alchemy_ac97c_res,
158         .num_resources  = ARRAY_SIZE(alchemy_ac97c_res),
159 };
160 
161 static struct platform_device alchemy_ac97c_dma_dev = {
162         .name           = "alchemy-pcm-dma",
163         .id             = 0,
164 };
165 
166 static struct platform_device db1x00_codec_dev = {
167         .name           = "ac97-codec",
168         .id             = -1,
169 };
170 
171 static struct platform_device db1x00_audio_dev = {
172         .name           = "db1000-audio",
173 };
174 
175 /******************************************************************************/
176 
177 static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
178 {
179         void (*mmc_cd)(struct mmc_host *, unsigned long);
180         /* link against CONFIG_MMC=m */
181         mmc_cd = symbol_get(mmc_detect_change);
182         mmc_cd(ptr, msecs_to_jiffies(500));
183         symbol_put(mmc_detect_change);
184 
185         return IRQ_HANDLED;
186 }
187 
188 static int db1100_mmc_cd_setup(void *mmc_host, int en)
189 {
190         int ret = 0, irq;
191 
192         if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
193                 irq = AU1100_GPIO19_INT;
194         else
195                 irq = AU1100_GPIO14_INT;        /* PB1100 SD0 CD# */
196 
197         if (en) {
198                 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
199                 ret = request_irq(irq, db1100_mmc_cd, 0,
200                                   "sd0_cd", mmc_host);
201         } else
202                 free_irq(irq, mmc_host);
203         return ret;
204 }
205 
206 static int db1100_mmc1_cd_setup(void *mmc_host, int en)
207 {
208         int ret = 0, irq;
209 
210         if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
211                 irq = AU1100_GPIO20_INT;
212         else
213                 irq = AU1100_GPIO15_INT;        /* PB1100 SD1 CD# */
214 
215         if (en) {
216                 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
217                 ret = request_irq(irq, db1100_mmc_cd, 0,
218                                   "sd1_cd", mmc_host);
219         } else
220                 free_irq(irq, mmc_host);
221         return ret;
222 }
223 
224 static int db1100_mmc_card_readonly(void *mmc_host)
225 {
226         /* testing suggests that this bit is inverted */
227         return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1;
228 }
229 
230 static int db1100_mmc_card_inserted(void *mmc_host)
231 {
232         return !alchemy_gpio_get_value(19);
233 }
234 
235 static void db1100_mmc_set_power(void *mmc_host, int state)
236 {
237         int bit;
238 
239         if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
240                 bit = BCSR_BOARD_SD0PWR;
241         else
242                 bit = BCSR_BOARD_PB1100_SD0PWR;
243 
244         if (state) {
245                 bcsr_mod(BCSR_BOARD, 0, bit);
246                 msleep(400);    /* stabilization time */
247         } else
248                 bcsr_mod(BCSR_BOARD, bit, 0);
249 }
250 
251 static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
252 {
253         if (b != LED_OFF)
254                 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
255         else
256                 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
257 }
258 
259 static struct led_classdev db1100_mmc_led = {
260         .brightness_set = db1100_mmcled_set,
261 };
262 
263 static int db1100_mmc1_card_readonly(void *mmc_host)
264 {
265         return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0;
266 }
267 
268 static int db1100_mmc1_card_inserted(void *mmc_host)
269 {
270         return !alchemy_gpio_get_value(20);
271 }
272 
273 static void db1100_mmc1_set_power(void *mmc_host, int state)
274 {
275         int bit;
276 
277         if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
278                 bit = BCSR_BOARD_SD1PWR;
279         else
280                 bit = BCSR_BOARD_PB1100_SD1PWR;
281 
282         if (state) {
283                 bcsr_mod(BCSR_BOARD, 0, bit);
284                 msleep(400);    /* stabilization time */
285         } else
286                 bcsr_mod(BCSR_BOARD, bit, 0);
287 }
288 
289 static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
290 {
291         if (b != LED_OFF)
292                 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
293         else
294                 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
295 }
296 
297 static struct led_classdev db1100_mmc1_led = {
298         .brightness_set = db1100_mmc1led_set,
299 };
300 
301 static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {
302         [0] = {
303                 .cd_setup       = db1100_mmc_cd_setup,
304                 .set_power      = db1100_mmc_set_power,
305                 .card_inserted  = db1100_mmc_card_inserted,
306                 .card_readonly  = db1100_mmc_card_readonly,
307                 .led            = &db1100_mmc_led,
308         },
309         [1] = {
310                 .cd_setup       = db1100_mmc1_cd_setup,
311                 .set_power      = db1100_mmc1_set_power,
312                 .card_inserted  = db1100_mmc1_card_inserted,
313                 .card_readonly  = db1100_mmc1_card_readonly,
314                 .led            = &db1100_mmc1_led,
315         },
316 };
317 
318 static struct resource au1100_mmc0_resources[] = {
319         [0] = {
320                 .start  = AU1100_SD0_PHYS_ADDR,
321                 .end    = AU1100_SD0_PHYS_ADDR + 0xfff,
322                 .flags  = IORESOURCE_MEM,
323         },
324         [1] = {
325                 .start  = AU1100_SD_INT,
326                 .end    = AU1100_SD_INT,
327                 .flags  = IORESOURCE_IRQ,
328         },
329         [2] = {
330                 .start  = DMA_ID_SD0_TX,
331                 .end    = DMA_ID_SD0_TX,
332                 .flags  = IORESOURCE_DMA,
333         },
334         [3] = {
335                 .start  = DMA_ID_SD0_RX,
336                 .end    = DMA_ID_SD0_RX,
337                 .flags  = IORESOURCE_DMA,
338         }
339 };
340 
341 static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
342 
343 static struct platform_device db1100_mmc0_dev = {
344         .name           = "au1xxx-mmc",
345         .id             = 0,
346         .dev = {
347                 .dma_mask               = &au1xxx_mmc_dmamask,
348                 .coherent_dma_mask      = DMA_BIT_MASK(32),
349                 .platform_data          = &db1100_mmc_platdata[0],
350         },
351         .num_resources  = ARRAY_SIZE(au1100_mmc0_resources),
352         .resource       = au1100_mmc0_resources,
353 };
354 
355 static struct resource au1100_mmc1_res[] = {
356         [0] = {
357                 .start  = AU1100_SD1_PHYS_ADDR,
358                 .end    = AU1100_SD1_PHYS_ADDR + 0xfff,
359                 .flags  = IORESOURCE_MEM,
360         },
361         [1] = {
362                 .start  = AU1100_SD_INT,
363                 .end    = AU1100_SD_INT,
364                 .flags  = IORESOURCE_IRQ,
365         },
366         [2] = {
367                 .start  = DMA_ID_SD1_TX,
368                 .end    = DMA_ID_SD1_TX,
369                 .flags  = IORESOURCE_DMA,
370         },
371         [3] = {
372                 .start  = DMA_ID_SD1_RX,
373                 .end    = DMA_ID_SD1_RX,
374                 .flags  = IORESOURCE_DMA,
375         }
376 };
377 
378 static struct platform_device db1100_mmc1_dev = {
379         .name           = "au1xxx-mmc",
380         .id             = 1,
381         .dev = {
382                 .dma_mask               = &au1xxx_mmc_dmamask,
383                 .coherent_dma_mask      = DMA_BIT_MASK(32),
384                 .platform_data          = &db1100_mmc_platdata[1],
385         },
386         .num_resources  = ARRAY_SIZE(au1100_mmc1_res),
387         .resource       = au1100_mmc1_res,
388 };
389 
390 /******************************************************************************/
391 
392 static void db1000_irda_set_phy_mode(int mode)
393 {
394         unsigned short mask = BCSR_RESETS_IRDA_MODE_MASK | BCSR_RESETS_FIR_SEL;
395 
396         switch (mode) {
397         case AU1000_IRDA_PHY_MODE_OFF:
398                 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_OFF);
399                 break;
400         case AU1000_IRDA_PHY_MODE_SIR:
401                 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL);
402                 break;
403         case AU1000_IRDA_PHY_MODE_FIR:
404                 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL |
405                                             BCSR_RESETS_FIR_SEL);
406                 break;
407         }
408 }
409 
410 static struct au1k_irda_platform_data db1000_irda_platdata = {
411         .set_phy_mode   = db1000_irda_set_phy_mode,
412 };
413 
414 static struct resource au1000_irda_res[] = {
415         [0] = {
416                 .start  = AU1000_IRDA_PHYS_ADDR,
417                 .end    = AU1000_IRDA_PHYS_ADDR + 0x0fff,
418                 .flags  = IORESOURCE_MEM,
419         },
420         [1] = {
421                 .start  = AU1000_IRDA_TX_INT,
422                 .end    = AU1000_IRDA_TX_INT,
423                 .flags  = IORESOURCE_IRQ,
424         },
425         [2] = {
426                 .start  = AU1000_IRDA_RX_INT,
427                 .end    = AU1000_IRDA_RX_INT,
428                 .flags  = IORESOURCE_IRQ,
429         },
430 };
431 
432 static struct platform_device db1000_irda_dev = {
433         .name   = "au1000-irda",
434         .id     = -1,
435         .dev    = {
436                 .platform_data = &db1000_irda_platdata,
437         },
438         .resource       = au1000_irda_res,
439         .num_resources  = ARRAY_SIZE(au1000_irda_res),
440 };
441 
442 /******************************************************************************/
443 
444 static struct ads7846_platform_data db1100_touch_pd = {
445         .model          = 7846,
446         .vref_mv        = 3300,
447         .gpio_pendown   = 21,
448 };
449 
450 static struct spi_gpio_platform_data db1100_spictl_pd = {
451         .num_chipselect = 1,
452 };
453 
454 static struct spi_board_info db1100_spi_info[] __initdata = {
455         [0] = {
456                 .modalias        = "ads7846",
457                 .max_speed_hz    = 3250000,
458                 .bus_num         = 0,
459                 .chip_select     = 0,
460                 .mode            = 0,
461                 .irq             = AU1100_GPIO21_INT,
462                 .platform_data   = &db1100_touch_pd,
463         },
464 };
465 
466 static struct platform_device db1100_spi_dev = {
467         .name           = "spi_gpio",
468         .id             = 0,
469         .dev            = {
470                 .platform_data  = &db1100_spictl_pd,
471         },
472 };
473 
474 /*
475  * Alchemy GPIO 2 has its base at 200 so the GPIO lines
476  * 207 thru 210 are GPIOs at offset 7 thru 10 at this chip.
477  */
478 static struct gpiod_lookup_table db1100_spi_gpiod_table = {
479         .dev_id         = "spi_gpio",
480         .table          = {
481                 GPIO_LOOKUP("alchemy-gpio2", 9,
482                             "sck", GPIO_ACTIVE_HIGH),
483                 GPIO_LOOKUP("alchemy-gpio2", 8,
484                             "mosi", GPIO_ACTIVE_HIGH),
485                 GPIO_LOOKUP("alchemy-gpio2", 7,
486                             "miso", GPIO_ACTIVE_HIGH),
487                 GPIO_LOOKUP("alchemy-gpio2", 10,
488                             "cs", GPIO_ACTIVE_HIGH),
489                 { },
490         },
491 };
492 
493 static struct platform_device *db1x00_devs[] = {
494         &db1x00_codec_dev,
495         &alchemy_ac97c_dma_dev,
496         &alchemy_ac97c_dev,
497         &db1x00_audio_dev,
498 };
499 
500 static struct platform_device *db1000_devs[] = {
501         &db1000_irda_dev,
502 };
503 
504 static struct platform_device *db1100_devs[] = {
505         &au1100_lcd_device,
506         &db1100_mmc0_dev,
507         &db1100_mmc1_dev,
508         &db1000_irda_dev,
509 };
510 
511 int __init db1000_dev_setup(void)
512 {
513         int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
514         int c0, c1, d0, d1, s0, s1, flashsize = 32,  twosocks = 1;
515         unsigned long pfc;
516         struct clk *c, *p;
517 
518         if (board == BCSR_WHOAMI_DB1500) {
519                 c0 = AU1500_GPIO2_INT;
520                 c1 = AU1500_GPIO5_INT;
521                 d0 = 0; /* GPIO number, NOT irq! */
522                 d1 = 3; /* GPIO number, NOT irq! */
523                 s0 = AU1500_GPIO1_INT;
524                 s1 = AU1500_GPIO4_INT;
525         } else if (board == BCSR_WHOAMI_DB1100) {
526                 c0 = AU1100_GPIO2_INT;
527                 c1 = AU1100_GPIO5_INT;
528                 d0 = 0; /* GPIO number, NOT irq! */
529                 d1 = 3; /* GPIO number, NOT irq! */
530                 s0 = AU1100_GPIO1_INT;
531                 s1 = AU1100_GPIO4_INT;
532 
533                 gpio_request(19, "sd0_cd");
534                 gpio_request(20, "sd1_cd");
535                 gpio_direction_input(19);       /* sd0 cd# */
536                 gpio_direction_input(20);       /* sd1 cd# */
537 
538                 /* spi_gpio on SSI0 pins */
539                 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
540                 pfc |= (1 << 0);        /* SSI0 pins as GPIOs */
541                 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
542 
543                 spi_register_board_info(db1100_spi_info,
544                                         ARRAY_SIZE(db1100_spi_info));
545 
546                 /* link LCD clock to AUXPLL */
547                 p = clk_get(NULL, "auxpll_clk");
548                 c = clk_get(NULL, "lcd_intclk");
549                 if (!IS_ERR(c) && !IS_ERR(p)) {
550                         clk_set_parent(c, p);
551                         clk_set_rate(c, clk_get_rate(p));
552                 }
553                 if (!IS_ERR(c))
554                         clk_put(c);
555                 if (!IS_ERR(p))
556                         clk_put(p);
557 
558                 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
559                 gpiod_add_lookup_table(&db1100_spi_gpiod_table);
560                 platform_device_register(&db1100_spi_dev);
561         } else if (board == BCSR_WHOAMI_DB1000) {
562                 c0 = AU1000_GPIO2_INT;
563                 c1 = AU1000_GPIO5_INT;
564                 d0 = 0; /* GPIO number, NOT irq! */
565                 d1 = 3; /* GPIO number, NOT irq! */
566                 s0 = AU1000_GPIO1_INT;
567                 s1 = AU1000_GPIO4_INT;
568                 platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs));
569         } else if ((board == BCSR_WHOAMI_PB1500) ||
570                    (board == BCSR_WHOAMI_PB1500R2)) {
571                 c0 = AU1500_GPIO203_INT;
572                 d0 = 1; /* GPIO number, NOT irq! */
573                 s0 = AU1500_GPIO202_INT;
574                 twosocks = 0;
575                 flashsize = 64;
576                 /* RTC and daughtercard irqs */
577                 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW);
578                 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
579                 /* EPSON S1D13806 0x1b000000
580                  * SRAM 1MB/2MB   0x1a000000
581                  * DS1693 RTC     0x0c000000
582                  */
583         } else if (board == BCSR_WHOAMI_PB1100) {
584                 c0 = AU1100_GPIO11_INT;
585                 d0 = 9; /* GPIO number, NOT irq! */
586                 s0 = AU1100_GPIO10_INT;
587                 twosocks = 0;
588                 flashsize = 64;
589                 /* pendown, rtc, daughtercard irqs */
590                 irq_set_irq_type(AU1100_GPIO8_INT, IRQ_TYPE_LEVEL_LOW);
591                 irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW);
592                 irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW);
593                 /* EPSON S1D13806 0x1b000000
594                  * SRAM 1MB/2MB   0x1a000000
595                  * DiskOnChip     0x0d000000
596                  * DS1693 RTC     0x0c000000
597                  */
598                 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
599         } else
600                 return 0; /* unknown board, no further dev setup to do */
601 
602         irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
603         irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
604 
605         db1x_register_pcmcia_socket(
606                 AU1000_PCMCIA_ATTR_PHYS_ADDR,
607                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
608                 AU1000_PCMCIA_MEM_PHYS_ADDR,
609                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
610                 AU1000_PCMCIA_IO_PHYS_ADDR,
611                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
612                 c0, d0, /*s0*/0, 0, 0);
613 
614         if (twosocks) {
615                 irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
616                 irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
617 
618                 db1x_register_pcmcia_socket(
619                         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
620                         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
621                         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
622                         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
623                         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
624                         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
625                         c1, d1, /*s1*/0, 0, 1);
626         }
627 
628         platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
629         db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED);
630         return 0;
631 }
632 

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