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TOMOYO Linux Cross Reference
Linux/arch/mips/cavium-octeon/setup.c

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  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Copyright (C) 2004-2007 Cavium Networks
  7  * Copyright (C) 2008, 2009 Wind River Systems
  8  *   written by Ralf Baechle <ralf@linux-mips.org>
  9  */
 10 #include <linux/compiler.h>
 11 #include <linux/vmalloc.h>
 12 #include <linux/init.h>
 13 #include <linux/kernel.h>
 14 #include <linux/console.h>
 15 #include <linux/delay.h>
 16 #include <linux/export.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/io.h>
 19 #include <linux/serial.h>
 20 #include <linux/smp.h>
 21 #include <linux/types.h>
 22 #include <linux/string.h>       /* for memset */
 23 #include <linux/tty.h>
 24 #include <linux/time.h>
 25 #include <linux/platform_device.h>
 26 #include <linux/serial_core.h>
 27 #include <linux/serial_8250.h>
 28 #include <linux/of_fdt.h>
 29 #include <linux/libfdt.h>
 30 #include <linux/kexec.h>
 31 
 32 #include <asm/processor.h>
 33 #include <asm/reboot.h>
 34 #include <asm/smp-ops.h>
 35 #include <asm/irq_cpu.h>
 36 #include <asm/mipsregs.h>
 37 #include <asm/bootinfo.h>
 38 #include <asm/sections.h>
 39 #include <asm/setup.h>
 40 #include <asm/time.h>
 41 
 42 #include <asm/octeon/octeon.h>
 43 #include <asm/octeon/pci-octeon.h>
 44 #include <asm/octeon/cvmx-rst-defs.h>
 45 
 46 /*
 47  * TRUE for devices having registers with little-endian byte
 48  * order, FALSE for registers with native-endian byte order.
 49  * PCI mandates little-endian, USB and SATA are configuraable,
 50  * but we chose little-endian for these.
 51  */
 52 const bool octeon_should_swizzle_table[256] = {
 53         [0x00] = true,  /* bootbus/CF */
 54         [0x1b] = true,  /* PCI mmio window */
 55         [0x1c] = true,  /* PCI mmio window */
 56         [0x1d] = true,  /* PCI mmio window */
 57         [0x1e] = true,  /* PCI mmio window */
 58         [0x68] = true,  /* OCTEON III USB */
 59         [0x69] = true,  /* OCTEON III USB */
 60         [0x6c] = true,  /* OCTEON III SATA */
 61         [0x6f] = true,  /* OCTEON II USB */
 62 };
 63 EXPORT_SYMBOL(octeon_should_swizzle_table);
 64 
 65 #ifdef CONFIG_PCI
 66 extern void pci_console_init(const char *arg);
 67 #endif
 68 
 69 static unsigned long long max_memory = ULLONG_MAX;
 70 static unsigned long long reserve_low_mem;
 71 
 72 DEFINE_SEMAPHORE(octeon_bootbus_sem);
 73 EXPORT_SYMBOL(octeon_bootbus_sem);
 74 
 75 struct octeon_boot_descriptor *octeon_boot_desc_ptr;
 76 
 77 struct cvmx_bootinfo *octeon_bootinfo;
 78 EXPORT_SYMBOL(octeon_bootinfo);
 79 
 80 #ifdef CONFIG_KEXEC
 81 #ifdef CONFIG_SMP
 82 /*
 83  * Wait for relocation code is prepared and send
 84  * secondary CPUs to spin until kernel is relocated.
 85  */
 86 static void octeon_kexec_smp_down(void *ignored)
 87 {
 88         int cpu = smp_processor_id();
 89 
 90         local_irq_disable();
 91         set_cpu_online(cpu, false);
 92         while (!atomic_read(&kexec_ready_to_reboot))
 93                 cpu_relax();
 94 
 95         asm volatile (
 96         "       sync                                            \n"
 97         "       synci   ($0)                                    \n");
 98 
 99         kexec_reboot();
100 }
101 #endif
102 
103 #define OCTEON_DDR0_BASE    (0x0ULL)
104 #define OCTEON_DDR0_SIZE    (0x010000000ULL)
105 #define OCTEON_DDR1_BASE    (0x410000000ULL)
106 #define OCTEON_DDR1_SIZE    (0x010000000ULL)
107 #define OCTEON_DDR2_BASE    (0x020000000ULL)
108 #define OCTEON_DDR2_SIZE    (0x3e0000000ULL)
109 #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
110 
111 static struct kimage *kimage_ptr;
112 
113 static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes)
114 {
115         int64_t addr;
116         struct cvmx_bootmem_desc *bootmem_desc;
117 
118         bootmem_desc = cvmx_bootmem_get_desc();
119 
120         if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) {
121                 mem_size = OCTEON_MAX_PHY_MEM_SIZE;
122                 pr_err("Error: requested memory too large,"
123                        "truncating to maximum size\n");
124         }
125 
126         bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
127         bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
128 
129         addr = (OCTEON_DDR0_BASE + reserve_low_mem + low_reserved_bytes);
130         bootmem_desc->head_addr = 0;
131 
132         if (mem_size <= OCTEON_DDR0_SIZE) {
133                 __cvmx_bootmem_phy_free(addr,
134                                 mem_size - reserve_low_mem -
135                                 low_reserved_bytes, 0);
136                 return;
137         }
138 
139         __cvmx_bootmem_phy_free(addr,
140                         OCTEON_DDR0_SIZE - reserve_low_mem -
141                         low_reserved_bytes, 0);
142 
143         mem_size -= OCTEON_DDR0_SIZE;
144 
145         if (mem_size > OCTEON_DDR1_SIZE) {
146                 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
147                 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
148                                 mem_size - OCTEON_DDR1_SIZE, 0);
149         } else
150                 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
151 }
152 
153 static int octeon_kexec_prepare(struct kimage *image)
154 {
155         int i;
156         char *bootloader = "kexec";
157 
158         octeon_boot_desc_ptr->argc = 0;
159         for (i = 0; i < image->nr_segments; i++) {
160                 if (!strncmp(bootloader, (char *)image->segment[i].buf,
161                                 strlen(bootloader))) {
162                         /*
163                          * convert command line string to array
164                          * of parameters (as bootloader does).
165                          */
166                         int argc = 0, offt;
167                         char *str = (char *)image->segment[i].buf;
168                         char *ptr = strchr(str, ' ');
169                         while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) {
170                                 *ptr = '\0';
171                                 if (ptr[1] != ' ') {
172                                         offt = (int)(ptr - str + 1);
173                                         octeon_boot_desc_ptr->argv[argc] =
174                                                 image->segment[i].mem + offt;
175                                         argc++;
176                                 }
177                                 ptr = strchr(ptr + 1, ' ');
178                         }
179                         octeon_boot_desc_ptr->argc = argc;
180                         break;
181                 }
182         }
183 
184         /*
185          * Information about segments will be needed during pre-boot memory
186          * initialization.
187          */
188         kimage_ptr = image;
189         return 0;
190 }
191 
192 static void octeon_generic_shutdown(void)
193 {
194         int i;
195 #ifdef CONFIG_SMP
196         int cpu;
197 #endif
198         struct cvmx_bootmem_desc *bootmem_desc;
199         void *named_block_array_ptr;
200 
201         bootmem_desc = cvmx_bootmem_get_desc();
202         named_block_array_ptr =
203                 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr);
204 
205 #ifdef CONFIG_SMP
206         /* disable watchdogs */
207         for_each_online_cpu(cpu)
208                 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
209 #else
210         cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
211 #endif
212         if (kimage_ptr != kexec_crash_image) {
213                 memset(named_block_array_ptr,
214                         0x0,
215                         CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
216                         sizeof(struct cvmx_bootmem_named_block_desc));
217                 /*
218                  * Mark all memory (except low 0x100000 bytes) as free.
219                  * It is the same thing that bootloader does.
220                  */
221                 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL,
222                                 0x100000);
223                 /*
224                  * Allocate all segments to avoid their corruption during boot.
225                  */
226                 for (i = 0; i < kimage_ptr->nr_segments; i++)
227                         cvmx_bootmem_alloc_address(
228                                 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE,
229                                 kimage_ptr->segment[i].mem - PAGE_SIZE,
230                                 PAGE_SIZE);
231         } else {
232                 /*
233                  * Do not mark all memory as free. Free only named sections
234                  * leaving the rest of memory unchanged.
235                  */
236                 struct cvmx_bootmem_named_block_desc *ptr =
237                         (struct cvmx_bootmem_named_block_desc *)
238                         named_block_array_ptr;
239 
240                 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++)
241                         if (ptr[i].size)
242                                 cvmx_bootmem_free_named(ptr[i].name);
243         }
244         kexec_args[2] = 1UL; /* running on octeon_main_processor */
245         kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
246 #ifdef CONFIG_SMP
247         secondary_kexec_args[2] = 0UL; /* running on secondary cpu */
248         secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
249 #endif
250 }
251 
252 static void octeon_shutdown(void)
253 {
254         octeon_generic_shutdown();
255 #ifdef CONFIG_SMP
256         smp_call_function(octeon_kexec_smp_down, NULL, 0);
257         smp_wmb();
258         while (num_online_cpus() > 1) {
259                 cpu_relax();
260                 mdelay(1);
261         }
262 #endif
263 }
264 
265 static void octeon_crash_shutdown(struct pt_regs *regs)
266 {
267         octeon_generic_shutdown();
268         default_machine_crash_shutdown(regs);
269 }
270 
271 #ifdef CONFIG_SMP
272 void octeon_crash_smp_send_stop(void)
273 {
274         int cpu;
275 
276         /* disable watchdogs */
277         for_each_online_cpu(cpu)
278                 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
279 }
280 #endif
281 
282 #endif /* CONFIG_KEXEC */
283 
284 #ifdef CONFIG_CAVIUM_RESERVE32
285 uint64_t octeon_reserve32_memory;
286 EXPORT_SYMBOL(octeon_reserve32_memory);
287 #endif
288 
289 #ifdef CONFIG_KEXEC
290 /* crashkernel cmdline parameter is parsed _after_ memory setup
291  * we also parse it here (workaround for EHB5200) */
292 static uint64_t crashk_size, crashk_base;
293 #endif
294 
295 static int octeon_uart;
296 
297 extern asmlinkage void handle_int(void);
298 
299 /**
300  * Return non zero if we are currently running in the Octeon simulator
301  *
302  * Returns
303  */
304 int octeon_is_simulation(void)
305 {
306         return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
307 }
308 EXPORT_SYMBOL(octeon_is_simulation);
309 
310 /**
311  * Return true if Octeon is in PCI Host mode. This means
312  * Linux can control the PCI bus.
313  *
314  * Returns Non zero if Octeon in host mode.
315  */
316 int octeon_is_pci_host(void)
317 {
318 #ifdef CONFIG_PCI
319         return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
320 #else
321         return 0;
322 #endif
323 }
324 
325 /**
326  * Get the clock rate of Octeon
327  *
328  * Returns Clock rate in HZ
329  */
330 uint64_t octeon_get_clock_rate(void)
331 {
332         struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
333 
334         return sysinfo->cpu_clock_hz;
335 }
336 EXPORT_SYMBOL(octeon_get_clock_rate);
337 
338 static u64 octeon_io_clock_rate;
339 
340 u64 octeon_get_io_clock_rate(void)
341 {
342         return octeon_io_clock_rate;
343 }
344 EXPORT_SYMBOL(octeon_get_io_clock_rate);
345 
346 
347 /**
348  * Write to the LCD display connected to the bootbus. This display
349  * exists on most Cavium evaluation boards. If it doesn't exist, then
350  * this function doesn't do anything.
351  *
352  * @s:      String to write
353  */
354 void octeon_write_lcd(const char *s)
355 {
356         if (octeon_bootinfo->led_display_base_addr) {
357                 void __iomem *lcd_address =
358                         ioremap_nocache(octeon_bootinfo->led_display_base_addr,
359                                         8);
360                 int i;
361                 for (i = 0; i < 8; i++, s++) {
362                         if (*s)
363                                 iowrite8(*s, lcd_address + i);
364                         else
365                                 iowrite8(' ', lcd_address + i);
366                 }
367                 iounmap(lcd_address);
368         }
369 }
370 
371 /**
372  * Return the console uart passed by the bootloader
373  *
374  * Returns uart   (0 or 1)
375  */
376 int octeon_get_boot_uart(void)
377 {
378         return (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
379                 1 : 0;
380 }
381 
382 /**
383  * Get the coremask Linux was booted on.
384  *
385  * Returns Core mask
386  */
387 int octeon_get_boot_coremask(void)
388 {
389         return octeon_boot_desc_ptr->core_mask;
390 }
391 
392 /**
393  * Check the hardware BIST results for a CPU
394  */
395 void octeon_check_cpu_bist(void)
396 {
397         const int coreid = cvmx_get_core_num();
398         unsigned long long mask;
399         unsigned long long bist_val;
400 
401         /* Check BIST results for COP0 registers */
402         mask = 0x1f00000000ull;
403         bist_val = read_octeon_c0_icacheerr();
404         if (bist_val & mask)
405                 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
406                        coreid, bist_val);
407 
408         bist_val = read_octeon_c0_dcacheerr();
409         if (bist_val & 1)
410                 pr_err("Core%d L1 Dcache parity error: "
411                        "CacheErr(dcache) = 0x%llx\n",
412                        coreid, bist_val);
413 
414         mask = 0xfc00000000000000ull;
415         bist_val = read_c0_cvmmemctl();
416         if (bist_val & mask)
417                 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
418                        coreid, bist_val);
419 
420         write_octeon_c0_dcacheerr(0);
421 }
422 
423 /**
424  * Reboot Octeon
425  *
426  * @command: Command to pass to the bootloader. Currently ignored.
427  */
428 static void octeon_restart(char *command)
429 {
430         /* Disable all watchdogs before soft reset. They don't get cleared */
431 #ifdef CONFIG_SMP
432         int cpu;
433         for_each_online_cpu(cpu)
434                 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
435 #else
436         cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
437 #endif
438 
439         mb();
440         while (1)
441                 if (OCTEON_IS_OCTEON3())
442                         cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
443                 else
444                         cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
445 }
446 
447 
448 /**
449  * Permanently stop a core.
450  *
451  * @arg: Ignored.
452  */
453 static void octeon_kill_core(void *arg)
454 {
455         if (octeon_is_simulation())
456                 /* A break instruction causes the simulator stop a core */
457                 asm volatile ("break" ::: "memory");
458 
459         local_irq_disable();
460         /* Disable watchdog on this core. */
461         cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
462         /* Spin in a low power mode. */
463         while (true)
464                 asm volatile ("wait" ::: "memory");
465 }
466 
467 
468 /**
469  * Halt the system
470  */
471 static void octeon_halt(void)
472 {
473         smp_call_function(octeon_kill_core, NULL, 0);
474 
475         switch (octeon_bootinfo->board_type) {
476         case CVMX_BOARD_TYPE_NAO38:
477                 /* Driving a 1 to GPIO 12 shuts off this board */
478                 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
479                 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
480                 break;
481         default:
482                 octeon_write_lcd("PowerOff");
483                 break;
484         }
485 
486         octeon_kill_core(NULL);
487 }
488 
489 static char __read_mostly octeon_system_type[80];
490 
491 static void __init init_octeon_system_type(void)
492 {
493         char const *board_type;
494 
495         board_type = cvmx_board_type_to_string(octeon_bootinfo->board_type);
496         if (board_type == NULL) {
497                 struct device_node *root;
498                 int ret;
499 
500                 root = of_find_node_by_path("/");
501                 ret = of_property_read_string(root, "model", &board_type);
502                 of_node_put(root);
503                 if (ret)
504                         board_type = "Unsupported Board";
505         }
506 
507         snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)",
508                  board_type, octeon_model_get_string(read_c0_prid()));
509 }
510 
511 /**
512  * Return a string representing the system type
513  *
514  * Returns
515  */
516 const char *octeon_board_type_string(void)
517 {
518         return octeon_system_type;
519 }
520 
521 const char *get_system_type(void)
522         __attribute__ ((alias("octeon_board_type_string")));
523 
524 void octeon_user_io_init(void)
525 {
526         union octeon_cvmemctl cvmmemctl;
527 
528         /* Get the current settings for CP0_CVMMEMCTL_REG */
529         cvmmemctl.u64 = read_c0_cvmmemctl();
530         /* R/W If set, marked write-buffer entries time out the same
531          * as as other entries; if clear, marked write-buffer entries
532          * use the maximum timeout. */
533         cvmmemctl.s.dismarkwblongto = 1;
534         /* R/W If set, a merged store does not clear the write-buffer
535          * entry timeout state. */
536         cvmmemctl.s.dismrgclrwbto = 0;
537         /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
538          * word location for an IOBDMA. The other 8 bits come from the
539          * SCRADDR field of the IOBDMA. */
540         cvmmemctl.s.iobdmascrmsb = 0;
541         /* R/W If set, SYNCWS and SYNCS only order marked stores; if
542          * clear, SYNCWS and SYNCS only order unmarked
543          * stores. SYNCWSMARKED has no effect when DISSYNCWS is
544          * set. */
545         cvmmemctl.s.syncwsmarked = 0;
546         /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
547         cvmmemctl.s.dissyncws = 0;
548         /* R/W If set, no stall happens on write buffer full. */
549         if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
550                 cvmmemctl.s.diswbfst = 1;
551         else
552                 cvmmemctl.s.diswbfst = 0;
553         /* R/W If set (and SX set), supervisor-level loads/stores can
554          * use XKPHYS addresses with <48>==0 */
555         cvmmemctl.s.xkmemenas = 0;
556 
557         /* R/W If set (and UX set), user-level loads/stores can use
558          * XKPHYS addresses with VA<48>==0 */
559         cvmmemctl.s.xkmemenau = 0;
560 
561         /* R/W If set (and SX set), supervisor-level loads/stores can
562          * use XKPHYS addresses with VA<48>==1 */
563         cvmmemctl.s.xkioenas = 0;
564 
565         /* R/W If set (and UX set), user-level loads/stores can use
566          * XKPHYS addresses with VA<48>==1 */
567         cvmmemctl.s.xkioenau = 0;
568 
569         /* R/W If set, all stores act as SYNCW (NOMERGE must be set
570          * when this is set) RW, reset to 0. */
571         cvmmemctl.s.allsyncw = 0;
572 
573         /* R/W If set, no stores merge, and all stores reach the
574          * coherent bus in order. */
575         cvmmemctl.s.nomerge = 0;
576         /* R/W Selects the bit in the counter used for DID time-outs 0
577          * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
578          * between 1x and 2x this interval. For example, with
579          * DIDTTO=3, expiration interval is between 16K and 32K. */
580         cvmmemctl.s.didtto = 0;
581         /* R/W If set, the (mem) CSR clock never turns off. */
582         cvmmemctl.s.csrckalwys = 0;
583         /* R/W If set, mclk never turns off. */
584         cvmmemctl.s.mclkalwys = 0;
585         /* R/W Selects the bit in the counter used for write buffer
586          * flush time-outs (WBFLT+11) is the bit position in an
587          * internal counter used to determine expiration. The write
588          * buffer expires between 1x and 2x this interval. For
589          * example, with WBFLT = 0, a write buffer expires between 2K
590          * and 4K cycles after the write buffer entry is allocated. */
591         cvmmemctl.s.wbfltime = 0;
592         /* R/W If set, do not put Istream in the L2 cache. */
593         cvmmemctl.s.istrnol2 = 0;
594 
595         /*
596          * R/W The write buffer threshold. As per erratum Core-14752
597          * for CN63XX, a sc/scd might fail if the write buffer is
598          * full.  Lowering WBTHRESH greatly lowers the chances of the
599          * write buffer ever being full and triggering the erratum.
600          */
601         if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
602                 cvmmemctl.s.wbthresh = 4;
603         else
604                 cvmmemctl.s.wbthresh = 10;
605 
606         /* R/W If set, CVMSEG is available for loads/stores in
607          * kernel/debug mode. */
608 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
609         cvmmemctl.s.cvmsegenak = 1;
610 #else
611         cvmmemctl.s.cvmsegenak = 0;
612 #endif
613         /* R/W If set, CVMSEG is available for loads/stores in
614          * supervisor mode. */
615         cvmmemctl.s.cvmsegenas = 0;
616         /* R/W If set, CVMSEG is available for loads/stores in user
617          * mode. */
618         cvmmemctl.s.cvmsegenau = 0;
619 
620         write_c0_cvmmemctl(cvmmemctl.u64);
621 
622         /* Setup of CVMSEG is done in kernel-entry-init.h */
623         if (smp_processor_id() == 0)
624                 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
625                           CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
626                           CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
627 
628         if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
629                 union cvmx_iob_fau_timeout fau_timeout;
630 
631                 /* Set a default for the hardware timeouts */
632                 fau_timeout.u64 = 0;
633                 fau_timeout.s.tout_val = 0xfff;
634                 /* Disable tagwait FAU timeout */
635                 fau_timeout.s.tout_enb = 0;
636                 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
637         }
638 
639         if ((!OCTEON_IS_MODEL(OCTEON_CN68XX) &&
640              !OCTEON_IS_MODEL(OCTEON_CN7XXX)) ||
641             OCTEON_IS_MODEL(OCTEON_CN70XX)) {
642                 union cvmx_pow_nw_tim nm_tim;
643 
644                 nm_tim.u64 = 0;
645                 /* 4096 cycles */
646                 nm_tim.s.nw_tim = 3;
647                 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
648         }
649 
650         write_octeon_c0_icacheerr(0);
651         write_c0_derraddr1(0);
652 }
653 
654 /**
655  * Early entry point for arch setup
656  */
657 void __init prom_init(void)
658 {
659         struct cvmx_sysinfo *sysinfo;
660         const char *arg;
661         char *p;
662         int i;
663         u64 t;
664         int argc;
665 #ifdef CONFIG_CAVIUM_RESERVE32
666         int64_t addr = -1;
667 #endif
668         /*
669          * The bootloader passes a pointer to the boot descriptor in
670          * $a3, this is available as fw_arg3.
671          */
672         octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
673         octeon_bootinfo =
674                 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
675         cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
676 
677         sysinfo = cvmx_sysinfo_get();
678         memset(sysinfo, 0, sizeof(*sysinfo));
679         sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
680         sysinfo->phy_mem_desc_addr = (u64)phys_to_virt(octeon_bootinfo->phy_mem_desc_addr);
681 
682         if ((octeon_bootinfo->major_version > 1) ||
683             (octeon_bootinfo->major_version == 1 &&
684              octeon_bootinfo->minor_version >= 4))
685                 cvmx_coremask_copy(&sysinfo->core_mask,
686                                    &octeon_bootinfo->ext_core_mask);
687         else
688                 cvmx_coremask_set64(&sysinfo->core_mask,
689                                     octeon_bootinfo->core_mask);
690 
691         /* Some broken u-boot pass garbage in upper bits, clear them out */
692         if (!OCTEON_IS_MODEL(OCTEON_CN78XX))
693                 for (i = 512; i < 1024; i++)
694                         cvmx_coremask_clear_core(&sysinfo->core_mask, i);
695 
696         sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
697         sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
698         sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
699         sysinfo->board_type = octeon_bootinfo->board_type;
700         sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
701         sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
702         memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
703                sizeof(sysinfo->mac_addr_base));
704         sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
705         memcpy(sysinfo->board_serial_number,
706                octeon_bootinfo->board_serial_number,
707                sizeof(sysinfo->board_serial_number));
708         sysinfo->compact_flash_common_base_addr =
709                 octeon_bootinfo->compact_flash_common_base_addr;
710         sysinfo->compact_flash_attribute_base_addr =
711                 octeon_bootinfo->compact_flash_attribute_base_addr;
712         sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
713         sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
714         sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
715 
716         if (OCTEON_IS_OCTEON2()) {
717                 /* I/O clock runs at a different rate than the CPU. */
718                 union cvmx_mio_rst_boot rst_boot;
719                 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
720                 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
721         } else if (OCTEON_IS_OCTEON3()) {
722                 /* I/O clock runs at a different rate than the CPU. */
723                 union cvmx_rst_boot rst_boot;
724                 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
725                 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
726         } else {
727                 octeon_io_clock_rate = sysinfo->cpu_clock_hz;
728         }
729 
730         t = read_c0_cvmctl();
731         if ((t & (1ull << 27)) == 0) {
732                 /*
733                  * Setup the multiplier save/restore code if
734                  * CvmCtl[NOMUL] clear.
735                  */
736                 void *save;
737                 void *save_end;
738                 void *restore;
739                 void *restore_end;
740                 int save_len;
741                 int restore_len;
742                 int save_max = (char *)octeon_mult_save_end -
743                         (char *)octeon_mult_save;
744                 int restore_max = (char *)octeon_mult_restore_end -
745                         (char *)octeon_mult_restore;
746                 if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) {
747                         save = octeon_mult_save3;
748                         save_end = octeon_mult_save3_end;
749                         restore = octeon_mult_restore3;
750                         restore_end = octeon_mult_restore3_end;
751                 } else {
752                         save = octeon_mult_save2;
753                         save_end = octeon_mult_save2_end;
754                         restore = octeon_mult_restore2;
755                         restore_end = octeon_mult_restore2_end;
756                 }
757                 save_len = (char *)save_end - (char *)save;
758                 restore_len = (char *)restore_end - (char *)restore;
759                 if (!WARN_ON(save_len > save_max ||
760                                 restore_len > restore_max)) {
761                         memcpy(octeon_mult_save, save, save_len);
762                         memcpy(octeon_mult_restore, restore, restore_len);
763                 }
764         }
765 
766         /*
767          * Only enable the LED controller if we're running on a CN38XX, CN58XX,
768          * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
769          */
770         if (!octeon_is_simulation() &&
771             octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
772                 cvmx_write_csr(CVMX_LED_EN, 0);
773                 cvmx_write_csr(CVMX_LED_PRT, 0);
774                 cvmx_write_csr(CVMX_LED_DBG, 0);
775                 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
776                 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
777                 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
778                 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
779                 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
780                 cvmx_write_csr(CVMX_LED_EN, 1);
781         }
782 #ifdef CONFIG_CAVIUM_RESERVE32
783         /*
784          * We need to temporarily allocate all memory in the reserve32
785          * region. This makes sure the kernel doesn't allocate this
786          * memory when it is getting memory from the
787          * bootloader. Later, after the memory allocations are
788          * complete, the reserve32 will be freed.
789          *
790          * Allocate memory for RESERVED32 aligned on 2MB boundary. This
791          * is in case we later use hugetlb entries with it.
792          */
793         addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
794                                                 0, 0, 2 << 20,
795                                                 "CAVIUM_RESERVE32", 0);
796         if (addr < 0)
797                 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
798         else
799                 octeon_reserve32_memory = addr;
800 #endif
801 
802 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
803         if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
804                 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
805         } else {
806                 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
807 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
808                 /* TLB refill */
809                 cvmx_l2c_lock_mem_region(ebase, 0x100);
810 #endif
811 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
812                 /* General exception */
813                 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
814 #endif
815 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
816                 /* Interrupt handler */
817                 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
818 #endif
819 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
820                 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
821                 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
822 #endif
823 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
824                 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
825 #endif
826         }
827 #endif
828 
829         octeon_check_cpu_bist();
830 
831         octeon_uart = octeon_get_boot_uart();
832 
833 #ifdef CONFIG_SMP
834         octeon_write_lcd("LinuxSMP");
835 #else
836         octeon_write_lcd("Linux");
837 #endif
838 
839         octeon_setup_delays();
840 
841         /*
842          * BIST should always be enabled when doing a soft reset. L2
843          * Cache locking for instance is not cleared unless BIST is
844          * enabled.  Unfortunately due to a chip errata G-200 for
845          * Cn38XX and CN31XX, BIST msut be disabled on these parts.
846          */
847         if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
848             OCTEON_IS_MODEL(OCTEON_CN31XX))
849                 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
850         else
851                 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
852 
853         /* Default to 64MB in the simulator to speed things up */
854         if (octeon_is_simulation())
855                 max_memory = 64ull << 20;
856 
857         arg = strstr(arcs_cmdline, "mem=");
858         if (arg) {
859                 max_memory = memparse(arg + 4, &p);
860                 if (max_memory == 0)
861                         max_memory = 32ull << 30;
862                 if (*p == '@')
863                         reserve_low_mem = memparse(p + 1, &p);
864         }
865 
866         arcs_cmdline[0] = 0;
867         argc = octeon_boot_desc_ptr->argc;
868         for (i = 0; i < argc; i++) {
869                 const char *arg =
870                         cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
871                 if ((strncmp(arg, "MEM=", 4) == 0) ||
872                     (strncmp(arg, "mem=", 4) == 0)) {
873                         max_memory = memparse(arg + 4, &p);
874                         if (max_memory == 0)
875                                 max_memory = 32ull << 30;
876                         if (*p == '@')
877                                 reserve_low_mem = memparse(p + 1, &p);
878 #ifdef CONFIG_KEXEC
879                 } else if (strncmp(arg, "crashkernel=", 12) == 0) {
880                         crashk_size = memparse(arg+12, &p);
881                         if (*p == '@')
882                                 crashk_base = memparse(p+1, &p);
883                         strcat(arcs_cmdline, " ");
884                         strcat(arcs_cmdline, arg);
885                         /*
886                          * To do: switch parsing to new style, something like:
887                          * parse_crashkernel(arg, sysinfo->system_dram_size,
888                          *                &crashk_size, &crashk_base);
889                          */
890 #endif
891                 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
892                            sizeof(arcs_cmdline) - 1) {
893                         strcat(arcs_cmdline, " ");
894                         strcat(arcs_cmdline, arg);
895                 }
896         }
897 
898         if (strstr(arcs_cmdline, "console=") == NULL) {
899                 if (octeon_uart == 1)
900                         strcat(arcs_cmdline, " console=ttyS1,115200");
901                 else
902                         strcat(arcs_cmdline, " console=ttyS0,115200");
903         }
904 
905         mips_hpt_frequency = octeon_get_clock_rate();
906 
907         octeon_init_cvmcount();
908 
909         _machine_restart = octeon_restart;
910         _machine_halt = octeon_halt;
911 
912 #ifdef CONFIG_KEXEC
913         _machine_kexec_shutdown = octeon_shutdown;
914         _machine_crash_shutdown = octeon_crash_shutdown;
915         _machine_kexec_prepare = octeon_kexec_prepare;
916 #ifdef CONFIG_SMP
917         _crash_smp_send_stop = octeon_crash_smp_send_stop;
918 #endif
919 #endif
920 
921         octeon_user_io_init();
922         octeon_setup_smp();
923 }
924 
925 /* Exclude a single page from the regions obtained in plat_mem_setup. */
926 #ifndef CONFIG_CRASH_DUMP
927 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
928 {
929         if (addr > *mem && addr < *mem + *size) {
930                 u64 inc = addr - *mem;
931                 add_memory_region(*mem, inc, BOOT_MEM_RAM);
932                 *mem += inc;
933                 *size -= inc;
934         }
935 
936         if (addr == *mem && *size > PAGE_SIZE) {
937                 *mem += PAGE_SIZE;
938                 *size -= PAGE_SIZE;
939         }
940 }
941 #endif /* CONFIG_CRASH_DUMP */
942 
943 void __init fw_init_cmdline(void)
944 {
945         int i;
946 
947         octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
948         for (i = 0; i < octeon_boot_desc_ptr->argc; i++) {
949                 const char *arg =
950                         cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
951                 if (strlen(arcs_cmdline) + strlen(arg) + 1 <
952                            sizeof(arcs_cmdline) - 1) {
953                         strcat(arcs_cmdline, " ");
954                         strcat(arcs_cmdline, arg);
955                 }
956         }
957 }
958 
959 void __init *plat_get_fdt(void)
960 {
961         octeon_bootinfo =
962                 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
963         return phys_to_virt(octeon_bootinfo->fdt_addr);
964 }
965 
966 void __init plat_mem_setup(void)
967 {
968         uint64_t mem_alloc_size;
969         uint64_t total;
970         uint64_t crashk_end;
971 #ifndef CONFIG_CRASH_DUMP
972         int64_t memory;
973         uint64_t kernel_start;
974         uint64_t kernel_size;
975 #endif
976 
977         total = 0;
978         crashk_end = 0;
979 
980         /*
981          * The Mips memory init uses the first memory location for
982          * some memory vectors. When SPARSEMEM is in use, it doesn't
983          * verify that the size is big enough for the final
984          * vectors. Making the smallest chuck 4MB seems to be enough
985          * to consistently work.
986          */
987         mem_alloc_size = 4 << 20;
988         if (mem_alloc_size > max_memory)
989                 mem_alloc_size = max_memory;
990 
991 /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */
992 #ifdef CONFIG_CRASH_DUMP
993         add_memory_region(reserve_low_mem, max_memory, BOOT_MEM_RAM);
994         total += max_memory;
995 #else
996 #ifdef CONFIG_KEXEC
997         if (crashk_size > 0) {
998                 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM);
999                 crashk_end = crashk_base + crashk_size;
1000         }
1001 #endif
1002         /*
1003          * When allocating memory, we want incrementing addresses from
1004          * bootmem_alloc so the code in add_memory_region can merge
1005          * regions next to each other.
1006          */
1007         cvmx_bootmem_lock();
1008         while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
1009                 && (total < max_memory)) {
1010                 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
1011                                                 __pa_symbol(&_end), -1,
1012                                                 0x100000,
1013                                                 CVMX_BOOTMEM_FLAG_NO_LOCKING);
1014                 if (memory >= 0) {
1015                         u64 size = mem_alloc_size;
1016 #ifdef CONFIG_KEXEC
1017                         uint64_t end;
1018 #endif
1019 
1020                         /*
1021                          * exclude a page at the beginning and end of
1022                          * the 256MB PCIe 'hole' so the kernel will not
1023                          * try to allocate multi-page buffers that
1024                          * span the discontinuity.
1025                          */
1026                         memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
1027                                             &memory, &size);
1028                         memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
1029                                             CVMX_PCIE_BAR1_PHYS_SIZE,
1030                                             &memory, &size);
1031 #ifdef CONFIG_KEXEC
1032                         end = memory + mem_alloc_size;
1033 
1034                         /*
1035                          * This function automatically merges address regions
1036                          * next to each other if they are received in
1037                          * incrementing order
1038                          */
1039                         if (memory < crashk_base && end >  crashk_end) {
1040                                 /* region is fully in */
1041                                 add_memory_region(memory,
1042                                                   crashk_base - memory,
1043                                                   BOOT_MEM_RAM);
1044                                 total += crashk_base - memory;
1045                                 add_memory_region(crashk_end,
1046                                                   end - crashk_end,
1047                                                   BOOT_MEM_RAM);
1048                                 total += end - crashk_end;
1049                                 continue;
1050                         }
1051 
1052                         if (memory >= crashk_base && end <= crashk_end)
1053                                 /*
1054                                  * Entire memory region is within the new
1055                                  *  kernel's memory, ignore it.
1056                                  */
1057                                 continue;
1058 
1059                         if (memory > crashk_base && memory < crashk_end &&
1060                             end > crashk_end) {
1061                                 /*
1062                                  * Overlap with the beginning of the region,
1063                                  * reserve the beginning.
1064                                   */
1065                                 mem_alloc_size -= crashk_end - memory;
1066                                 memory = crashk_end;
1067                         } else if (memory < crashk_base && end > crashk_base &&
1068                                    end < crashk_end)
1069                                 /*
1070                                  * Overlap with the beginning of the region,
1071                                  * chop of end.
1072                                  */
1073                                 mem_alloc_size -= end - crashk_base;
1074 #endif
1075                         add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
1076                         total += mem_alloc_size;
1077                         /* Recovering mem_alloc_size */
1078                         mem_alloc_size = 4 << 20;
1079                 } else {
1080                         break;
1081                 }
1082         }
1083         cvmx_bootmem_unlock();
1084         /* Add the memory region for the kernel. */
1085         kernel_start = (unsigned long) _text;
1086         kernel_size = _end - _text;
1087 
1088         /* Adjust for physical offset. */
1089         kernel_start &= ~0xffffffff80000000ULL;
1090         add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM);
1091 #endif /* CONFIG_CRASH_DUMP */
1092 
1093 #ifdef CONFIG_CAVIUM_RESERVE32
1094         /*
1095          * Now that we've allocated the kernel memory it is safe to
1096          * free the reserved region. We free it here so that builtin
1097          * drivers can use the memory.
1098          */
1099         if (octeon_reserve32_memory)
1100                 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
1101 #endif /* CONFIG_CAVIUM_RESERVE32 */
1102 
1103         if (total == 0)
1104                 panic("Unable to allocate memory from "
1105                       "cvmx_bootmem_phy_alloc");
1106 }
1107 
1108 /*
1109  * Emit one character to the boot UART.  Exported for use by the
1110  * watchdog timer.
1111  */
1112 void prom_putchar(char c)
1113 {
1114         uint64_t lsrval;
1115 
1116         /* Spin until there is room */
1117         do {
1118                 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
1119         } while ((lsrval & 0x20) == 0);
1120 
1121         /* Write the byte */
1122         cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
1123 }
1124 EXPORT_SYMBOL(prom_putchar);
1125 
1126 void __init prom_free_prom_memory(void)
1127 {
1128         if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
1129                 /* Check for presence of Core-14449 fix.  */
1130                 u32 insn;
1131                 u32 *foo;
1132 
1133                 foo = &insn;
1134 
1135                 asm volatile("# before" : : : "memory");
1136                 prefetch(foo);
1137                 asm volatile(
1138                         ".set push\n\t"
1139                         ".set noreorder\n\t"
1140                         "bal 1f\n\t"
1141                         "nop\n"
1142                         "1:\tlw %0,-12($31)\n\t"
1143                         ".set pop\n\t"
1144                         : "=r" (insn) : : "$31", "memory");
1145 
1146                 if ((insn >> 26) != 0x33)
1147                         panic("No PREF instruction at Core-14449 probe point.");
1148 
1149                 if (((insn >> 16) & 0x1f) != 28)
1150                         panic("OCTEON II DCache prefetch workaround not in place (%04x).\n"
1151                               "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).",
1152                               insn);
1153         }
1154 }
1155 
1156 void __init octeon_fill_mac_addresses(void);
1157 
1158 void __init device_tree_init(void)
1159 {
1160         const void *fdt;
1161         bool do_prune;
1162         bool fill_mac;
1163 
1164         if (fw_passed_dtb) {
1165                 fdt = (void *)fw_passed_dtb;
1166                 do_prune = false;
1167                 fill_mac = true;
1168                 pr_info("Using appended Device Tree.\n");
1169         } else if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
1170                 fdt = phys_to_virt(octeon_bootinfo->fdt_addr);
1171                 if (fdt_check_header(fdt))
1172                         panic("Corrupt Device Tree passed to kernel.");
1173                 do_prune = false;
1174                 fill_mac = false;
1175                 pr_info("Using passed Device Tree.\n");
1176         } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
1177                 fdt = &__dtb_octeon_68xx_begin;
1178                 do_prune = true;
1179                 fill_mac = true;
1180         } else {
1181                 fdt = &__dtb_octeon_3xxx_begin;
1182                 do_prune = true;
1183                 fill_mac = true;
1184         }
1185 
1186         initial_boot_params = (void *)fdt;
1187 
1188         if (do_prune) {
1189                 octeon_prune_device_tree();
1190                 pr_info("Using internal Device Tree.\n");
1191         }
1192         if (fill_mac)
1193                 octeon_fill_mac_addresses();
1194         unflatten_and_copy_device_tree();
1195         init_octeon_system_type();
1196 }
1197 
1198 static int __initdata disable_octeon_edac_p;
1199 
1200 static int __init disable_octeon_edac(char *str)
1201 {
1202         disable_octeon_edac_p = 1;
1203         return 0;
1204 }
1205 early_param("disable_octeon_edac", disable_octeon_edac);
1206 
1207 static char *edac_device_names[] = {
1208         "octeon_l2c_edac",
1209         "octeon_pc_edac",
1210 };
1211 
1212 static int __init edac_devinit(void)
1213 {
1214         struct platform_device *dev;
1215         int i, err = 0;
1216         int num_lmc;
1217         char *name;
1218 
1219         if (disable_octeon_edac_p)
1220                 return 0;
1221 
1222         for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) {
1223                 name = edac_device_names[i];
1224                 dev = platform_device_register_simple(name, -1, NULL, 0);
1225                 if (IS_ERR(dev)) {
1226                         pr_err("Registration of %s failed!\n", name);
1227                         err = PTR_ERR(dev);
1228                 }
1229         }
1230 
1231         num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 :
1232                 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1);
1233         for (i = 0; i < num_lmc; i++) {
1234                 dev = platform_device_register_simple("octeon_lmc_edac",
1235                                                       i, NULL, 0);
1236                 if (IS_ERR(dev)) {
1237                         pr_err("Registration of octeon_lmc_edac %d failed!\n", i);
1238                         err = PTR_ERR(dev);
1239                 }
1240         }
1241 
1242         return err;
1243 }
1244 device_initcall(edac_devinit);
1245 
1246 static void __initdata *octeon_dummy_iospace;
1247 
1248 static int __init octeon_no_pci_init(void)
1249 {
1250         /*
1251          * Initially assume there is no PCI. The PCI/PCIe platform code will
1252          * later re-initialize these to correct values if they are present.
1253          */
1254         octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT);
1255         set_io_port_base((unsigned long)octeon_dummy_iospace);
1256         ioport_resource.start = MAX_RESOURCE;
1257         ioport_resource.end = 0;
1258         return 0;
1259 }
1260 core_initcall(octeon_no_pci_init);
1261 
1262 static int __init octeon_no_pci_release(void)
1263 {
1264         /*
1265          * Release the allocated memory if a real IO space is there.
1266          */
1267         if ((unsigned long)octeon_dummy_iospace != mips_io_port_base)
1268                 vfree(octeon_dummy_iospace);
1269         return 0;
1270 }
1271 late_initcall(octeon_no_pci_release);
1272 

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