~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/arch/mips/cavium-octeon/smp.c

Version: ~ [ linux-6.0-rc1 ] ~ [ linux-5.19.1 ] ~ [ linux-5.18.17 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.60 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.136 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.210 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.255 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.290 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.325 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.302 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.9 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
  7  */
  8 #include <linux/cpu.h>
  9 #include <linux/delay.h>
 10 #include <linux/smp.h>
 11 #include <linux/interrupt.h>
 12 #include <linux/kernel_stat.h>
 13 #include <linux/sched.h>
 14 #include <linux/module.h>
 15 
 16 #include <asm/mmu_context.h>
 17 #include <asm/time.h>
 18 #include <asm/setup.h>
 19 
 20 #include <asm/octeon/octeon.h>
 21 
 22 #include "octeon_boot.h"
 23 
 24 volatile unsigned long octeon_processor_boot = 0xff;
 25 volatile unsigned long octeon_processor_sp;
 26 volatile unsigned long octeon_processor_gp;
 27 
 28 #ifdef CONFIG_HOTPLUG_CPU
 29 uint64_t octeon_bootloader_entry_addr;
 30 EXPORT_SYMBOL(octeon_bootloader_entry_addr);
 31 #endif
 32 
 33 static void octeon_icache_flush(void)
 34 {
 35         asm volatile ("synci 0($0)\n");
 36 }
 37 
 38 static void (*octeon_message_functions[8])(void) = {
 39         scheduler_ipi,
 40         generic_smp_call_function_interrupt,
 41         octeon_icache_flush,
 42 };
 43 
 44 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
 45 {
 46         u64 mbox_clrx = CVMX_CIU_MBOX_CLRX(cvmx_get_core_num());
 47         u64 action;
 48         int i;
 49 
 50         /*
 51          * Make sure the function array initialization remains
 52          * correct.
 53          */
 54         BUILD_BUG_ON(SMP_RESCHEDULE_YOURSELF != (1 << 0));
 55         BUILD_BUG_ON(SMP_CALL_FUNCTION       != (1 << 1));
 56         BUILD_BUG_ON(SMP_ICACHE_FLUSH        != (1 << 2));
 57 
 58         /*
 59          * Load the mailbox register to figure out what we're supposed
 60          * to do.
 61          */
 62         action = cvmx_read_csr(mbox_clrx);
 63 
 64         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
 65                 action &= 0xff;
 66         else
 67                 action &= 0xffff;
 68 
 69         /* Clear the mailbox to clear the interrupt */
 70         cvmx_write_csr(mbox_clrx, action);
 71 
 72         for (i = 0; i < ARRAY_SIZE(octeon_message_functions) && action;) {
 73                 if (action & 1) {
 74                         void (*fn)(void) = octeon_message_functions[i];
 75 
 76                         if (fn)
 77                                 fn();
 78                 }
 79                 action >>= 1;
 80                 i++;
 81         }
 82         return IRQ_HANDLED;
 83 }
 84 
 85 /**
 86  * Cause the function described by call_data to be executed on the passed
 87  * cpu.  When the function has finished, increment the finished field of
 88  * call_data.
 89  */
 90 void octeon_send_ipi_single(int cpu, unsigned int action)
 91 {
 92         int coreid = cpu_logical_map(cpu);
 93         /*
 94         pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
 95                coreid, action);
 96         */
 97         cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
 98 }
 99 
100 static inline void octeon_send_ipi_mask(const struct cpumask *mask,
101                                         unsigned int action)
102 {
103         unsigned int i;
104 
105         for_each_cpu(i, mask)
106                 octeon_send_ipi_single(i, action);
107 }
108 
109 /**
110  * Detect available CPUs, populate cpu_possible_mask
111  */
112 static void octeon_smp_hotplug_setup(void)
113 {
114 #ifdef CONFIG_HOTPLUG_CPU
115         struct linux_app_boot_info *labi;
116 
117         if (!setup_max_cpus)
118                 return;
119 
120         labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
121         if (labi->labi_signature != LABI_SIGNATURE) {
122                 pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
123                 return;
124         }
125 
126         octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
127 #endif
128 }
129 
130 static void __init octeon_smp_setup(void)
131 {
132         const int coreid = cvmx_get_core_num();
133         int cpus;
134         int id;
135         struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
136 
137 #ifdef CONFIG_HOTPLUG_CPU
138         int core_mask = octeon_get_boot_coremask();
139         unsigned int num_cores = cvmx_octeon_num_cores();
140 #endif
141 
142         /* The present CPUs are initially just the boot cpu (CPU 0). */
143         for (id = 0; id < NR_CPUS; id++) {
144                 set_cpu_possible(id, id == 0);
145                 set_cpu_present(id, id == 0);
146         }
147 
148         __cpu_number_map[coreid] = 0;
149         __cpu_logical_map[0] = coreid;
150 
151         /* The present CPUs get the lowest CPU numbers. */
152         cpus = 1;
153         for (id = 0; id < NR_CPUS; id++) {
154                 if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) {
155                         set_cpu_possible(cpus, true);
156                         set_cpu_present(cpus, true);
157                         __cpu_number_map[id] = cpus;
158                         __cpu_logical_map[cpus] = id;
159                         cpus++;
160                 }
161         }
162 
163 #ifdef CONFIG_HOTPLUG_CPU
164         /*
165          * The possible CPUs are all those present on the chip.  We
166          * will assign CPU numbers for possible cores as well.  Cores
167          * are always consecutively numberd from 0.
168          */
169         for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr &&
170                      id < num_cores && id < NR_CPUS; id++) {
171                 if (!(core_mask & (1 << id))) {
172                         set_cpu_possible(cpus, true);
173                         __cpu_number_map[id] = cpus;
174                         __cpu_logical_map[cpus] = id;
175                         cpus++;
176                 }
177         }
178 #endif
179 
180         octeon_smp_hotplug_setup();
181 }
182 
183 /**
184  * Firmware CPU startup hook
185  *
186  */
187 static void octeon_boot_secondary(int cpu, struct task_struct *idle)
188 {
189         int count;
190 
191         pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
192                 cpu_logical_map(cpu));
193 
194         octeon_processor_sp = __KSTK_TOS(idle);
195         octeon_processor_gp = (unsigned long)(task_thread_info(idle));
196         octeon_processor_boot = cpu_logical_map(cpu);
197         mb();
198 
199         count = 10000;
200         while (octeon_processor_sp && count) {
201                 /* Waiting for processor to get the SP and GP */
202                 udelay(1);
203                 count--;
204         }
205         if (count == 0)
206                 pr_err("Secondary boot timeout\n");
207 }
208 
209 /**
210  * After we've done initial boot, this function is called to allow the
211  * board code to clean up state, if needed
212  */
213 static void octeon_init_secondary(void)
214 {
215         unsigned int sr;
216 
217         sr = set_c0_status(ST0_BEV);
218         write_c0_ebase((u32)ebase);
219         write_c0_status(sr);
220 
221         octeon_check_cpu_bist();
222         octeon_init_cvmcount();
223 
224         octeon_irq_setup_secondary();
225 }
226 
227 /**
228  * Callout to firmware before smp_init
229  *
230  */
231 static void __init octeon_prepare_cpus(unsigned int max_cpus)
232 {
233         /*
234          * Only the low order mailbox bits are used for IPIs, leave
235          * the other bits alone.
236          */
237         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
238         if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
239                         IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
240                         mailbox_interrupt)) {
241                 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
242         }
243 }
244 
245 /**
246  * Last chance for the board code to finish SMP initialization before
247  * the CPU is "online".
248  */
249 static void octeon_smp_finish(void)
250 {
251         octeon_user_io_init();
252 
253         /* to generate the first CPU timer interrupt */
254         write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
255         local_irq_enable();
256 }
257 
258 #ifdef CONFIG_HOTPLUG_CPU
259 
260 /* State of each CPU. */
261 DEFINE_PER_CPU(int, cpu_state);
262 
263 static int octeon_cpu_disable(void)
264 {
265         unsigned int cpu = smp_processor_id();
266 
267         if (cpu == 0)
268                 return -EBUSY;
269 
270         if (!octeon_bootloader_entry_addr)
271                 return -ENOTSUPP;
272 
273         set_cpu_online(cpu, false);
274         calculate_cpu_foreign_map();
275         cpumask_clear_cpu(cpu, &cpu_callin_map);
276         octeon_fixup_irqs();
277 
278         __flush_cache_all();
279         local_flush_tlb_all();
280 
281         return 0;
282 }
283 
284 static void octeon_cpu_die(unsigned int cpu)
285 {
286         int coreid = cpu_logical_map(cpu);
287         uint32_t mask, new_mask;
288         const struct cvmx_bootmem_named_block_desc *block_desc;
289 
290         while (per_cpu(cpu_state, cpu) != CPU_DEAD)
291                 cpu_relax();
292 
293         /*
294          * This is a bit complicated strategics of getting/settig available
295          * cores mask, copied from bootloader
296          */
297 
298         mask = 1 << coreid;
299         /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
300         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
301 
302         if (!block_desc) {
303                 struct linux_app_boot_info *labi;
304 
305                 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
306 
307                 labi->avail_coremask |= mask;
308                 new_mask = labi->avail_coremask;
309         } else {                       /* alternative, already initialized */
310                 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
311                                                                AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
312                 *p |= mask;
313                 new_mask = *p;
314         }
315 
316         pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
317         mb();
318         cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
319         cvmx_write_csr(CVMX_CIU_PP_RST, 0);
320 }
321 
322 void play_dead(void)
323 {
324         int cpu = cpu_number_map(cvmx_get_core_num());
325 
326         idle_task_exit();
327         octeon_processor_boot = 0xff;
328         per_cpu(cpu_state, cpu) = CPU_DEAD;
329 
330         mb();
331 
332         while (1)       /* core will be reset here */
333                 ;
334 }
335 
336 extern void kernel_entry(unsigned long arg1, ...);
337 
338 static void start_after_reset(void)
339 {
340         kernel_entry(0, 0, 0);  /* set a2 = 0 for secondary core */
341 }
342 
343 static int octeon_update_boot_vector(unsigned int cpu)
344 {
345 
346         int coreid = cpu_logical_map(cpu);
347         uint32_t avail_coremask;
348         const struct cvmx_bootmem_named_block_desc *block_desc;
349         struct boot_init_vector *boot_vect =
350                 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
351 
352         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
353 
354         if (!block_desc) {
355                 struct linux_app_boot_info *labi;
356 
357                 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
358 
359                 avail_coremask = labi->avail_coremask;
360                 labi->avail_coremask &= ~(1 << coreid);
361         } else {                       /* alternative, already initialized */
362                 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
363                         block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
364         }
365 
366         if (!(avail_coremask & (1 << coreid))) {
367                 /* core not available, assume, that caught by simple-executive */
368                 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
369                 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
370         }
371 
372         boot_vect[coreid].app_start_func_addr =
373                 (uint32_t) (unsigned long) start_after_reset;
374         boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
375 
376         mb();
377 
378         cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
379 
380         return 0;
381 }
382 
383 static int octeon_cpu_callback(struct notifier_block *nfb,
384         unsigned long action, void *hcpu)
385 {
386         unsigned int cpu = (unsigned long)hcpu;
387 
388         switch (action & ~CPU_TASKS_FROZEN) {
389         case CPU_UP_PREPARE:
390                 octeon_update_boot_vector(cpu);
391                 break;
392         case CPU_ONLINE:
393                 pr_info("Cpu %d online\n", cpu);
394                 break;
395         case CPU_DEAD:
396                 break;
397         }
398 
399         return NOTIFY_OK;
400 }
401 
402 static int register_cavium_notifier(void)
403 {
404         hotcpu_notifier(octeon_cpu_callback, 0);
405         return 0;
406 }
407 late_initcall(register_cavium_notifier);
408 
409 #endif  /* CONFIG_HOTPLUG_CPU */
410 
411 struct plat_smp_ops octeon_smp_ops = {
412         .send_ipi_single        = octeon_send_ipi_single,
413         .send_ipi_mask          = octeon_send_ipi_mask,
414         .init_secondary         = octeon_init_secondary,
415         .smp_finish             = octeon_smp_finish,
416         .boot_secondary         = octeon_boot_secondary,
417         .smp_setup              = octeon_smp_setup,
418         .prepare_cpus           = octeon_prepare_cpus,
419 #ifdef CONFIG_HOTPLUG_CPU
420         .cpu_disable            = octeon_cpu_disable,
421         .cpu_die                = octeon_cpu_die,
422 #endif
423 };
424 
425 static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id)
426 {
427         scheduler_ipi();
428         return IRQ_HANDLED;
429 }
430 
431 static irqreturn_t octeon_78xx_call_function_interrupt(int irq, void *dev_id)
432 {
433         generic_smp_call_function_interrupt();
434         return IRQ_HANDLED;
435 }
436 
437 static irqreturn_t octeon_78xx_icache_flush_interrupt(int irq, void *dev_id)
438 {
439         octeon_icache_flush();
440         return IRQ_HANDLED;
441 }
442 
443 /*
444  * Callout to firmware before smp_init
445  */
446 static void octeon_78xx_prepare_cpus(unsigned int max_cpus)
447 {
448         if (request_irq(OCTEON_IRQ_MBOX0 + 0,
449                         octeon_78xx_reched_interrupt,
450                         IRQF_PERCPU | IRQF_NO_THREAD, "Scheduler",
451                         octeon_78xx_reched_interrupt)) {
452                 panic("Cannot request_irq for SchedulerIPI");
453         }
454         if (request_irq(OCTEON_IRQ_MBOX0 + 1,
455                         octeon_78xx_call_function_interrupt,
456                         IRQF_PERCPU | IRQF_NO_THREAD, "SMP-Call",
457                         octeon_78xx_call_function_interrupt)) {
458                 panic("Cannot request_irq for SMP-Call");
459         }
460         if (request_irq(OCTEON_IRQ_MBOX0 + 2,
461                         octeon_78xx_icache_flush_interrupt,
462                         IRQF_PERCPU | IRQF_NO_THREAD, "ICache-Flush",
463                         octeon_78xx_icache_flush_interrupt)) {
464                 panic("Cannot request_irq for ICache-Flush");
465         }
466 }
467 
468 static void octeon_78xx_send_ipi_single(int cpu, unsigned int action)
469 {
470         int i;
471 
472         for (i = 0; i < 8; i++) {
473                 if (action & 1)
474                         octeon_ciu3_mbox_send(cpu, i);
475                 action >>= 1;
476         }
477 }
478 
479 static void octeon_78xx_send_ipi_mask(const struct cpumask *mask,
480                                       unsigned int action)
481 {
482         unsigned int cpu;
483 
484         for_each_cpu(cpu, mask)
485                 octeon_78xx_send_ipi_single(cpu, action);
486 }
487 
488 static struct plat_smp_ops octeon_78xx_smp_ops = {
489         .send_ipi_single        = octeon_78xx_send_ipi_single,
490         .send_ipi_mask          = octeon_78xx_send_ipi_mask,
491         .init_secondary         = octeon_init_secondary,
492         .smp_finish             = octeon_smp_finish,
493         .boot_secondary         = octeon_boot_secondary,
494         .smp_setup              = octeon_smp_setup,
495         .prepare_cpus           = octeon_78xx_prepare_cpus,
496 #ifdef CONFIG_HOTPLUG_CPU
497         .cpu_disable            = octeon_cpu_disable,
498         .cpu_die                = octeon_cpu_die,
499 #endif
500 };
501 
502 void __init octeon_setup_smp(void)
503 {
504         struct plat_smp_ops *ops;
505 
506         if (octeon_has_feature(OCTEON_FEATURE_CIU3))
507                 ops = &octeon_78xx_smp_ops;
508         else
509                 ops = &octeon_smp_ops;
510 
511         register_smp_ops(ops);
512 }
513 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp