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Linux/arch/mips/dec/kn02xa-berr.c

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  1 /*
  2  *      Bus error event handling code for 5000-series systems equipped
  3  *      with parity error detection logic, i.e. DECstation/DECsystem
  4  *      5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal
  5  *      DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50
  6  *      (KN04-CA) systems.
  7  *
  8  *      Copyright (c) 2005  Maciej W. Rozycki
  9  *
 10  *      This program is free software; you can redistribute it and/or
 11  *      modify it under the terms of the GNU General Public License
 12  *      as published by the Free Software Foundation; either version
 13  *      2 of the License, or (at your option) any later version.
 14  */
 15 
 16 #include <linux/init.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/kernel.h>
 19 #include <linux/types.h>
 20 
 21 #include <asm/addrspace.h>
 22 #include <asm/cpu-type.h>
 23 #include <asm/irq_regs.h>
 24 #include <asm/ptrace.h>
 25 #include <asm/traps.h>
 26 
 27 #include <asm/dec/kn02ca.h>
 28 #include <asm/dec/kn02xa.h>
 29 #include <asm/dec/kn05.h>
 30 
 31 static inline void dec_kn02xa_be_ack(void)
 32 {
 33         volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
 34         volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
 35 
 36         *mer = KN02CA_MER_INTR;         /* Clear errors; keep the ARC IRQ. */
 37         *mem_intr = 0;                  /* Any write clears the bus IRQ. */
 38         iob();
 39 }
 40 
 41 static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
 42                                  int invoker)
 43 {
 44         volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
 45         volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
 46 
 47         static const char excstr[] = "exception";
 48         static const char intstr[] = "interrupt";
 49         static const char cpustr[] = "CPU";
 50         static const char mreadstr[] = "memory read";
 51         static const char readstr[] = "read";
 52         static const char writestr[] = "write";
 53         static const char timestr[] = "timeout";
 54         static const char paritystr[] = "parity error";
 55         static const char lanestat[][4] = { " OK", "BAD" };
 56 
 57         const char *kind, *agent, *cycle, *event;
 58         unsigned long address;
 59 
 60         u32 mer = *kn02xa_mer;
 61         u32 ear = *kn02xa_ear;
 62         int action = MIPS_BE_FATAL;
 63 
 64         /* Ack ASAP, so that any subsequent errors get caught. */
 65         dec_kn02xa_be_ack();
 66 
 67         kind = invoker ? intstr : excstr;
 68 
 69         /* No DMA errors? */
 70         agent = cpustr;
 71 
 72         address = ear & KN02XA_EAR_ADDRESS;
 73 
 74         /* Low 256MB is decoded as memory, high -- as TC. */
 75         if (address < 0x10000000) {
 76                 cycle = mreadstr;
 77                 event = paritystr;
 78         } else {
 79                 cycle = invoker ? writestr : readstr;
 80                 event = timestr;
 81         }
 82 
 83         if (is_fixup)
 84                 action = MIPS_BE_FIXUP;
 85 
 86         if (action != MIPS_BE_FIXUP)
 87                 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
 88                         kind, agent, cycle, event, address);
 89 
 90         if (action != MIPS_BE_FIXUP && address < 0x10000000)
 91                 printk(KERN_ALERT "  Byte lane status %#3x -- "
 92                        "#3: %s, #2: %s, #1: %s, #0: %s\n",
 93                        (mer & KN02XA_MER_BYTERR) >> 8,
 94                        lanestat[(mer & KN02XA_MER_BYTERR_3) != 0],
 95                        lanestat[(mer & KN02XA_MER_BYTERR_2) != 0],
 96                        lanestat[(mer & KN02XA_MER_BYTERR_1) != 0],
 97                        lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]);
 98 
 99         return action;
100 }
101 
102 int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup)
103 {
104         return dec_kn02xa_be_backend(regs, is_fixup, 0);
105 }
106 
107 irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id)
108 {
109         struct pt_regs *regs = get_irq_regs();
110         int action = dec_kn02xa_be_backend(regs, 0, 1);
111 
112         if (action == MIPS_BE_DISCARD)
113                 return IRQ_HANDLED;
114 
115         /*
116          * FIXME: Find the affected processes and kill them, otherwise
117          * we must die.
118          *
119          * The interrupt is asynchronously delivered thus EPC and RA
120          * may be irrelevant, but are printed for a reference.
121          */
122         printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
123                regs->cp0_epc, regs->regs[31]);
124         die("Unrecoverable bus error", regs);
125 }
126 
127 
128 void __init dec_kn02xa_be_init(void)
129 {
130         volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
131 
132         /* For KN04 we need to make sure EE (?) is enabled in the MB.  */
133         if (current_cpu_type() == CPU_R4000SC)
134                 *mbcs |= KN4K_MB_CSR_EE;
135         fast_iob();
136 
137         /* Clear any leftover errors from the firmware. */
138         dec_kn02xa_be_ack();
139 }
140 

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