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Linux/arch/mips/gt64120/momenco_ocelot/setup.c

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  1 /*
  2  * setup.c
  3  *
  4  * BRIEF MODULE DESCRIPTION
  5  * Momentum Computer Ocelot (CP7000) - board dependent boot routines
  6  *
  7  * Copyright (C) 1996, 1997, 2001  Ralf Baechle
  8  * Copyright (C) 2000 RidgeRun, Inc.
  9  * Copyright (C) 2001 Red Hat, Inc.
 10  * Copyright (C) 2002 Momentum Computer
 11  *
 12  * Author: RidgeRun, Inc.
 13  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
 14  *
 15  * Copyright 2001 MontaVista Software Inc.
 16  * Author: jsun@mvista.com or jsun@junsun.net
 17  *
 18  *  This program is free software; you can redistribute  it and/or modify it
 19  *  under  the terms of  the GNU General  Public License as published by the
 20  *  Free Software Foundation;  either version 2 of the  License, or (at your
 21  *  option) any later version.
 22  *
 23  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 24  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 25  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 26  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 27  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 28  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 29  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 30  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 31  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 32  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33  *
 34  *  You should have received a copy of the  GNU General Public License along
 35  *  with this program; if not, write  to the Free Software Foundation, Inc.,
 36  *  675 Mass Ave, Cambridge, MA 02139, USA.
 37  *
 38  */
 39 #include <linux/init.h>
 40 #include <linux/kernel.h>
 41 #include <linux/types.h>
 42 #include <linux/mc146818rtc.h>
 43 #include <linux/mm.h>
 44 #include <linux/swap.h>
 45 #include <linux/ioport.h>
 46 #include <linux/sched.h>
 47 #include <linux/interrupt.h>
 48 #include <linux/pci.h>
 49 #include <linux/timex.h>
 50 #include <linux/vmalloc.h>
 51 #include <asm/time.h>
 52 #include <asm/bootinfo.h>
 53 #include <asm/page.h>
 54 #include <asm/bootinfo.h>
 55 #include <asm/io.h>
 56 #include <asm/irq.h>
 57 #include <asm/pci.h>
 58 #include <asm/processor.h>
 59 #include <asm/ptrace.h>
 60 #include <asm/reboot.h>
 61 #include <asm/mc146818rtc.h>
 62 #include <asm/traps.h>
 63 #include <linux/version.h>
 64 #include <linux/bootmem.h>
 65 #include <linux/initrd.h>
 66 #include <asm/gt64120/gt64120.h>
 67 #include "ocelot_pld.h"
 68 
 69 extern struct rtc_ops no_rtc_ops;
 70 
 71 unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE);
 72 
 73 /* These functions are used for rebooting or halting the machine*/
 74 extern void momenco_ocelot_restart(char *command);
 75 extern void momenco_ocelot_halt(void);
 76 extern void momenco_ocelot_power_off(void);
 77 
 78 extern void gt64120_time_init(void);
 79 extern void momenco_ocelot_irq_setup(void);
 80 
 81 static char reset_reason;
 82 
 83 #define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1)
 84 
 85 static void __init setup_l3cache(unsigned long size);
 86 
 87 /* setup code for a handoff from a version 1 PMON 2000 PROM */
 88 void PMON_v1_setup()
 89 {
 90         /* A wired TLB entry for the GT64120A and the serial port. The
 91            GT64120A is going to be hit on every IRQ anyway - there's
 92            absolutely no point in letting it be a random TLB entry, as
 93            it'll just cause needless churning of the TLB. And we use
 94            the other half for the serial port, which is just a PITA
 95            otherwise :)
 96 
 97                 Device                  Physical        Virtual
 98                 GT64120 Internal Regs   0x24000000      0xe0000000
 99                 UARTs (CS2)             0x2d000000      0xe0001000
100         */
101         add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K);
102 
103         /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
104            in the CS[012] region. We can't use ioremap() yet. The NVRAM
105            is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
106 
107                 Ocelot PLD (CS0)        0x2c000000      0xe0020000
108                 NVRAM                   0x2c800000      0xe0030000
109         */
110 
111         add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
112 
113         /* Relocate the CS3/BootCS region */
114         GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
115 
116         /* Relocate CS[012] */
117         GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21);
118 
119         /* Relocate the GT64120A itself... */
120         GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21);
121         mb();
122         gt64120_base = 0xe0000000;
123 
124         /* ...and the PCI0 view of it. */
125         GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020);
126         GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000);
127         GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024);
128         GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001);
129 }
130 
131 /* setup code for a handoff from a version 2 PMON 2000 PROM */
132 void PMON_v2_setup()
133 {
134         /* A wired TLB entry for the GT64120A and the serial port. The
135            GT64120A is going to be hit on every IRQ anyway - there's
136            absolutely no point in letting it be a random TLB entry, as
137            it'll just cause needless churning of the TLB. And we use
138            the other half for the serial port, which is just a PITA
139            otherwise :)
140 
141                 Device                  Physical        Virtual
142                 GT64120 Internal Regs   0xf4000000      0xe0000000
143                 UARTs (CS2)             0xfd000000      0xe0001000
144         */
145         add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K);
146 
147         /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
148            in the CS[012] region. We can't use ioremap() yet. The NVRAM
149            is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
150 
151                 Ocelot PLD (CS0)        0xfc000000      0xe0020000
152                 NVRAM                   0xfc800000      0xe0030000
153         */
154         add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K);
155 
156         gt64120_base = 0xe0000000;
157 }
158 
159 void __init momenco_ocelot_setup(void)
160 {
161         void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
162         unsigned int tmpword;
163 
164         board_time_init = gt64120_time_init;
165 
166         _machine_restart = momenco_ocelot_restart;
167         _machine_halt = momenco_ocelot_halt;
168         _machine_power_off = momenco_ocelot_power_off;
169 
170         /*
171          * initrd_start = (ulong)ocelot_initrd_start;
172          * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
173          * initrd_below_start_ok = 1;
174          */
175         rtc_ops = &no_rtc_ops;
176 
177         /* do handoff reconfiguration */
178         if (gt64120_base == KSEG1ADDR(GT_DEF_BASE))
179                 PMON_v1_setup();
180         else
181                 PMON_v2_setup();
182 
183         /* Turn off the Bit-Error LED */
184         OCELOT_PLD_WRITE(0x80, INTCLR);
185 
186         /* Relocate all the PCI1 stuff, not that we use it */
187         GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21);
188         GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
189         GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
190 
191         /* Relocate PCI0 I/O and Mem0 */
192         GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
193         GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
194 
195         /* Relocate PCI0 Mem1 */
196         GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
197 
198         /* For the initial programming, we assume 512MB configuration */
199         /* Relocate the CPU's view of the RAM... */
200         GT_WRITE(GT_SCS10LD_OFS, 0);
201         GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
202         GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21);
203         GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
204 
205         GT_WRITE(GT_SCS1LD_OFS, 0xff);
206         GT_WRITE(GT_SCS1HD_OFS, 0x00);
207         GT_WRITE(GT_SCS0LD_OFS, 0);
208         GT_WRITE(GT_SCS0HD_OFS, 0xff);
209         GT_WRITE(GT_SCS3LD_OFS, 0xff);
210         GT_WRITE(GT_SCS3HD_OFS, 0x00);
211         GT_WRITE(GT_SCS2LD_OFS, 0);
212         GT_WRITE(GT_SCS2HD_OFS, 0xff);
213 
214         /* ...and the PCI0 view of it. */
215         GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010);
216         GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000);
217         GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
218         GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000);
219         GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
220         GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
221 
222         tmpword = OCELOT_PLD_READ(BOARDREV);
223         if (tmpword < 26)
224                 printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword);
225         else
226                 printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword);
227 
228         tmpword = OCELOT_PLD_READ(PLD1_ID);
229         printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
230         tmpword = OCELOT_PLD_READ(PLD2_ID);
231         printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
232         tmpword = OCELOT_PLD_READ(RESET_STATUS);
233         printk("Reset reason: 0x%x\n", tmpword);
234         reset_reason = tmpword;
235         OCELOT_PLD_WRITE(0xff, RESET_STATUS);
236 
237         tmpword = OCELOT_PLD_READ(BOARD_STATUS);
238         printk("Board Status register: 0x%02x\n", tmpword);
239         printk("  - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
240         printk("  - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
241         printk("  - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
242         printk("  - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
243         printk("  - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
244 
245         if (tmpword&12)
246                 l3func((1<<(((tmpword&12) >> 2)+20)));
247 
248         switch(tmpword &3) {
249         case 3:
250                 /* 512MiB */
251                 /* Decoders are allready set -- just add the
252                  * appropriate region */
253                 add_memory_region( 0x40<<20,  0xC0<<20, BOOT_MEM_RAM);
254                 add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
255                 break;
256         case 2:
257                 /* 256MiB -- two banks of 128MiB */
258                 GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21);
259                 GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21);
260                 GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
261 
262                 GT_WRITE(GT_SCS0HD_OFS, 0x7f);
263                 GT_WRITE(GT_SCS2LD_OFS, 0x80);
264                 GT_WRITE(GT_SCS2HD_OFS, 0xff);
265 
266                 /* reconfigure the PCI0 interface view of memory */
267                 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
268                 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000);
269                 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
270                 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
271 
272                 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
273                 add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
274                 break;
275         case 1:
276                 /* 128MiB -- 64MiB per bank */
277                 GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21);
278                 GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21);
279                 GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21);
280 
281                 GT_WRITE(GT_SCS0HD_OFS, 0x3f);
282                 GT_WRITE(GT_SCS2LD_OFS, 0x40);
283                 GT_WRITE(GT_SCS2HD_OFS, 0x7f);
284 
285                 /* reconfigure the PCI0 interface view of memory */
286                 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
287                 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
288                 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000);
289                 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000);
290 
291                 /* add the appropriate region */
292                 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
293                 break;
294         case 0:
295                 /* 64MiB */
296                 GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21);
297                 GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21);
298                 GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21);
299 
300                 GT_WRITE(GT_SCS0HD_OFS, 0x1f);
301                 GT_WRITE(GT_SCS2LD_OFS, 0x20);
302                 GT_WRITE(GT_SCS2HD_OFS, 0x3f);
303 
304                 /* reconfigure the PCI0 interface view of memory */
305                 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
306                 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
307                 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000);
308                 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000);
309 
310                 break;
311         }
312 
313         /* Fix up the DiskOnChip mapping */
314         GT_WRITE(0x468, 0xfef73);
315 }
316 
317 extern int rm7k_tcache_enabled;
318 /*
319  * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
320  */
321 #define Page_Invalidate_T 0x16
322 static void __init setup_l3cache(unsigned long size)
323 {
324         int register i;
325         unsigned long tmp;
326 
327         printk("Enabling L3 cache...");
328 
329         /* Enable the L3 cache in the GT64120A's CPU Configuration register */
330         GT_READ(0, &tmp);
331         GT_WRITE(0, tmp | (1<<14));
332 
333         /* Enable the L3 cache in the CPU */
334         set_c0_config(1<<12 /* CONF_TE */);
335 
336         /* Clear the cache */
337         write_c0_taglo(0);
338         write_c0_taghi(0);
339 
340         for (i=0; i < size; i+= 4096) {
341                 __asm__ __volatile__ (
342                         ".set noreorder\n\t"
343                         ".set mips3\n\t"
344                         "cache %1, (%0)\n\t"
345                         ".set mips0\n\t"
346                         ".set reorder"
347                         :
348                         : "r" (KSEG0ADDR(i)),
349                           "i" (Page_Invalidate_T));
350         }
351 
352         /* Let the RM7000 MM code know that the tertiary cache is enabled */
353         rm7k_tcache_enabled = 1;
354 
355         printk("Done\n");
356 }
357 
358 
359 /* This needs to be one of the first initcalls, because no I/O port access
360    can work before this */
361 
362 static int io_base_ioremap(void)
363 {
364         void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE);
365 
366         if (!io_remap_range) {
367                 panic("Could not ioremap I/O port range");
368         }
369         set_io_port_base(io_remap_range - GT_PCI_IO_BASE);
370 
371         return 0;
372 }
373 
374 module_init(io_base_ioremap);
375 

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