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TOMOYO Linux Cross Reference
Linux/arch/mips/include/asm/gic.h

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  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  7  *
  8  * GIC Register Definitions
  9  *
 10  */
 11 #ifndef _ASM_GICREGS_H
 12 #define _ASM_GICREGS_H
 13 
 14 #undef  GICISBYTELITTLEENDIAN
 15 
 16 /* Constants */
 17 #define GIC_POL_POS                     1
 18 #define GIC_POL_NEG                     0
 19 #define GIC_TRIG_EDGE                   1
 20 #define GIC_TRIG_LEVEL                  0
 21 
 22 #define GIC_NUM_INTRS                   (24 + NR_CPUS * 2)
 23 
 24 #define MSK(n) ((1 << (n)) - 1)
 25 #define REG32(addr)             (*(volatile unsigned int *) (addr))
 26 #define REG(base, offs)         REG32((unsigned long)(base) + offs##_##OFS)
 27 #define REGP(base, phys)        REG32((unsigned long)(base) + (phys))
 28 
 29 /* Accessors */
 30 #define GIC_REG(segment, offset) \
 31         REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
 32 #define GIC_REG_ADDR(segment, offset) \
 33         REG32(_gic_base + segment##_##SECTION_OFS + offset)
 34 
 35 #define GIC_ABS_REG(segment, offset) \
 36         (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
 37 #define GIC_REG_ABS_ADDR(segment, offset) \
 38         (_gic_base + segment##_##SECTION_OFS + offset)
 39 
 40 #ifdef GICISBYTELITTLEENDIAN
 41 #define GICREAD(reg, data)      ((data) = (reg), (data) = le32_to_cpu(data))
 42 #define GICWRITE(reg, data)     ((reg) = cpu_to_le32(data))
 43 #define GICBIS(reg, bits)                       \
 44         ({unsigned int data;                    \
 45                 GICREAD(reg, data);             \
 46                 data |= bits;                   \
 47                 GICWRITE(reg, data);            \
 48         })
 49 
 50 #else
 51 #define GICREAD(reg, data)      ((data) = (reg))
 52 #define GICWRITE(reg, data)     ((reg) = (data))
 53 #define GICBIS(reg, bits)       ((reg) |= (bits))
 54 #endif
 55 
 56 
 57 /* GIC Address Space */
 58 #define SHARED_SECTION_OFS              0x0000
 59 #define SHARED_SECTION_SIZE             0x8000
 60 #define VPE_LOCAL_SECTION_OFS           0x8000
 61 #define VPE_LOCAL_SECTION_SIZE          0x4000
 62 #define VPE_OTHER_SECTION_OFS           0xc000
 63 #define VPE_OTHER_SECTION_SIZE          0x4000
 64 #define USM_VISIBLE_SECTION_OFS         0x10000
 65 #define USM_VISIBLE_SECTION_SIZE        0x10000
 66 
 67 /* Register Map for Shared Section */
 68 
 69 #define GIC_SH_CONFIG_OFS               0x0000
 70 
 71 /* Shared Global Counter */
 72 #define GIC_SH_COUNTER_31_00_OFS        0x0010
 73 #define GIC_SH_COUNTER_63_32_OFS        0x0014
 74 #define GIC_SH_REVISIONID_OFS           0x0020
 75 
 76 /* Interrupt Polarity */
 77 #define GIC_SH_POL_31_0_OFS             0x0100
 78 #define GIC_SH_POL_63_32_OFS            0x0104
 79 #define GIC_SH_POL_95_64_OFS            0x0108
 80 #define GIC_SH_POL_127_96_OFS           0x010c
 81 #define GIC_SH_POL_159_128_OFS          0x0110
 82 #define GIC_SH_POL_191_160_OFS          0x0114
 83 #define GIC_SH_POL_223_192_OFS          0x0118
 84 #define GIC_SH_POL_255_224_OFS          0x011c
 85 
 86 /* Edge/Level Triggering */
 87 #define GIC_SH_TRIG_31_0_OFS            0x0180
 88 #define GIC_SH_TRIG_63_32_OFS           0x0184
 89 #define GIC_SH_TRIG_95_64_OFS           0x0188
 90 #define GIC_SH_TRIG_127_96_OFS          0x018c
 91 #define GIC_SH_TRIG_159_128_OFS         0x0190
 92 #define GIC_SH_TRIG_191_160_OFS         0x0194
 93 #define GIC_SH_TRIG_223_192_OFS         0x0198
 94 #define GIC_SH_TRIG_255_224_OFS         0x019c
 95 
 96 /* Dual Edge Triggering */
 97 #define GIC_SH_DUAL_31_0_OFS            0x0200
 98 #define GIC_SH_DUAL_63_32_OFS           0x0204
 99 #define GIC_SH_DUAL_95_64_OFS           0x0208
100 #define GIC_SH_DUAL_127_96_OFS          0x020c
101 #define GIC_SH_DUAL_159_128_OFS         0x0210
102 #define GIC_SH_DUAL_191_160_OFS         0x0214
103 #define GIC_SH_DUAL_223_192_OFS         0x0218
104 #define GIC_SH_DUAL_255_224_OFS         0x021c
105 
106 /* Set/Clear corresponding bit in Edge Detect Register */
107 #define GIC_SH_WEDGE_OFS                0x0280
108 
109 /* Reset Mask - Disables Interrupt */
110 #define GIC_SH_RMASK_31_0_OFS           0x0300
111 #define GIC_SH_RMASK_63_32_OFS          0x0304
112 #define GIC_SH_RMASK_95_64_OFS          0x0308
113 #define GIC_SH_RMASK_127_96_OFS         0x030c
114 #define GIC_SH_RMASK_159_128_OFS        0x0310
115 #define GIC_SH_RMASK_191_160_OFS        0x0314
116 #define GIC_SH_RMASK_223_192_OFS        0x0318
117 #define GIC_SH_RMASK_255_224_OFS        0x031c
118 
119 /* Set Mask (WO) - Enables Interrupt */
120 #define GIC_SH_SMASK_31_0_OFS           0x0380
121 #define GIC_SH_SMASK_63_32_OFS          0x0384
122 #define GIC_SH_SMASK_95_64_OFS          0x0388
123 #define GIC_SH_SMASK_127_96_OFS         0x038c
124 #define GIC_SH_SMASK_159_128_OFS        0x0390
125 #define GIC_SH_SMASK_191_160_OFS        0x0394
126 #define GIC_SH_SMASK_223_192_OFS        0x0398
127 #define GIC_SH_SMASK_255_224_OFS        0x039c
128 
129 /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
130 #define GIC_SH_MASK_31_0_OFS            0x0400
131 #define GIC_SH_MASK_63_32_OFS           0x0404
132 #define GIC_SH_MASK_95_64_OFS           0x0408
133 #define GIC_SH_MASK_127_96_OFS          0x040c
134 #define GIC_SH_MASK_159_128_OFS         0x0410
135 #define GIC_SH_MASK_191_160_OFS         0x0414
136 #define GIC_SH_MASK_223_192_OFS         0x0418
137 #define GIC_SH_MASK_255_224_OFS         0x041c
138 
139 /* Pending Global Interrupts (RO) */
140 #define GIC_SH_PEND_31_0_OFS            0x0480
141 #define GIC_SH_PEND_63_32_OFS           0x0484
142 #define GIC_SH_PEND_95_64_OFS           0x0488
143 #define GIC_SH_PEND_127_96_OFS          0x048c
144 #define GIC_SH_PEND_159_128_OFS         0x0490
145 #define GIC_SH_PEND_191_160_OFS         0x0494
146 #define GIC_SH_PEND_223_192_OFS         0x0498
147 #define GIC_SH_PEND_255_224_OFS         0x049c
148 
149 #define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
150 
151 /* Maps Interrupt X to a Pin */
152 #define GIC_SH_MAP_TO_PIN(intr) \
153         (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
154 
155 #define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
156 
157 /* Maps Interrupt X to a VPE */
158 #define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
159         (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
160 #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)  (1 << ((vpe) % 32))
161 
162 /* Convert an interrupt number to a byte offset/bit for multi-word registers */
163 #define GIC_INTR_OFS(intr) (((intr) / 32)*4)
164 #define GIC_INTR_BIT(intr) ((intr) % 32)
165 
166 /* Polarity : Reset Value is always 0 */
167 #define GIC_SH_SET_POLARITY_OFS         0x0100
168 #define GIC_SET_POLARITY(intr, pol) \
169         GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
170                 GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
171 
172 /* Triggering : Reset Value is always 0 */
173 #define GIC_SH_SET_TRIGGER_OFS          0x0180
174 #define GIC_SET_TRIGGER(intr, trig) \
175         GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
176                 GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
177 
178 /* Mask manipulation */
179 #define GIC_SH_SMASK_OFS                0x0380
180 #define GIC_SET_INTR_MASK(intr) \
181         GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
182                 GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
183 #define GIC_SH_RMASK_OFS                0x0300
184 #define GIC_CLR_INTR_MASK(intr) \
185         GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
186                 GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
187 
188 /* Register Map for Local Section */
189 #define GIC_VPE_CTL_OFS                 0x0000
190 #define GIC_VPE_PEND_OFS                0x0004
191 #define GIC_VPE_MASK_OFS                0x0008
192 #define GIC_VPE_RMASK_OFS               0x000c
193 #define GIC_VPE_SMASK_OFS               0x0010
194 #define GIC_VPE_WD_MAP_OFS              0x0040
195 #define GIC_VPE_COMPARE_MAP_OFS         0x0044
196 #define GIC_VPE_TIMER_MAP_OFS           0x0048
197 #define GIC_VPE_PERFCTR_MAP_OFS         0x0050
198 #define GIC_VPE_SWINT0_MAP_OFS          0x0054
199 #define GIC_VPE_SWINT1_MAP_OFS          0x0058
200 #define GIC_VPE_OTHER_ADDR_OFS          0x0080
201 #define GIC_VPE_WD_CONFIG0_OFS          0x0090
202 #define GIC_VPE_WD_COUNT0_OFS           0x0094
203 #define GIC_VPE_WD_INITIAL0_OFS         0x0098
204 #define GIC_VPE_COMPARE_LO_OFS          0x00a0
205 #define GIC_VPE_COMPARE_HI_OFS          0x00a4
206 
207 #define GIC_VPE_EIC_SHADOW_SET_BASE     0x0100
208 #define GIC_VPE_EIC_SS(intr) \
209         (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))
210 
211 #define GIC_VPE_EIC_VEC_BASE            0x0800
212 #define GIC_VPE_EIC_VEC(intr) \
213         (GIC_VPE_EIC_VEC_BASE + (4 * intr))
214 
215 #define GIC_VPE_TENABLE_NMI_OFS         0x1000
216 #define GIC_VPE_TENABLE_YQ_OFS          0x1004
217 #define GIC_VPE_TENABLE_INT_31_0_OFS    0x1080
218 #define GIC_VPE_TENABLE_INT_63_32_OFS   0x1084
219 
220 /* User Mode Visible Section Register Map */
221 #define GIC_UMV_SH_COUNTER_31_00_OFS    0x0000
222 #define GIC_UMV_SH_COUNTER_63_32_OFS    0x0004
223 
224 /* Masks */
225 #define GIC_SH_CONFIG_COUNTSTOP_SHF     28
226 #define GIC_SH_CONFIG_COUNTSTOP_MSK     (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
227 
228 #define GIC_SH_CONFIG_COUNTBITS_SHF     24
229 #define GIC_SH_CONFIG_COUNTBITS_MSK     (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
230 
231 #define GIC_SH_CONFIG_NUMINTRS_SHF      16
232 #define GIC_SH_CONFIG_NUMINTRS_MSK      (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
233 
234 #define GIC_SH_CONFIG_NUMVPES_SHF       0
235 #define GIC_SH_CONFIG_NUMVPES_MSK       (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
236 
237 #define GIC_SH_WEDGE_SET(intr)          (intr | (0x1 << 31))
238 #define GIC_SH_WEDGE_CLR(intr)          (intr & ~(0x1 << 31))
239 
240 #define GIC_MAP_TO_PIN_SHF              31
241 #define GIC_MAP_TO_PIN_MSK              (MSK(1) << GIC_MAP_TO_PIN_SHF)
242 #define GIC_MAP_TO_NMI_SHF              30
243 #define GIC_MAP_TO_NMI_MSK              (MSK(1) << GIC_MAP_TO_NMI_SHF)
244 #define GIC_MAP_TO_YQ_SHF               29
245 #define GIC_MAP_TO_YQ_MSK               (MSK(1) << GIC_MAP_TO_YQ_SHF)
246 #define GIC_MAP_SHF                     0
247 #define GIC_MAP_MSK                     (MSK(6) << GIC_MAP_SHF)
248 
249 /* GIC_VPE_CTL Masks */
250 #define GIC_VPE_CTL_PERFCNT_RTBL_SHF    2
251 #define GIC_VPE_CTL_PERFCNT_RTBL_MSK    (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
252 #define GIC_VPE_CTL_TIMER_RTBL_SHF      1
253 #define GIC_VPE_CTL_TIMER_RTBL_MSK      (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
254 #define GIC_VPE_CTL_EIC_MODE_SHF        0
255 #define GIC_VPE_CTL_EIC_MODE_MSK        (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
256 
257 /* GIC_VPE_PEND Masks */
258 #define GIC_VPE_PEND_WD_SHF             0
259 #define GIC_VPE_PEND_WD_MSK             (MSK(1) << GIC_VPE_PEND_WD_SHF)
260 #define GIC_VPE_PEND_CMP_SHF            1
261 #define GIC_VPE_PEND_CMP_MSK            (MSK(1) << GIC_VPE_PEND_CMP_SHF)
262 #define GIC_VPE_PEND_TIMER_SHF          2
263 #define GIC_VPE_PEND_TIMER_MSK          (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
264 #define GIC_VPE_PEND_PERFCOUNT_SHF      3
265 #define GIC_VPE_PEND_PERFCOUNT_MSK      (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
266 #define GIC_VPE_PEND_SWINT0_SHF         4
267 #define GIC_VPE_PEND_SWINT0_MSK         (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
268 #define GIC_VPE_PEND_SWINT1_SHF         5
269 #define GIC_VPE_PEND_SWINT1_MSK         (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
270 
271 /* GIC_VPE_RMASK Masks */
272 #define GIC_VPE_RMASK_WD_SHF            0
273 #define GIC_VPE_RMASK_WD_MSK            (MSK(1) << GIC_VPE_RMASK_WD_SHF)
274 #define GIC_VPE_RMASK_CMP_SHF           1
275 #define GIC_VPE_RMASK_CMP_MSK           (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
276 #define GIC_VPE_RMASK_TIMER_SHF         2
277 #define GIC_VPE_RMASK_TIMER_MSK         (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
278 #define GIC_VPE_RMASK_PERFCNT_SHF       3
279 #define GIC_VPE_RMASK_PERFCNT_MSK       (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
280 #define GIC_VPE_RMASK_SWINT0_SHF        4
281 #define GIC_VPE_RMASK_SWINT0_MSK        (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
282 #define GIC_VPE_RMASK_SWINT1_SHF        5
283 #define GIC_VPE_RMASK_SWINT1_MSK        (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
284 
285 /* GIC_VPE_SMASK Masks */
286 #define GIC_VPE_SMASK_WD_SHF            0
287 #define GIC_VPE_SMASK_WD_MSK            (MSK(1) << GIC_VPE_SMASK_WD_SHF)
288 #define GIC_VPE_SMASK_CMP_SHF           1
289 #define GIC_VPE_SMASK_CMP_MSK           (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
290 #define GIC_VPE_SMASK_TIMER_SHF         2
291 #define GIC_VPE_SMASK_TIMER_MSK         (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
292 #define GIC_VPE_SMASK_PERFCNT_SHF       3
293 #define GIC_VPE_SMASK_PERFCNT_MSK       (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
294 #define GIC_VPE_SMASK_SWINT0_SHF        4
295 #define GIC_VPE_SMASK_SWINT0_MSK        (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
296 #define GIC_VPE_SMASK_SWINT1_SHF        5
297 #define GIC_VPE_SMASK_SWINT1_MSK        (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
298 
299 /*
300  * Set the Mapping of Interrupt X to a VPE.
301  */
302 #define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
303         GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
304                  GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
305 
306 struct gic_pcpu_mask {
307         DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
308 };
309 
310 struct gic_pending_regs {
311         DECLARE_BITMAP(pending, GIC_NUM_INTRS);
312 };
313 
314 struct gic_intrmask_regs {
315         DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
316 };
317 
318 /*
319  * Interrupt Meta-data specification. The ipiflag helps
320  * in building ipi_map.
321  */
322 struct gic_intr_map {
323         unsigned int cpunum;    /* Directed to this CPU */
324 #define GIC_UNUSED              0xdead                  /* Dummy data */
325         unsigned int pin;       /* Directed to this Pin */
326         unsigned int polarity;  /* Polarity : +/-       */
327         unsigned int trigtype;  /* Trigger  : Edge/Levl */
328         unsigned int flags;     /* Misc flags   */
329 #define GIC_FLAG_IPI           0x01
330 #define GIC_FLAG_TRANSPARENT   0x02
331 };
332 
333 /*
334  * This is only used in EIC mode. This helps to figure out which
335  * shared interrupts we need to process when we get a vector interrupt.
336  */
337 #define GIC_MAX_SHARED_INTR  0x5
338 struct gic_shared_intr_map {
339         unsigned int num_shared_intr;
340         unsigned int intr_list[GIC_MAX_SHARED_INTR];
341         unsigned int local_intr_mask;
342 };
343 
344 /* GIC nomenclature for Core Interrupt Pins. */
345 #define GIC_CPU_INT0            0 /* Core Interrupt 2 */
346 #define GIC_CPU_INT1            1 /* .                */
347 #define GIC_CPU_INT2            2 /* .                */
348 #define GIC_CPU_INT3            3 /* .                */
349 #define GIC_CPU_INT4            4 /* .                */
350 #define GIC_CPU_INT5            5 /* Core Interrupt 7 */
351 
352 /* Local GIC interrupts. */
353 #define GIC_INT_TMR             (GIC_CPU_INT5)
354 #define GIC_INT_PERFCTR         (GIC_CPU_INT5)
355 
356 /* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
357 #define GIC_CPU_TO_VEC_OFFSET   (2)
358 
359 /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
360 #define GIC_PIN_TO_VEC_OFFSET   (1)
361 
362 #include <linux/clocksource.h>
363 #include <linux/irq.h>
364 
365 extern unsigned int gic_present;
366 extern unsigned int gic_frequency;
367 extern unsigned long _gic_base;
368 extern unsigned int gic_irq_base;
369 extern unsigned int gic_irq_flags[];
370 extern struct gic_shared_intr_map gic_shared_intr_map[];
371 
372 extern void gic_init(unsigned long gic_base_addr,
373         unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
374         unsigned int intrmap_size, unsigned int irqbase);
375 extern void gic_clocksource_init(unsigned int);
376 extern unsigned int gic_compare_int (void);
377 extern cycle_t gic_read_count(void);
378 extern cycle_t gic_read_compare(void);
379 extern void gic_write_compare(cycle_t cnt);
380 extern void gic_send_ipi(unsigned int intr);
381 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
382 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
383 extern void gic_bind_eic_interrupt(int irq, int set);
384 extern unsigned int gic_get_timer_pending(void);
385 extern unsigned int gic_get_int(void);
386 extern void gic_enable_interrupt(int irq_vec);
387 extern void gic_disable_interrupt(int irq_vec);
388 extern void gic_irq_ack(struct irq_data *d);
389 extern void gic_finish_irq(struct irq_data *d);
390 extern void gic_platform_init(int irqs, struct irq_chip *irq_controller);
391 #endif /* _ASM_GICREGS_H */
392 

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