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TOMOYO Linux Cross Reference
Linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h

Version: ~ [ linux-5.4-rc3 ] ~ [ linux-5.3.6 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.79 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.149 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.196 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.196 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.75 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 #ifndef BCM63XX_REGS_H_
  2 #define BCM63XX_REGS_H_
  3 
  4 /*************************************************************************
  5  * _REG relative to RSET_PERF
  6  *************************************************************************/
  7 
  8 /* Chip Identifier / Revision register */
  9 #define PERF_REV_REG                    0x0
 10 #define REV_CHIPID_SHIFT                16
 11 #define REV_CHIPID_MASK                 (0xffff << REV_CHIPID_SHIFT)
 12 #define REV_REVID_SHIFT                 0
 13 #define REV_REVID_MASK                  (0xff << REV_REVID_SHIFT)
 14 
 15 /* Clock Control register */
 16 #define PERF_CKCTL_REG                  0x4
 17 
 18 #define CKCTL_3368_MAC_EN               (1 << 3)
 19 #define CKCTL_3368_TC_EN                (1 << 5)
 20 #define CKCTL_3368_US_TOP_EN            (1 << 6)
 21 #define CKCTL_3368_DS_TOP_EN            (1 << 7)
 22 #define CKCTL_3368_APM_EN               (1 << 8)
 23 #define CKCTL_3368_SPI_EN               (1 << 9)
 24 #define CKCTL_3368_USBS_EN              (1 << 10)
 25 #define CKCTL_3368_BMU_EN               (1 << 11)
 26 #define CKCTL_3368_PCM_EN               (1 << 12)
 27 #define CKCTL_3368_NTP_EN               (1 << 13)
 28 #define CKCTL_3368_ACP_B_EN             (1 << 14)
 29 #define CKCTL_3368_ACP_A_EN             (1 << 15)
 30 #define CKCTL_3368_EMUSB_EN             (1 << 17)
 31 #define CKCTL_3368_ENET0_EN             (1 << 18)
 32 #define CKCTL_3368_ENET1_EN             (1 << 19)
 33 #define CKCTL_3368_USBU_EN              (1 << 20)
 34 #define CKCTL_3368_EPHY_EN              (1 << 21)
 35 
 36 #define CKCTL_3368_ALL_SAFE_EN          (CKCTL_3368_MAC_EN | \
 37                                          CKCTL_3368_TC_EN | \
 38                                          CKCTL_3368_US_TOP_EN | \
 39                                          CKCTL_3368_DS_TOP_EN | \
 40                                          CKCTL_3368_APM_EN | \
 41                                          CKCTL_3368_SPI_EN | \
 42                                          CKCTL_3368_USBS_EN | \
 43                                          CKCTL_3368_BMU_EN | \
 44                                          CKCTL_3368_PCM_EN | \
 45                                          CKCTL_3368_NTP_EN | \
 46                                          CKCTL_3368_ACP_B_EN | \
 47                                          CKCTL_3368_ACP_A_EN | \
 48                                          CKCTL_3368_EMUSB_EN | \
 49                                          CKCTL_3368_USBU_EN)
 50 
 51 #define CKCTL_6328_PHYMIPS_EN           (1 << 0)
 52 #define CKCTL_6328_ADSL_QPROC_EN        (1 << 1)
 53 #define CKCTL_6328_ADSL_AFE_EN          (1 << 2)
 54 #define CKCTL_6328_ADSL_EN              (1 << 3)
 55 #define CKCTL_6328_MIPS_EN              (1 << 4)
 56 #define CKCTL_6328_SAR_EN               (1 << 5)
 57 #define CKCTL_6328_PCM_EN               (1 << 6)
 58 #define CKCTL_6328_USBD_EN              (1 << 7)
 59 #define CKCTL_6328_USBH_EN              (1 << 8)
 60 #define CKCTL_6328_HSSPI_EN             (1 << 9)
 61 #define CKCTL_6328_PCIE_EN              (1 << 10)
 62 #define CKCTL_6328_ROBOSW_EN            (1 << 11)
 63 
 64 #define CKCTL_6328_ALL_SAFE_EN          (CKCTL_6328_PHYMIPS_EN |        \
 65                                         CKCTL_6328_ADSL_QPROC_EN |      \
 66                                         CKCTL_6328_ADSL_AFE_EN |        \
 67                                         CKCTL_6328_ADSL_EN |            \
 68                                         CKCTL_6328_SAR_EN  |            \
 69                                         CKCTL_6328_PCM_EN  |            \
 70                                         CKCTL_6328_USBD_EN |            \
 71                                         CKCTL_6328_USBH_EN |            \
 72                                         CKCTL_6328_ROBOSW_EN |          \
 73                                         CKCTL_6328_PCIE_EN)
 74 
 75 #define CKCTL_6338_ADSLPHY_EN           (1 << 0)
 76 #define CKCTL_6338_MPI_EN               (1 << 1)
 77 #define CKCTL_6338_DRAM_EN              (1 << 2)
 78 #define CKCTL_6338_ENET_EN              (1 << 4)
 79 #define CKCTL_6338_USBS_EN              (1 << 4)
 80 #define CKCTL_6338_SAR_EN               (1 << 5)
 81 #define CKCTL_6338_SPI_EN               (1 << 9)
 82 
 83 #define CKCTL_6338_ALL_SAFE_EN          (CKCTL_6338_ADSLPHY_EN |        \
 84                                         CKCTL_6338_MPI_EN |             \
 85                                         CKCTL_6338_ENET_EN |            \
 86                                         CKCTL_6338_SAR_EN |             \
 87                                         CKCTL_6338_SPI_EN)
 88 
 89 /* BCM6345 clock bits are shifted by 16 on the left, because of the test
 90  * control register which is 16-bits wide. That way we do not have any
 91  * specific BCM6345 code for handling clocks, and writing 0 to the test
 92  * control register is fine.
 93  */
 94 #define CKCTL_6345_CPU_EN               (1 << 16)
 95 #define CKCTL_6345_BUS_EN               (1 << 17)
 96 #define CKCTL_6345_EBI_EN               (1 << 18)
 97 #define CKCTL_6345_UART_EN              (1 << 19)
 98 #define CKCTL_6345_ADSLPHY_EN           (1 << 20)
 99 #define CKCTL_6345_ENET_EN              (1 << 23)
100 #define CKCTL_6345_USBH_EN              (1 << 24)
101 
102 #define CKCTL_6345_ALL_SAFE_EN          (CKCTL_6345_ENET_EN |   \
103                                         CKCTL_6345_USBH_EN |    \
104                                         CKCTL_6345_ADSLPHY_EN)
105 
106 #define CKCTL_6348_ADSLPHY_EN           (1 << 0)
107 #define CKCTL_6348_MPI_EN               (1 << 1)
108 #define CKCTL_6348_SDRAM_EN             (1 << 2)
109 #define CKCTL_6348_M2M_EN               (1 << 3)
110 #define CKCTL_6348_ENET_EN              (1 << 4)
111 #define CKCTL_6348_SAR_EN               (1 << 5)
112 #define CKCTL_6348_USBS_EN              (1 << 6)
113 #define CKCTL_6348_USBH_EN              (1 << 8)
114 #define CKCTL_6348_SPI_EN               (1 << 9)
115 
116 #define CKCTL_6348_ALL_SAFE_EN          (CKCTL_6348_ADSLPHY_EN |        \
117                                         CKCTL_6348_M2M_EN |             \
118                                         CKCTL_6348_ENET_EN |            \
119                                         CKCTL_6348_SAR_EN |             \
120                                         CKCTL_6348_USBS_EN |            \
121                                         CKCTL_6348_USBH_EN |            \
122                                         CKCTL_6348_SPI_EN)
123 
124 #define CKCTL_6358_ENET_EN              (1 << 4)
125 #define CKCTL_6358_ADSLPHY_EN           (1 << 5)
126 #define CKCTL_6358_PCM_EN               (1 << 8)
127 #define CKCTL_6358_SPI_EN               (1 << 9)
128 #define CKCTL_6358_USBS_EN              (1 << 10)
129 #define CKCTL_6358_SAR_EN               (1 << 11)
130 #define CKCTL_6358_EMUSB_EN             (1 << 17)
131 #define CKCTL_6358_ENET0_EN             (1 << 18)
132 #define CKCTL_6358_ENET1_EN             (1 << 19)
133 #define CKCTL_6358_USBSU_EN             (1 << 20)
134 #define CKCTL_6358_EPHY_EN              (1 << 21)
135 
136 #define CKCTL_6358_ALL_SAFE_EN          (CKCTL_6358_ENET_EN |           \
137                                         CKCTL_6358_ADSLPHY_EN |         \
138                                         CKCTL_6358_PCM_EN |             \
139                                         CKCTL_6358_SPI_EN |             \
140                                         CKCTL_6358_USBS_EN |            \
141                                         CKCTL_6358_SAR_EN |             \
142                                         CKCTL_6358_EMUSB_EN |           \
143                                         CKCTL_6358_ENET0_EN |           \
144                                         CKCTL_6358_ENET1_EN |           \
145                                         CKCTL_6358_USBSU_EN |           \
146                                         CKCTL_6358_EPHY_EN)
147 
148 #define CKCTL_6362_ADSL_QPROC_EN        (1 << 1)
149 #define CKCTL_6362_ADSL_AFE_EN          (1 << 2)
150 #define CKCTL_6362_ADSL_EN              (1 << 3)
151 #define CKCTL_6362_MIPS_EN              (1 << 4)
152 #define CKCTL_6362_WLAN_OCP_EN          (1 << 5)
153 #define CKCTL_6362_SWPKT_USB_EN         (1 << 7)
154 #define CKCTL_6362_SWPKT_SAR_EN         (1 << 8)
155 #define CKCTL_6362_SAR_EN               (1 << 9)
156 #define CKCTL_6362_ROBOSW_EN            (1 << 10)
157 #define CKCTL_6362_PCM_EN               (1 << 11)
158 #define CKCTL_6362_USBD_EN              (1 << 12)
159 #define CKCTL_6362_USBH_EN              (1 << 13)
160 #define CKCTL_6362_IPSEC_EN             (1 << 14)
161 #define CKCTL_6362_SPI_EN               (1 << 15)
162 #define CKCTL_6362_HSSPI_EN             (1 << 16)
163 #define CKCTL_6362_PCIE_EN              (1 << 17)
164 #define CKCTL_6362_FAP_EN               (1 << 18)
165 #define CKCTL_6362_PHYMIPS_EN           (1 << 19)
166 #define CKCTL_6362_NAND_EN              (1 << 20)
167 
168 #define CKCTL_6362_ALL_SAFE_EN          (CKCTL_6362_PHYMIPS_EN |        \
169                                         CKCTL_6362_ADSL_QPROC_EN |      \
170                                         CKCTL_6362_ADSL_AFE_EN |        \
171                                         CKCTL_6362_ADSL_EN |            \
172                                         CKCTL_6362_SAR_EN  |            \
173                                         CKCTL_6362_PCM_EN  |            \
174                                         CKCTL_6362_IPSEC_EN |           \
175                                         CKCTL_6362_USBD_EN |            \
176                                         CKCTL_6362_USBH_EN |            \
177                                         CKCTL_6362_ROBOSW_EN |          \
178                                         CKCTL_6362_PCIE_EN)
179 
180 
181 #define CKCTL_6368_VDSL_QPROC_EN        (1 << 2)
182 #define CKCTL_6368_VDSL_AFE_EN          (1 << 3)
183 #define CKCTL_6368_VDSL_BONDING_EN      (1 << 4)
184 #define CKCTL_6368_VDSL_EN              (1 << 5)
185 #define CKCTL_6368_PHYMIPS_EN           (1 << 6)
186 #define CKCTL_6368_SWPKT_USB_EN         (1 << 7)
187 #define CKCTL_6368_SWPKT_SAR_EN         (1 << 8)
188 #define CKCTL_6368_SPI_EN               (1 << 9)
189 #define CKCTL_6368_USBD_EN              (1 << 10)
190 #define CKCTL_6368_SAR_EN               (1 << 11)
191 #define CKCTL_6368_ROBOSW_EN            (1 << 12)
192 #define CKCTL_6368_UTOPIA_EN            (1 << 13)
193 #define CKCTL_6368_PCM_EN               (1 << 14)
194 #define CKCTL_6368_USBH_EN              (1 << 15)
195 #define CKCTL_6368_DISABLE_GLESS_EN     (1 << 16)
196 #define CKCTL_6368_NAND_EN              (1 << 17)
197 #define CKCTL_6368_IPSEC_EN             (1 << 18)
198 
199 #define CKCTL_6368_ALL_SAFE_EN          (CKCTL_6368_SWPKT_USB_EN |      \
200                                         CKCTL_6368_SWPKT_SAR_EN |       \
201                                         CKCTL_6368_SPI_EN |             \
202                                         CKCTL_6368_USBD_EN |            \
203                                         CKCTL_6368_SAR_EN |             \
204                                         CKCTL_6368_ROBOSW_EN |          \
205                                         CKCTL_6368_UTOPIA_EN |          \
206                                         CKCTL_6368_PCM_EN |             \
207                                         CKCTL_6368_USBH_EN |            \
208                                         CKCTL_6368_DISABLE_GLESS_EN |   \
209                                         CKCTL_6368_NAND_EN |            \
210                                         CKCTL_6368_IPSEC_EN)
211 
212 /* System PLL Control register  */
213 #define PERF_SYS_PLL_CTL_REG            0x8
214 #define SYS_PLL_SOFT_RESET              0x1
215 
216 /* Interrupt Mask register */
217 #define PERF_IRQMASK_3368_REG           0xc
218 #define PERF_IRQMASK_6328_REG(x)        (0x20 + (x) * 0x10)
219 #define PERF_IRQMASK_6338_REG           0xc
220 #define PERF_IRQMASK_6345_REG           0xc
221 #define PERF_IRQMASK_6348_REG           0xc
222 #define PERF_IRQMASK_6358_REG(x)        (0xc + (x) * 0x2c)
223 #define PERF_IRQMASK_6362_REG(x)        (0x20 + (x) * 0x10)
224 #define PERF_IRQMASK_6368_REG(x)        (0x20 + (x) * 0x10)
225 
226 /* Interrupt Status register */
227 #define PERF_IRQSTAT_3368_REG           0x10
228 #define PERF_IRQSTAT_6328_REG(x)        (0x28 + (x) * 0x10)
229 #define PERF_IRQSTAT_6338_REG           0x10
230 #define PERF_IRQSTAT_6345_REG           0x10
231 #define PERF_IRQSTAT_6348_REG           0x10
232 #define PERF_IRQSTAT_6358_REG(x)        (0x10 + (x) * 0x2c)
233 #define PERF_IRQSTAT_6362_REG(x)        (0x28 + (x) * 0x10)
234 #define PERF_IRQSTAT_6368_REG(x)        (0x28 + (x) * 0x10)
235 
236 /* External Interrupt Configuration register */
237 #define PERF_EXTIRQ_CFG_REG_3368        0x14
238 #define PERF_EXTIRQ_CFG_REG_6328        0x18
239 #define PERF_EXTIRQ_CFG_REG_6338        0x14
240 #define PERF_EXTIRQ_CFG_REG_6345        0x14
241 #define PERF_EXTIRQ_CFG_REG_6348        0x14
242 #define PERF_EXTIRQ_CFG_REG_6358        0x14
243 #define PERF_EXTIRQ_CFG_REG_6362        0x18
244 #define PERF_EXTIRQ_CFG_REG_6368        0x18
245 
246 #define PERF_EXTIRQ_CFG_REG2_6368       0x1c
247 
248 /* for 6348 only */
249 #define EXTIRQ_CFG_SENSE_6348(x)        (1 << (x))
250 #define EXTIRQ_CFG_STAT_6348(x)         (1 << (x + 5))
251 #define EXTIRQ_CFG_CLEAR_6348(x)        (1 << (x + 10))
252 #define EXTIRQ_CFG_MASK_6348(x)         (1 << (x + 15))
253 #define EXTIRQ_CFG_BOTHEDGE_6348(x)     (1 << (x + 20))
254 #define EXTIRQ_CFG_LEVELSENSE_6348(x)   (1 << (x + 25))
255 #define EXTIRQ_CFG_CLEAR_ALL_6348       (0xf << 10)
256 #define EXTIRQ_CFG_MASK_ALL_6348        (0xf << 15)
257 
258 /* for all others */
259 #define EXTIRQ_CFG_SENSE(x)             (1 << (x))
260 #define EXTIRQ_CFG_STAT(x)              (1 << (x + 4))
261 #define EXTIRQ_CFG_CLEAR(x)             (1 << (x + 8))
262 #define EXTIRQ_CFG_MASK(x)              (1 << (x + 12))
263 #define EXTIRQ_CFG_BOTHEDGE(x)          (1 << (x + 16))
264 #define EXTIRQ_CFG_LEVELSENSE(x)        (1 << (x + 20))
265 #define EXTIRQ_CFG_CLEAR_ALL            (0xf << 8)
266 #define EXTIRQ_CFG_MASK_ALL             (0xf << 12)
267 
268 /* Soft Reset register */
269 #define PERF_SOFTRESET_REG              0x28
270 #define PERF_SOFTRESET_6328_REG         0x10
271 #define PERF_SOFTRESET_6358_REG         0x34
272 #define PERF_SOFTRESET_6362_REG         0x10
273 #define PERF_SOFTRESET_6368_REG         0x10
274 
275 #define SOFTRESET_3368_SPI_MASK         (1 << 0)
276 #define SOFTRESET_3368_ENET_MASK        (1 << 2)
277 #define SOFTRESET_3368_MPI_MASK         (1 << 3)
278 #define SOFTRESET_3368_EPHY_MASK        (1 << 6)
279 #define SOFTRESET_3368_USBS_MASK        (1 << 11)
280 #define SOFTRESET_3368_PCM_MASK         (1 << 13)
281 
282 #define SOFTRESET_6328_SPI_MASK         (1 << 0)
283 #define SOFTRESET_6328_EPHY_MASK        (1 << 1)
284 #define SOFTRESET_6328_SAR_MASK         (1 << 2)
285 #define SOFTRESET_6328_ENETSW_MASK      (1 << 3)
286 #define SOFTRESET_6328_USBS_MASK        (1 << 4)
287 #define SOFTRESET_6328_USBH_MASK        (1 << 5)
288 #define SOFTRESET_6328_PCM_MASK         (1 << 6)
289 #define SOFTRESET_6328_PCIE_CORE_MASK   (1 << 7)
290 #define SOFTRESET_6328_PCIE_MASK        (1 << 8)
291 #define SOFTRESET_6328_PCIE_EXT_MASK    (1 << 9)
292 #define SOFTRESET_6328_PCIE_HARD_MASK   (1 << 10)
293 
294 #define SOFTRESET_6338_SPI_MASK         (1 << 0)
295 #define SOFTRESET_6338_ENET_MASK        (1 << 2)
296 #define SOFTRESET_6338_USBH_MASK        (1 << 3)
297 #define SOFTRESET_6338_USBS_MASK        (1 << 4)
298 #define SOFTRESET_6338_ADSL_MASK        (1 << 5)
299 #define SOFTRESET_6338_DMAMEM_MASK      (1 << 6)
300 #define SOFTRESET_6338_SAR_MASK         (1 << 7)
301 #define SOFTRESET_6338_ACLC_MASK        (1 << 8)
302 #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
303 #define SOFTRESET_6338_ALL       (SOFTRESET_6338_SPI_MASK |             \
304                                   SOFTRESET_6338_ENET_MASK |            \
305                                   SOFTRESET_6338_USBH_MASK |            \
306                                   SOFTRESET_6338_USBS_MASK |            \
307                                   SOFTRESET_6338_ADSL_MASK |            \
308                                   SOFTRESET_6338_DMAMEM_MASK |          \
309                                   SOFTRESET_6338_SAR_MASK |             \
310                                   SOFTRESET_6338_ACLC_MASK |            \
311                                   SOFTRESET_6338_ADSLMIPSPLL_MASK)
312 
313 #define SOFTRESET_6348_SPI_MASK         (1 << 0)
314 #define SOFTRESET_6348_ENET_MASK        (1 << 2)
315 #define SOFTRESET_6348_USBH_MASK        (1 << 3)
316 #define SOFTRESET_6348_USBS_MASK        (1 << 4)
317 #define SOFTRESET_6348_ADSL_MASK        (1 << 5)
318 #define SOFTRESET_6348_DMAMEM_MASK      (1 << 6)
319 #define SOFTRESET_6348_SAR_MASK         (1 << 7)
320 #define SOFTRESET_6348_ACLC_MASK        (1 << 8)
321 #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
322 
323 #define SOFTRESET_6348_ALL       (SOFTRESET_6348_SPI_MASK |             \
324                                   SOFTRESET_6348_ENET_MASK |            \
325                                   SOFTRESET_6348_USBH_MASK |            \
326                                   SOFTRESET_6348_USBS_MASK |            \
327                                   SOFTRESET_6348_ADSL_MASK |            \
328                                   SOFTRESET_6348_DMAMEM_MASK |          \
329                                   SOFTRESET_6348_SAR_MASK |             \
330                                   SOFTRESET_6348_ACLC_MASK |            \
331                                   SOFTRESET_6348_ADSLMIPSPLL_MASK)
332 
333 #define SOFTRESET_6358_SPI_MASK         (1 << 0)
334 #define SOFTRESET_6358_ENET_MASK        (1 << 2)
335 #define SOFTRESET_6358_MPI_MASK         (1 << 3)
336 #define SOFTRESET_6358_EPHY_MASK        (1 << 6)
337 #define SOFTRESET_6358_SAR_MASK         (1 << 7)
338 #define SOFTRESET_6358_USBH_MASK        (1 << 12)
339 #define SOFTRESET_6358_PCM_MASK         (1 << 13)
340 #define SOFTRESET_6358_ADSL_MASK        (1 << 14)
341 
342 #define SOFTRESET_6362_SPI_MASK         (1 << 0)
343 #define SOFTRESET_6362_IPSEC_MASK       (1 << 1)
344 #define SOFTRESET_6362_EPHY_MASK        (1 << 2)
345 #define SOFTRESET_6362_SAR_MASK         (1 << 3)
346 #define SOFTRESET_6362_ENETSW_MASK      (1 << 4)
347 #define SOFTRESET_6362_USBS_MASK        (1 << 5)
348 #define SOFTRESET_6362_USBH_MASK        (1 << 6)
349 #define SOFTRESET_6362_PCM_MASK         (1 << 7)
350 #define SOFTRESET_6362_PCIE_CORE_MASK   (1 << 8)
351 #define SOFTRESET_6362_PCIE_MASK        (1 << 9)
352 #define SOFTRESET_6362_PCIE_EXT_MASK    (1 << 10)
353 #define SOFTRESET_6362_WLAN_SHIM_MASK   (1 << 11)
354 #define SOFTRESET_6362_DDR_PHY_MASK     (1 << 12)
355 #define SOFTRESET_6362_FAP_MASK         (1 << 13)
356 #define SOFTRESET_6362_WLAN_UBUS_MASK   (1 << 14)
357 
358 #define SOFTRESET_6368_SPI_MASK         (1 << 0)
359 #define SOFTRESET_6368_MPI_MASK         (1 << 3)
360 #define SOFTRESET_6368_EPHY_MASK        (1 << 6)
361 #define SOFTRESET_6368_SAR_MASK         (1 << 7)
362 #define SOFTRESET_6368_ENETSW_MASK      (1 << 10)
363 #define SOFTRESET_6368_USBS_MASK        (1 << 11)
364 #define SOFTRESET_6368_USBH_MASK        (1 << 12)
365 #define SOFTRESET_6368_PCM_MASK         (1 << 13)
366 
367 /* MIPS PLL control register */
368 #define PERF_MIPSPLLCTL_REG             0x34
369 #define MIPSPLLCTL_N1_SHIFT             20
370 #define MIPSPLLCTL_N1_MASK              (0x7 << MIPSPLLCTL_N1_SHIFT)
371 #define MIPSPLLCTL_N2_SHIFT             15
372 #define MIPSPLLCTL_N2_MASK              (0x1f << MIPSPLLCTL_N2_SHIFT)
373 #define MIPSPLLCTL_M1REF_SHIFT          12
374 #define MIPSPLLCTL_M1REF_MASK           (0x7 << MIPSPLLCTL_M1REF_SHIFT)
375 #define MIPSPLLCTL_M2REF_SHIFT          9
376 #define MIPSPLLCTL_M2REF_MASK           (0x7 << MIPSPLLCTL_M2REF_SHIFT)
377 #define MIPSPLLCTL_M1CPU_SHIFT          6
378 #define MIPSPLLCTL_M1CPU_MASK           (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
379 #define MIPSPLLCTL_M1BUS_SHIFT          3
380 #define MIPSPLLCTL_M1BUS_MASK           (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
381 #define MIPSPLLCTL_M2BUS_SHIFT          0
382 #define MIPSPLLCTL_M2BUS_MASK           (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
383 
384 /* ADSL PHY PLL Control register */
385 #define PERF_ADSLPLLCTL_REG             0x38
386 #define ADSLPLLCTL_N1_SHIFT             20
387 #define ADSLPLLCTL_N1_MASK              (0x7 << ADSLPLLCTL_N1_SHIFT)
388 #define ADSLPLLCTL_N2_SHIFT             15
389 #define ADSLPLLCTL_N2_MASK              (0x1f << ADSLPLLCTL_N2_SHIFT)
390 #define ADSLPLLCTL_M1REF_SHIFT          12
391 #define ADSLPLLCTL_M1REF_MASK           (0x7 << ADSLPLLCTL_M1REF_SHIFT)
392 #define ADSLPLLCTL_M2REF_SHIFT          9
393 #define ADSLPLLCTL_M2REF_MASK           (0x7 << ADSLPLLCTL_M2REF_SHIFT)
394 #define ADSLPLLCTL_M1CPU_SHIFT          6
395 #define ADSLPLLCTL_M1CPU_MASK           (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
396 #define ADSLPLLCTL_M1BUS_SHIFT          3
397 #define ADSLPLLCTL_M1BUS_MASK           (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
398 #define ADSLPLLCTL_M2BUS_SHIFT          0
399 #define ADSLPLLCTL_M2BUS_MASK           (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
400 
401 #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus)       \
402                                 (((n1) << ADSLPLLCTL_N1_SHIFT) |        \
403                                 ((n2) << ADSLPLLCTL_N2_SHIFT) |         \
404                                 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) |   \
405                                 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) |   \
406                                 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) |   \
407                                 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) |   \
408                                 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
409 
410 
411 /*************************************************************************
412  * _REG relative to RSET_TIMER
413  *************************************************************************/
414 
415 #define BCM63XX_TIMER_COUNT             4
416 #define TIMER_T0_ID                     0
417 #define TIMER_T1_ID                     1
418 #define TIMER_T2_ID                     2
419 #define TIMER_WDT_ID                    3
420 
421 /* Timer irqstat register */
422 #define TIMER_IRQSTAT_REG               0
423 #define TIMER_IRQSTAT_TIMER_CAUSE(x)    (1 << (x))
424 #define TIMER_IRQSTAT_TIMER0_CAUSE      (1 << 0)
425 #define TIMER_IRQSTAT_TIMER1_CAUSE      (1 << 1)
426 #define TIMER_IRQSTAT_TIMER2_CAUSE      (1 << 2)
427 #define TIMER_IRQSTAT_WDT_CAUSE         (1 << 3)
428 #define TIMER_IRQSTAT_TIMER_IR_EN(x)    (1 << ((x) + 8))
429 #define TIMER_IRQSTAT_TIMER0_IR_EN      (1 << 8)
430 #define TIMER_IRQSTAT_TIMER1_IR_EN      (1 << 9)
431 #define TIMER_IRQSTAT_TIMER2_IR_EN      (1 << 10)
432 
433 /* Timer control register */
434 #define TIMER_CTLx_REG(x)               (0x4 + (x * 4))
435 #define TIMER_CTL0_REG                  0x4
436 #define TIMER_CTL1_REG                  0x8
437 #define TIMER_CTL2_REG                  0xC
438 #define TIMER_CTL_COUNTDOWN_MASK        (0x3fffffff)
439 #define TIMER_CTL_MONOTONIC_MASK        (1 << 30)
440 #define TIMER_CTL_ENABLE_MASK           (1 << 31)
441 
442 
443 /*************************************************************************
444  * _REG relative to RSET_WDT
445  *************************************************************************/
446 
447 /* Watchdog default count register */
448 #define WDT_DEFVAL_REG                  0x0
449 
450 /* Watchdog control register */
451 #define WDT_CTL_REG                     0x4
452 
453 /* Watchdog control register constants */
454 #define WDT_START_1                     (0xff00)
455 #define WDT_START_2                     (0x00ff)
456 #define WDT_STOP_1                      (0xee00)
457 #define WDT_STOP_2                      (0x00ee)
458 
459 /* Watchdog reset length register */
460 #define WDT_RSTLEN_REG                  0x8
461 
462 /* Watchdog soft reset register (BCM6328 only) */
463 #define WDT_SOFTRESET_REG               0xc
464 
465 /*************************************************************************
466  * _REG relative to RSET_GPIO
467  *************************************************************************/
468 
469 /* GPIO registers */
470 #define GPIO_CTL_HI_REG                 0x0
471 #define GPIO_CTL_LO_REG                 0x4
472 #define GPIO_DATA_HI_REG                0x8
473 #define GPIO_DATA_LO_REG                0xC
474 #define GPIO_DATA_LO_REG_6345           0x8
475 
476 /* GPIO mux registers and constants */
477 #define GPIO_MODE_REG                   0x18
478 
479 #define GPIO_MODE_6348_G4_DIAG          0x00090000
480 #define GPIO_MODE_6348_G4_UTOPIA        0x00080000
481 #define GPIO_MODE_6348_G4_LEGACY_LED    0x00030000
482 #define GPIO_MODE_6348_G4_MII_SNOOP     0x00020000
483 #define GPIO_MODE_6348_G4_EXT_EPHY      0x00010000
484 #define GPIO_MODE_6348_G3_DIAG          0x00009000
485 #define GPIO_MODE_6348_G3_UTOPIA        0x00008000
486 #define GPIO_MODE_6348_G3_EXT_MII       0x00007000
487 #define GPIO_MODE_6348_G2_DIAG          0x00000900
488 #define GPIO_MODE_6348_G2_PCI           0x00000500
489 #define GPIO_MODE_6348_G1_DIAG          0x00000090
490 #define GPIO_MODE_6348_G1_UTOPIA        0x00000080
491 #define GPIO_MODE_6348_G1_SPI_UART      0x00000060
492 #define GPIO_MODE_6348_G1_SPI_MASTER    0x00000060
493 #define GPIO_MODE_6348_G1_MII_PCCARD    0x00000040
494 #define GPIO_MODE_6348_G1_MII_SNOOP     0x00000020
495 #define GPIO_MODE_6348_G1_EXT_EPHY      0x00000010
496 #define GPIO_MODE_6348_G0_DIAG          0x00000009
497 #define GPIO_MODE_6348_G0_EXT_MII       0x00000007
498 
499 #define GPIO_MODE_6358_EXTRACS          (1 << 5)
500 #define GPIO_MODE_6358_UART1            (1 << 6)
501 #define GPIO_MODE_6358_EXTRA_SPI_SS     (1 << 7)
502 #define GPIO_MODE_6358_SERIAL_LED       (1 << 10)
503 #define GPIO_MODE_6358_UTOPIA           (1 << 12)
504 
505 #define GPIO_MODE_6368_ANALOG_AFE_0     (1 << 0)
506 #define GPIO_MODE_6368_ANALOG_AFE_1     (1 << 1)
507 #define GPIO_MODE_6368_SYS_IRQ          (1 << 2)
508 #define GPIO_MODE_6368_SERIAL_LED_DATA  (1 << 3)
509 #define GPIO_MODE_6368_SERIAL_LED_CLK   (1 << 4)
510 #define GPIO_MODE_6368_INET_LED         (1 << 5)
511 #define GPIO_MODE_6368_EPHY0_LED        (1 << 6)
512 #define GPIO_MODE_6368_EPHY1_LED        (1 << 7)
513 #define GPIO_MODE_6368_EPHY2_LED        (1 << 8)
514 #define GPIO_MODE_6368_EPHY3_LED        (1 << 9)
515 #define GPIO_MODE_6368_ROBOSW_LED_DAT   (1 << 10)
516 #define GPIO_MODE_6368_ROBOSW_LED_CLK   (1 << 11)
517 #define GPIO_MODE_6368_ROBOSW_LED0      (1 << 12)
518 #define GPIO_MODE_6368_ROBOSW_LED1      (1 << 13)
519 #define GPIO_MODE_6368_USBD_LED         (1 << 14)
520 #define GPIO_MODE_6368_NTR_PULSE        (1 << 15)
521 #define GPIO_MODE_6368_PCI_REQ1         (1 << 16)
522 #define GPIO_MODE_6368_PCI_GNT1         (1 << 17)
523 #define GPIO_MODE_6368_PCI_INTB         (1 << 18)
524 #define GPIO_MODE_6368_PCI_REQ0         (1 << 19)
525 #define GPIO_MODE_6368_PCI_GNT0         (1 << 20)
526 #define GPIO_MODE_6368_PCMCIA_CD1       (1 << 22)
527 #define GPIO_MODE_6368_PCMCIA_CD2       (1 << 23)
528 #define GPIO_MODE_6368_PCMCIA_VS1       (1 << 24)
529 #define GPIO_MODE_6368_PCMCIA_VS2       (1 << 25)
530 #define GPIO_MODE_6368_EBI_CS2          (1 << 26)
531 #define GPIO_MODE_6368_EBI_CS3          (1 << 27)
532 #define GPIO_MODE_6368_SPI_SSN2         (1 << 28)
533 #define GPIO_MODE_6368_SPI_SSN3         (1 << 29)
534 #define GPIO_MODE_6368_SPI_SSN4         (1 << 30)
535 #define GPIO_MODE_6368_SPI_SSN5         (1 << 31)
536 
537 
538 #define GPIO_PINMUX_OTHR_REG            0x24
539 #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
540 #define GPIO_PINMUX_OTHR_6328_USB_MASK  (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
541 #define GPIO_PINMUX_OTHR_6328_USB_HOST  (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
542 #define GPIO_PINMUX_OTHR_6328_USB_DEV   (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
543 
544 #define GPIO_BASEMODE_6368_REG          0x38
545 #define GPIO_BASEMODE_6368_UART2        0x1
546 #define GPIO_BASEMODE_6368_GPIO         0x0
547 #define GPIO_BASEMODE_6368_MASK         0x7
548 /* those bits must be kept as read in gpio basemode register*/
549 
550 #define GPIO_STRAPBUS_REG               0x40
551 #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
552 #define STRAPBUS_6358_BOOT_SEL_SERIAL   (0 << 1)
553 #define STRAPBUS_6368_BOOT_SEL_MASK     0x3
554 #define STRAPBUS_6368_BOOT_SEL_NAND     0
555 #define STRAPBUS_6368_BOOT_SEL_SERIAL   1
556 #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
557 
558 
559 /*************************************************************************
560  * _REG relative to RSET_ENET
561  *************************************************************************/
562 
563 /* Receiver Configuration register */
564 #define ENET_RXCFG_REG                  0x0
565 #define ENET_RXCFG_ALLMCAST_SHIFT       1
566 #define ENET_RXCFG_ALLMCAST_MASK        (1 << ENET_RXCFG_ALLMCAST_SHIFT)
567 #define ENET_RXCFG_PROMISC_SHIFT        3
568 #define ENET_RXCFG_PROMISC_MASK         (1 << ENET_RXCFG_PROMISC_SHIFT)
569 #define ENET_RXCFG_LOOPBACK_SHIFT       4
570 #define ENET_RXCFG_LOOPBACK_MASK        (1 << ENET_RXCFG_LOOPBACK_SHIFT)
571 #define ENET_RXCFG_ENFLOW_SHIFT         5
572 #define ENET_RXCFG_ENFLOW_MASK          (1 << ENET_RXCFG_ENFLOW_SHIFT)
573 
574 /* Receive Maximum Length register */
575 #define ENET_RXMAXLEN_REG               0x4
576 #define ENET_RXMAXLEN_SHIFT             0
577 #define ENET_RXMAXLEN_MASK              (0x7ff << ENET_RXMAXLEN_SHIFT)
578 
579 /* Transmit Maximum Length register */
580 #define ENET_TXMAXLEN_REG               0x8
581 #define ENET_TXMAXLEN_SHIFT             0
582 #define ENET_TXMAXLEN_MASK              (0x7ff << ENET_TXMAXLEN_SHIFT)
583 
584 /* MII Status/Control register */
585 #define ENET_MIISC_REG                  0x10
586 #define ENET_MIISC_MDCFREQDIV_SHIFT     0
587 #define ENET_MIISC_MDCFREQDIV_MASK      (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
588 #define ENET_MIISC_PREAMBLEEN_SHIFT     7
589 #define ENET_MIISC_PREAMBLEEN_MASK      (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
590 
591 /* MII Data register */
592 #define ENET_MIIDATA_REG                0x14
593 #define ENET_MIIDATA_DATA_SHIFT         0
594 #define ENET_MIIDATA_DATA_MASK          (0xffff << ENET_MIIDATA_DATA_SHIFT)
595 #define ENET_MIIDATA_TA_SHIFT           16
596 #define ENET_MIIDATA_TA_MASK            (0x3 << ENET_MIIDATA_TA_SHIFT)
597 #define ENET_MIIDATA_REG_SHIFT          18
598 #define ENET_MIIDATA_REG_MASK           (0x1f << ENET_MIIDATA_REG_SHIFT)
599 #define ENET_MIIDATA_PHYID_SHIFT        23
600 #define ENET_MIIDATA_PHYID_MASK         (0x1f << ENET_MIIDATA_PHYID_SHIFT)
601 #define ENET_MIIDATA_OP_READ_MASK       (0x6 << 28)
602 #define ENET_MIIDATA_OP_WRITE_MASK      (0x5 << 28)
603 
604 /* Ethernet Interrupt Mask register */
605 #define ENET_IRMASK_REG                 0x18
606 
607 /* Ethernet Interrupt register */
608 #define ENET_IR_REG                     0x1c
609 #define ENET_IR_MII                     (1 << 0)
610 #define ENET_IR_MIB                     (1 << 1)
611 #define ENET_IR_FLOWC                   (1 << 2)
612 
613 /* Ethernet Control register */
614 #define ENET_CTL_REG                    0x2c
615 #define ENET_CTL_ENABLE_SHIFT           0
616 #define ENET_CTL_ENABLE_MASK            (1 << ENET_CTL_ENABLE_SHIFT)
617 #define ENET_CTL_DISABLE_SHIFT          1
618 #define ENET_CTL_DISABLE_MASK           (1 << ENET_CTL_DISABLE_SHIFT)
619 #define ENET_CTL_SRESET_SHIFT           2
620 #define ENET_CTL_SRESET_MASK            (1 << ENET_CTL_SRESET_SHIFT)
621 #define ENET_CTL_EPHYSEL_SHIFT          3
622 #define ENET_CTL_EPHYSEL_MASK           (1 << ENET_CTL_EPHYSEL_SHIFT)
623 
624 /* Transmit Control register */
625 #define ENET_TXCTL_REG                  0x30
626 #define ENET_TXCTL_FD_SHIFT             0
627 #define ENET_TXCTL_FD_MASK              (1 << ENET_TXCTL_FD_SHIFT)
628 
629 /* Transmit Watermask register */
630 #define ENET_TXWMARK_REG                0x34
631 #define ENET_TXWMARK_WM_SHIFT           0
632 #define ENET_TXWMARK_WM_MASK            (0x3f << ENET_TXWMARK_WM_SHIFT)
633 
634 /* MIB Control register */
635 #define ENET_MIBCTL_REG                 0x38
636 #define ENET_MIBCTL_RDCLEAR_SHIFT       0
637 #define ENET_MIBCTL_RDCLEAR_MASK        (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
638 
639 /* Perfect Match Data Low register */
640 #define ENET_PML_REG(x)                 (0x58 + (x) * 8)
641 #define ENET_PMH_REG(x)                 (0x5c + (x) * 8)
642 #define ENET_PMH_DATAVALID_SHIFT        16
643 #define ENET_PMH_DATAVALID_MASK         (1 << ENET_PMH_DATAVALID_SHIFT)
644 
645 /* MIB register */
646 #define ENET_MIB_REG(x)                 (0x200 + (x) * 4)
647 #define ENET_MIB_REG_COUNT              55
648 
649 
650 /*************************************************************************
651  * _REG relative to RSET_ENETDMA
652  *************************************************************************/
653 #define ENETDMA_CHAN_WIDTH              0x10
654 #define ENETDMA_6345_CHAN_WIDTH         0x40
655 
656 /* Controller Configuration Register */
657 #define ENETDMA_CFG_REG                 (0x0)
658 #define ENETDMA_CFG_EN_SHIFT            0
659 #define ENETDMA_CFG_EN_MASK             (1 << ENETDMA_CFG_EN_SHIFT)
660 #define ENETDMA_CFG_FLOWCH_MASK(x)      (1 << ((x >> 1) + 1))
661 
662 /* Flow Control Descriptor Low Threshold register */
663 #define ENETDMA_FLOWCL_REG(x)           (0x4 + (x) * 6)
664 
665 /* Flow Control Descriptor High Threshold register */
666 #define ENETDMA_FLOWCH_REG(x)           (0x8 + (x) * 6)
667 
668 /* Flow Control Descriptor Buffer Alloca Threshold register */
669 #define ENETDMA_BUFALLOC_REG(x)         (0xc + (x) * 6)
670 #define ENETDMA_BUFALLOC_FORCE_SHIFT    31
671 #define ENETDMA_BUFALLOC_FORCE_MASK     (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
672 
673 /* Global interrupt status */
674 #define ENETDMA_GLB_IRQSTAT_REG         (0x40)
675 
676 /* Global interrupt mask */
677 #define ENETDMA_GLB_IRQMASK_REG         (0x44)
678 
679 /* Channel Configuration register */
680 #define ENETDMA_CHANCFG_REG(x)          (0x100 + (x) * 0x10)
681 #define ENETDMA_CHANCFG_EN_SHIFT        0
682 #define ENETDMA_CHANCFG_EN_MASK         (1 << ENETDMA_CHANCFG_EN_SHIFT)
683 #define ENETDMA_CHANCFG_PKTHALT_SHIFT   1
684 #define ENETDMA_CHANCFG_PKTHALT_MASK    (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
685 
686 /* Interrupt Control/Status register */
687 #define ENETDMA_IR_REG(x)               (0x104 + (x) * 0x10)
688 #define ENETDMA_IR_BUFDONE_MASK         (1 << 0)
689 #define ENETDMA_IR_PKTDONE_MASK         (1 << 1)
690 #define ENETDMA_IR_NOTOWNER_MASK        (1 << 2)
691 
692 /* Interrupt Mask register */
693 #define ENETDMA_IRMASK_REG(x)           (0x108 + (x) * 0x10)
694 
695 /* Maximum Burst Length */
696 #define ENETDMA_MAXBURST_REG(x)         (0x10C + (x) * 0x10)
697 
698 /* Ring Start Address register */
699 #define ENETDMA_RSTART_REG(x)           (0x200 + (x) * 0x10)
700 
701 /* State Ram Word 2 */
702 #define ENETDMA_SRAM2_REG(x)            (0x204 + (x) * 0x10)
703 
704 /* State Ram Word 3 */
705 #define ENETDMA_SRAM3_REG(x)            (0x208 + (x) * 0x10)
706 
707 /* State Ram Word 4 */
708 #define ENETDMA_SRAM4_REG(x)            (0x20c + (x) * 0x10)
709 
710 /* Broadcom 6345 ENET DMA definitions */
711 #define ENETDMA_6345_CHANCFG_REG        (0x00)
712 
713 #define ENETDMA_6345_MAXBURST_REG       (0x40)
714 
715 #define ENETDMA_6345_RSTART_REG         (0x08)
716 
717 #define ENETDMA_6345_LEN_REG            (0x0C)
718 
719 #define ENETDMA_6345_IR_REG             (0x14)
720 
721 #define ENETDMA_6345_IRMASK_REG         (0x18)
722 
723 #define ENETDMA_6345_FC_REG             (0x1C)
724 
725 #define ENETDMA_6345_BUFALLOC_REG       (0x20)
726 
727 /* Shift down for EOP, SOP and WRAP bits */
728 #define ENETDMA_6345_DESC_SHIFT         (3)
729 
730 /*************************************************************************
731  * _REG relative to RSET_ENETDMAC
732  *************************************************************************/
733 
734 /* Channel Configuration register */
735 #define ENETDMAC_CHANCFG_REG            (0x0)
736 #define ENETDMAC_CHANCFG_EN_SHIFT       0
737 #define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMAC_CHANCFG_EN_SHIFT)
738 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT  1
739 #define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
740 #define ENETDMAC_CHANCFG_BUFHALT_SHIFT  2
741 #define ENETDMAC_CHANCFG_BUFHALT_MASK   (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
742 #define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
743 #define ENETDMAC_CHANCFG_CHAINING_MASK  (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
744 #define ENETDMAC_CHANCFG_WRAP_EN_SHIFT  3
745 #define ENETDMAC_CHANCFG_WRAP_EN_MASK   (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
746 #define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
747 #define ENETDMAC_CHANCFG_FLOWC_EN_MASK  (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
748 
749 /* Interrupt Control/Status register */
750 #define ENETDMAC_IR_REG                 (0x4)
751 #define ENETDMAC_IR_BUFDONE_MASK        (1 << 0)
752 #define ENETDMAC_IR_PKTDONE_MASK        (1 << 1)
753 #define ENETDMAC_IR_NOTOWNER_MASK       (1 << 2)
754 
755 /* Interrupt Mask register */
756 #define ENETDMAC_IRMASK_REG             (0x8)
757 
758 /* Maximum Burst Length */
759 #define ENETDMAC_MAXBURST_REG           (0xc)
760 
761 
762 /*************************************************************************
763  * _REG relative to RSET_ENETDMAS
764  *************************************************************************/
765 
766 /* Ring Start Address register */
767 #define ENETDMAS_RSTART_REG             (0x0)
768 
769 /* State Ram Word 2 */
770 #define ENETDMAS_SRAM2_REG              (0x4)
771 
772 /* State Ram Word 3 */
773 #define ENETDMAS_SRAM3_REG              (0x8)
774 
775 /* State Ram Word 4 */
776 #define ENETDMAS_SRAM4_REG              (0xc)
777 
778 
779 /*************************************************************************
780  * _REG relative to RSET_ENETSW
781  *************************************************************************/
782 
783 /* Port traffic control */
784 #define ENETSW_PTCTRL_REG(x)            (0x0 + (x))
785 #define ENETSW_PTCTRL_RXDIS_MASK        (1 << 0)
786 #define ENETSW_PTCTRL_TXDIS_MASK        (1 << 1)
787 
788 /* Switch mode register */
789 #define ENETSW_SWMODE_REG               (0xb)
790 #define ENETSW_SWMODE_FWD_EN_MASK       (1 << 1)
791 
792 /* IMP override Register */
793 #define ENETSW_IMPOV_REG                (0xe)
794 #define ENETSW_IMPOV_FORCE_MASK         (1 << 7)
795 #define ENETSW_IMPOV_TXFLOW_MASK        (1 << 5)
796 #define ENETSW_IMPOV_RXFLOW_MASK        (1 << 4)
797 #define ENETSW_IMPOV_1000_MASK          (1 << 3)
798 #define ENETSW_IMPOV_100_MASK           (1 << 2)
799 #define ENETSW_IMPOV_FDX_MASK           (1 << 1)
800 #define ENETSW_IMPOV_LINKUP_MASK        (1 << 0)
801 
802 /* Port override Register */
803 #define ENETSW_PORTOV_REG(x)            (0x58 + (x))
804 #define ENETSW_PORTOV_ENABLE_MASK       (1 << 6)
805 #define ENETSW_PORTOV_TXFLOW_MASK       (1 << 5)
806 #define ENETSW_PORTOV_RXFLOW_MASK       (1 << 4)
807 #define ENETSW_PORTOV_1000_MASK         (1 << 3)
808 #define ENETSW_PORTOV_100_MASK          (1 << 2)
809 #define ENETSW_PORTOV_FDX_MASK          (1 << 1)
810 #define ENETSW_PORTOV_LINKUP_MASK       (1 << 0)
811 
812 /* MDIO control register */
813 #define ENETSW_MDIOC_REG                (0xb0)
814 #define ENETSW_MDIOC_EXT_MASK           (1 << 16)
815 #define ENETSW_MDIOC_REG_SHIFT          20
816 #define ENETSW_MDIOC_PHYID_SHIFT        25
817 #define ENETSW_MDIOC_RD_MASK            (1 << 30)
818 #define ENETSW_MDIOC_WR_MASK            (1 << 31)
819 
820 /* MDIO data register */
821 #define ENETSW_MDIOD_REG                (0xb4)
822 
823 /* Global Management Configuration Register */
824 #define ENETSW_GMCR_REG                 (0x200)
825 #define ENETSW_GMCR_RST_MIB_MASK        (1 << 0)
826 
827 /* MIB register */
828 #define ENETSW_MIB_REG(x)               (0x2800 + (x) * 4)
829 #define ENETSW_MIB_REG_COUNT            47
830 
831 /* Jumbo control register port mask register */
832 #define ENETSW_JMBCTL_PORT_REG          (0x4004)
833 
834 /* Jumbo control mib good frame register */
835 #define ENETSW_JMBCTL_MAXSIZE_REG       (0x4008)
836 
837 
838 /*************************************************************************
839  * _REG relative to RSET_OHCI_PRIV
840  *************************************************************************/
841 
842 #define OHCI_PRIV_REG                   0x0
843 #define OHCI_PRIV_PORT1_HOST_SHIFT      0
844 #define OHCI_PRIV_PORT1_HOST_MASK       (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
845 #define OHCI_PRIV_REG_SWAP_SHIFT        3
846 #define OHCI_PRIV_REG_SWAP_MASK         (1 << OHCI_PRIV_REG_SWAP_SHIFT)
847 
848 
849 /*************************************************************************
850  * _REG relative to RSET_USBH_PRIV
851  *************************************************************************/
852 
853 #define USBH_PRIV_SWAP_6358_REG         0x0
854 #define USBH_PRIV_SWAP_6368_REG         0x1c
855 
856 #define USBH_PRIV_SWAP_USBD_SHIFT       6
857 #define USBH_PRIV_SWAP_USBD_MASK        (1 << USBH_PRIV_SWAP_USBD_SHIFT)
858 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT  4
859 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
860 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT  3
861 #define USBH_PRIV_SWAP_EHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
862 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT  1
863 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
864 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT  0
865 #define USBH_PRIV_SWAP_OHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
866 
867 #define USBH_PRIV_UTMI_CTL_6368_REG     0x10
868 #define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12
869 #define USBH_PRIV_UTMI_CTL_NODRIV_MASK  (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
870 #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT  0
871 #define USBH_PRIV_UTMI_CTL_HOSTB_MASK   (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
872 
873 #define USBH_PRIV_TEST_6358_REG         0x24
874 #define USBH_PRIV_TEST_6368_REG         0x14
875 
876 #define USBH_PRIV_SETUP_6368_REG        0x28
877 #define USBH_PRIV_SETUP_IOC_SHIFT       4
878 #define USBH_PRIV_SETUP_IOC_MASK        (1 << USBH_PRIV_SETUP_IOC_SHIFT)
879 
880 
881 /*************************************************************************
882  * _REG relative to RSET_USBD
883  *************************************************************************/
884 
885 /* General control */
886 #define USBD_CONTROL_REG                0x00
887 #define USBD_CONTROL_TXZLENINS_SHIFT    14
888 #define USBD_CONTROL_TXZLENINS_MASK     (1 << USBD_CONTROL_TXZLENINS_SHIFT)
889 #define USBD_CONTROL_AUTO_CSRS_SHIFT    13
890 #define USBD_CONTROL_AUTO_CSRS_MASK     (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
891 #define USBD_CONTROL_RXZSCFG_SHIFT      12
892 #define USBD_CONTROL_RXZSCFG_MASK       (1 << USBD_CONTROL_RXZSCFG_SHIFT)
893 #define USBD_CONTROL_INIT_SEL_SHIFT     8
894 #define USBD_CONTROL_INIT_SEL_MASK      (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
895 #define USBD_CONTROL_FIFO_RESET_SHIFT   6
896 #define USBD_CONTROL_FIFO_RESET_MASK    (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
897 #define USBD_CONTROL_SETUPERRLOCK_SHIFT 5
898 #define USBD_CONTROL_SETUPERRLOCK_MASK  (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
899 #define USBD_CONTROL_DONE_CSRS_SHIFT    0
900 #define USBD_CONTROL_DONE_CSRS_MASK     (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
901 
902 /* Strap options */
903 #define USBD_STRAPS_REG                 0x04
904 #define USBD_STRAPS_APP_SELF_PWR_SHIFT  10
905 #define USBD_STRAPS_APP_SELF_PWR_MASK   (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
906 #define USBD_STRAPS_APP_DISCON_SHIFT    9
907 #define USBD_STRAPS_APP_DISCON_MASK     (1 << USBD_STRAPS_APP_DISCON_SHIFT)
908 #define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8
909 #define USBD_STRAPS_APP_CSRPRGSUP_MASK  (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
910 #define USBD_STRAPS_APP_RMTWKUP_SHIFT   6
911 #define USBD_STRAPS_APP_RMTWKUP_MASK    (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
912 #define USBD_STRAPS_APP_RAM_IF_SHIFT    7
913 #define USBD_STRAPS_APP_RAM_IF_MASK     (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
914 #define USBD_STRAPS_APP_8BITPHY_SHIFT   2
915 #define USBD_STRAPS_APP_8BITPHY_MASK    (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
916 #define USBD_STRAPS_SPEED_SHIFT         0
917 #define USBD_STRAPS_SPEED_MASK          (3 << USBD_STRAPS_SPEED_SHIFT)
918 
919 /* Stall control */
920 #define USBD_STALL_REG                  0x08
921 #define USBD_STALL_UPDATE_SHIFT         7
922 #define USBD_STALL_UPDATE_MASK          (1 << USBD_STALL_UPDATE_SHIFT)
923 #define USBD_STALL_ENABLE_SHIFT         6
924 #define USBD_STALL_ENABLE_MASK          (1 << USBD_STALL_ENABLE_SHIFT)
925 #define USBD_STALL_EPNUM_SHIFT          0
926 #define USBD_STALL_EPNUM_MASK           (0xf << USBD_STALL_EPNUM_SHIFT)
927 
928 /* General status */
929 #define USBD_STATUS_REG                 0x0c
930 #define USBD_STATUS_SOF_SHIFT           16
931 #define USBD_STATUS_SOF_MASK            (0x7ff << USBD_STATUS_SOF_SHIFT)
932 #define USBD_STATUS_SPD_SHIFT           12
933 #define USBD_STATUS_SPD_MASK            (3 << USBD_STATUS_SPD_SHIFT)
934 #define USBD_STATUS_ALTINTF_SHIFT       8
935 #define USBD_STATUS_ALTINTF_MASK        (0xf << USBD_STATUS_ALTINTF_SHIFT)
936 #define USBD_STATUS_INTF_SHIFT          4
937 #define USBD_STATUS_INTF_MASK           (0xf << USBD_STATUS_INTF_SHIFT)
938 #define USBD_STATUS_CFG_SHIFT           0
939 #define USBD_STATUS_CFG_MASK            (0xf << USBD_STATUS_CFG_SHIFT)
940 
941 /* Other events */
942 #define USBD_EVENTS_REG                 0x10
943 #define USBD_EVENTS_USB_LINK_SHIFT      10
944 #define USBD_EVENTS_USB_LINK_MASK       (1 << USBD_EVENTS_USB_LINK_SHIFT)
945 
946 /* IRQ status */
947 #define USBD_EVENT_IRQ_STATUS_REG       0x14
948 
949 /* IRQ level (2 bits per IRQ event) */
950 #define USBD_EVENT_IRQ_CFG_HI_REG       0x18
951 
952 #define USBD_EVENT_IRQ_CFG_LO_REG       0x1c
953 
954 #define USBD_EVENT_IRQ_CFG_SHIFT(x)     ((x & 0xf) << 1)
955 #define USBD_EVENT_IRQ_CFG_MASK(x)      (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
956 #define USBD_EVENT_IRQ_CFG_RISING(x)    (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
957 #define USBD_EVENT_IRQ_CFG_FALLING(x)   (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
958 
959 /* IRQ mask (1=unmasked) */
960 #define USBD_EVENT_IRQ_MASK_REG         0x20
961 
962 /* IRQ bits */
963 #define USBD_EVENT_IRQ_USB_LINK         10
964 #define USBD_EVENT_IRQ_SETCFG           9
965 #define USBD_EVENT_IRQ_SETINTF          8
966 #define USBD_EVENT_IRQ_ERRATIC_ERR      7
967 #define USBD_EVENT_IRQ_SET_CSRS         6
968 #define USBD_EVENT_IRQ_SUSPEND          5
969 #define USBD_EVENT_IRQ_EARLY_SUSPEND    4
970 #define USBD_EVENT_IRQ_SOF              3
971 #define USBD_EVENT_IRQ_ENUM_ON          2
972 #define USBD_EVENT_IRQ_SETUP            1
973 #define USBD_EVENT_IRQ_USB_RESET        0
974 
975 /* TX FIFO partitioning */
976 #define USBD_TXFIFO_CONFIG_REG          0x40
977 #define USBD_TXFIFO_CONFIG_END_SHIFT    16
978 #define USBD_TXFIFO_CONFIG_END_MASK     (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
979 #define USBD_TXFIFO_CONFIG_START_SHIFT  0
980 #define USBD_TXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
981 
982 /* RX FIFO partitioning */
983 #define USBD_RXFIFO_CONFIG_REG          0x44
984 #define USBD_RXFIFO_CONFIG_END_SHIFT    16
985 #define USBD_RXFIFO_CONFIG_END_MASK     (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
986 #define USBD_RXFIFO_CONFIG_START_SHIFT  0
987 #define USBD_RXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
988 
989 /* TX FIFO/endpoint configuration */
990 #define USBD_TXFIFO_EPSIZE_REG          0x48
991 
992 /* RX FIFO/endpoint configuration */
993 #define USBD_RXFIFO_EPSIZE_REG          0x4c
994 
995 /* Endpoint<->DMA mappings */
996 #define USBD_EPNUM_TYPEMAP_REG          0x50
997 #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT   8
998 #define USBD_EPNUM_TYPEMAP_TYPE_MASK    (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
999 #define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
1000 #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK  (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
1001 
1002 /* Misc per-endpoint settings */
1003 #define USBD_CSR_SETUPADDR_REG          0x80
1004 #define USBD_CSR_SETUPADDR_DEF          0xb550
1005 
1006 #define USBD_CSR_EP_REG(x)              (0x84 + (x) * 4)
1007 #define USBD_CSR_EP_MAXPKT_SHIFT        19
1008 #define USBD_CSR_EP_MAXPKT_MASK         (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
1009 #define USBD_CSR_EP_ALTIFACE_SHIFT      15
1010 #define USBD_CSR_EP_ALTIFACE_MASK       (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
1011 #define USBD_CSR_EP_IFACE_SHIFT         11
1012 #define USBD_CSR_EP_IFACE_MASK          (0xf << USBD_CSR_EP_IFACE_SHIFT)
1013 #define USBD_CSR_EP_CFG_SHIFT           7
1014 #define USBD_CSR_EP_CFG_MASK            (0xf << USBD_CSR_EP_CFG_SHIFT)
1015 #define USBD_CSR_EP_TYPE_SHIFT          5
1016 #define USBD_CSR_EP_TYPE_MASK           (3 << USBD_CSR_EP_TYPE_SHIFT)
1017 #define USBD_CSR_EP_DIR_SHIFT           4
1018 #define USBD_CSR_EP_DIR_MASK            (1 << USBD_CSR_EP_DIR_SHIFT)
1019 #define USBD_CSR_EP_LOG_SHIFT           0
1020 #define USBD_CSR_EP_LOG_MASK            (0xf << USBD_CSR_EP_LOG_SHIFT)
1021 
1022 
1023 /*************************************************************************
1024  * _REG relative to RSET_MPI
1025  *************************************************************************/
1026 
1027 /* well known (hard wired) chip select */
1028 #define MPI_CS_PCMCIA_COMMON            4
1029 #define MPI_CS_PCMCIA_ATTR              5
1030 #define MPI_CS_PCMCIA_IO                6
1031 
1032 /* Chip select base register */
1033 #define MPI_CSBASE_REG(x)               (0x0 + (x) * 8)
1034 #define MPI_CSBASE_BASE_SHIFT           13
1035 #define MPI_CSBASE_BASE_MASK            (0x1ffff << MPI_CSBASE_BASE_SHIFT)
1036 #define MPI_CSBASE_SIZE_SHIFT           0
1037 #define MPI_CSBASE_SIZE_MASK            (0xf << MPI_CSBASE_SIZE_SHIFT)
1038 
1039 #define MPI_CSBASE_SIZE_8K              0
1040 #define MPI_CSBASE_SIZE_16K             1
1041 #define MPI_CSBASE_SIZE_32K             2
1042 #define MPI_CSBASE_SIZE_64K             3
1043 #define MPI_CSBASE_SIZE_128K            4
1044 #define MPI_CSBASE_SIZE_256K            5
1045 #define MPI_CSBASE_SIZE_512K            6
1046 #define MPI_CSBASE_SIZE_1M              7
1047 #define MPI_CSBASE_SIZE_2M              8
1048 #define MPI_CSBASE_SIZE_4M              9
1049 #define MPI_CSBASE_SIZE_8M              10
1050 #define MPI_CSBASE_SIZE_16M             11
1051 #define MPI_CSBASE_SIZE_32M             12
1052 #define MPI_CSBASE_SIZE_64M             13
1053 #define MPI_CSBASE_SIZE_128M            14
1054 #define MPI_CSBASE_SIZE_256M            15
1055 
1056 /* Chip select control register */
1057 #define MPI_CSCTL_REG(x)                (0x4 + (x) * 8)
1058 #define MPI_CSCTL_ENABLE_MASK           (1 << 0)
1059 #define MPI_CSCTL_WAIT_SHIFT            1
1060 #define MPI_CSCTL_WAIT_MASK             (0x7 << MPI_CSCTL_WAIT_SHIFT)
1061 #define MPI_CSCTL_DATA16_MASK           (1 << 4)
1062 #define MPI_CSCTL_SYNCMODE_MASK         (1 << 7)
1063 #define MPI_CSCTL_TSIZE_MASK            (1 << 8)
1064 #define MPI_CSCTL_ENDIANSWAP_MASK       (1 << 10)
1065 #define MPI_CSCTL_SETUP_SHIFT           16
1066 #define MPI_CSCTL_SETUP_MASK            (0xf << MPI_CSCTL_SETUP_SHIFT)
1067 #define MPI_CSCTL_HOLD_SHIFT            20
1068 #define MPI_CSCTL_HOLD_MASK             (0xf << MPI_CSCTL_HOLD_SHIFT)
1069 
1070 /* PCI registers */
1071 #define MPI_SP0_RANGE_REG               0x100
1072 #define MPI_SP0_REMAP_REG               0x104
1073 #define MPI_SP0_REMAP_ENABLE_MASK       (1 << 0)
1074 #define MPI_SP1_RANGE_REG               0x10C
1075 #define MPI_SP1_REMAP_REG               0x110
1076 #define MPI_SP1_REMAP_ENABLE_MASK       (1 << 0)
1077 
1078 #define MPI_L2PCFG_REG                  0x11C
1079 #define MPI_L2PCFG_CFG_TYPE_SHIFT       0
1080 #define MPI_L2PCFG_CFG_TYPE_MASK        (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
1081 #define MPI_L2PCFG_REG_SHIFT            2
1082 #define MPI_L2PCFG_REG_MASK             (0x3f << MPI_L2PCFG_REG_SHIFT)
1083 #define MPI_L2PCFG_FUNC_SHIFT           8
1084 #define MPI_L2PCFG_FUNC_MASK            (0x7 << MPI_L2PCFG_FUNC_SHIFT)
1085 #define MPI_L2PCFG_DEVNUM_SHIFT         11
1086 #define MPI_L2PCFG_DEVNUM_MASK          (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
1087 #define MPI_L2PCFG_CFG_USEREG_MASK      (1 << 30)
1088 #define MPI_L2PCFG_CFG_SEL_MASK         (1 << 31)
1089 
1090 #define MPI_L2PMEMRANGE1_REG            0x120
1091 #define MPI_L2PMEMBASE1_REG             0x124
1092 #define MPI_L2PMEMREMAP1_REG            0x128
1093 #define MPI_L2PMEMRANGE2_REG            0x12C
1094 #define MPI_L2PMEMBASE2_REG             0x130
1095 #define MPI_L2PMEMREMAP2_REG            0x134
1096 #define MPI_L2PIORANGE_REG              0x138
1097 #define MPI_L2PIOBASE_REG               0x13C
1098 #define MPI_L2PIOREMAP_REG              0x140
1099 #define MPI_L2P_BASE_MASK               (0xffff8000)
1100 #define MPI_L2PREMAP_ENABLED_MASK       (1 << 0)
1101 #define MPI_L2PREMAP_IS_CARDBUS_MASK    (1 << 2)
1102 
1103 #define MPI_PCIMODESEL_REG              0x144
1104 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
1105 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
1106 #define MPI_PCIMODESEL_EXT_ARB_MASK     (1 << 2)
1107 #define MPI_PCIMODESEL_PREFETCH_SHIFT   4
1108 #define MPI_PCIMODESEL_PREFETCH_MASK    (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
1109 
1110 #define MPI_LOCBUSCTL_REG               0x14C
1111 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK  (1 << 0)
1112 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK   (1 << 1)
1113 
1114 #define MPI_LOCINT_REG                  0x150
1115 #define MPI_LOCINT_MASK(x)              (1 << (x + 16))
1116 #define MPI_LOCINT_STAT(x)              (1 << (x))
1117 #define MPI_LOCINT_DIR_FAILED           6
1118 #define MPI_LOCINT_EXT_PCI_INT          7
1119 #define MPI_LOCINT_SERR                 8
1120 #define MPI_LOCINT_CSERR                9
1121 
1122 #define MPI_PCICFGCTL_REG               0x178
1123 #define MPI_PCICFGCTL_CFGADDR_SHIFT     2
1124 #define MPI_PCICFGCTL_CFGADDR_MASK      (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
1125 #define MPI_PCICFGCTL_WRITEEN_MASK      (1 << 7)
1126 
1127 #define MPI_PCICFGDATA_REG              0x17C
1128 
1129 /* PCI host bridge custom register */
1130 #define BCMPCI_REG_TIMERS               0x40
1131 #define REG_TIMER_TRDY_SHIFT            0
1132 #define REG_TIMER_TRDY_MASK             (0xff << REG_TIMER_TRDY_SHIFT)
1133 #define REG_TIMER_RETRY_SHIFT           8
1134 #define REG_TIMER_RETRY_MASK            (0xff << REG_TIMER_RETRY_SHIFT)
1135 
1136 
1137 /*************************************************************************
1138  * _REG relative to RSET_PCMCIA
1139  *************************************************************************/
1140 
1141 #define PCMCIA_C1_REG                   0x0
1142 #define PCMCIA_C1_CD1_MASK              (1 << 0)
1143 #define PCMCIA_C1_CD2_MASK              (1 << 1)
1144 #define PCMCIA_C1_VS1_MASK              (1 << 2)
1145 #define PCMCIA_C1_VS2_MASK              (1 << 3)
1146 #define PCMCIA_C1_VS1OE_MASK            (1 << 6)
1147 #define PCMCIA_C1_VS2OE_MASK            (1 << 7)
1148 #define PCMCIA_C1_CBIDSEL_SHIFT         (8)
1149 #define PCMCIA_C1_CBIDSEL_MASK          (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
1150 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK   (1 << 13)
1151 #define PCMCIA_C1_EN_PCMCIA_MASK        (1 << 14)
1152 #define PCMCIA_C1_EN_CARDBUS_MASK       (1 << 15)
1153 #define PCMCIA_C1_RESET_MASK            (1 << 18)
1154 
1155 #define PCMCIA_C2_REG                   0x8
1156 #define PCMCIA_C2_DATA16_MASK           (1 << 0)
1157 #define PCMCIA_C2_BYTESWAP_MASK         (1 << 1)
1158 #define PCMCIA_C2_RWCOUNT_SHIFT         2
1159 #define PCMCIA_C2_RWCOUNT_MASK          (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
1160 #define PCMCIA_C2_INACTIVE_SHIFT        8
1161 #define PCMCIA_C2_INACTIVE_MASK         (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
1162 #define PCMCIA_C2_SETUP_SHIFT           16
1163 #define PCMCIA_C2_SETUP_MASK            (0x3f << PCMCIA_C2_SETUP_SHIFT)
1164 #define PCMCIA_C2_HOLD_SHIFT            24
1165 #define PCMCIA_C2_HOLD_MASK             (0x3f << PCMCIA_C2_HOLD_SHIFT)
1166 
1167 
1168 /*************************************************************************
1169  * _REG relative to RSET_SDRAM
1170  *************************************************************************/
1171 
1172 #define SDRAM_CFG_REG                   0x0
1173 #define SDRAM_CFG_ROW_SHIFT             4
1174 #define SDRAM_CFG_ROW_MASK              (0x3 << SDRAM_CFG_ROW_SHIFT)
1175 #define SDRAM_CFG_COL_SHIFT             6
1176 #define SDRAM_CFG_COL_MASK              (0x3 << SDRAM_CFG_COL_SHIFT)
1177 #define SDRAM_CFG_32B_SHIFT             10
1178 #define SDRAM_CFG_32B_MASK              (1 << SDRAM_CFG_32B_SHIFT)
1179 #define SDRAM_CFG_BANK_SHIFT            13
1180 #define SDRAM_CFG_BANK_MASK             (1 << SDRAM_CFG_BANK_SHIFT)
1181 
1182 #define SDRAM_MBASE_REG                 0xc
1183 
1184 #define SDRAM_PRIO_REG                  0x2C
1185 #define SDRAM_PRIO_MIPS_SHIFT           29
1186 #define SDRAM_PRIO_MIPS_MASK            (1 << SDRAM_PRIO_MIPS_SHIFT)
1187 #define SDRAM_PRIO_ADSL_SHIFT           30
1188 #define SDRAM_PRIO_ADSL_MASK            (1 << SDRAM_PRIO_ADSL_SHIFT)
1189 #define SDRAM_PRIO_EN_SHIFT             31
1190 #define SDRAM_PRIO_EN_MASK              (1 << SDRAM_PRIO_EN_SHIFT)
1191 
1192 
1193 /*************************************************************************
1194  * _REG relative to RSET_MEMC
1195  *************************************************************************/
1196 
1197 #define MEMC_CFG_REG                    0x4
1198 #define MEMC_CFG_32B_SHIFT              1
1199 #define MEMC_CFG_32B_MASK               (1 << MEMC_CFG_32B_SHIFT)
1200 #define MEMC_CFG_COL_SHIFT              3
1201 #define MEMC_CFG_COL_MASK               (0x3 << MEMC_CFG_COL_SHIFT)
1202 #define MEMC_CFG_ROW_SHIFT              6
1203 #define MEMC_CFG_ROW_MASK               (0x3 << MEMC_CFG_ROW_SHIFT)
1204 
1205 
1206 /*************************************************************************
1207  * _REG relative to RSET_DDR
1208  *************************************************************************/
1209 
1210 #define DDR_CSEND_REG                   0x8
1211 
1212 #define DDR_DMIPSPLLCFG_REG             0x18
1213 #define DMIPSPLLCFG_M1_SHIFT            0
1214 #define DMIPSPLLCFG_M1_MASK             (0xff << DMIPSPLLCFG_M1_SHIFT)
1215 #define DMIPSPLLCFG_N1_SHIFT            23
1216 #define DMIPSPLLCFG_N1_MASK             (0x3f << DMIPSPLLCFG_N1_SHIFT)
1217 #define DMIPSPLLCFG_N2_SHIFT            29
1218 #define DMIPSPLLCFG_N2_MASK             (0x7 << DMIPSPLLCFG_N2_SHIFT)
1219 
1220 #define DDR_DMIPSPLLCFG_6368_REG        0x20
1221 #define DMIPSPLLCFG_6368_P1_SHIFT       0
1222 #define DMIPSPLLCFG_6368_P1_MASK        (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
1223 #define DMIPSPLLCFG_6368_P2_SHIFT       4
1224 #define DMIPSPLLCFG_6368_P2_MASK        (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
1225 #define DMIPSPLLCFG_6368_NDIV_SHIFT     16
1226 #define DMIPSPLLCFG_6368_NDIV_MASK      (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
1227 
1228 #define DDR_DMIPSPLLDIV_6368_REG        0x24
1229 #define DMIPSPLLDIV_6368_MDIV_SHIFT     0
1230 #define DMIPSPLLDIV_6368_MDIV_MASK      (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
1231 
1232 
1233 /*************************************************************************
1234  * _REG relative to RSET_M2M
1235  *************************************************************************/
1236 
1237 #define M2M_RX                          0
1238 #define M2M_TX                          1
1239 
1240 #define M2M_SRC_REG(x)                  ((x) * 0x40 + 0x00)
1241 #define M2M_DST_REG(x)                  ((x) * 0x40 + 0x04)
1242 #define M2M_SIZE_REG(x)                 ((x) * 0x40 + 0x08)
1243 
1244 #define M2M_CTRL_REG(x)                 ((x) * 0x40 + 0x0c)
1245 #define M2M_CTRL_ENABLE_MASK            (1 << 0)
1246 #define M2M_CTRL_IRQEN_MASK             (1 << 1)
1247 #define M2M_CTRL_ERROR_CLR_MASK         (1 << 6)
1248 #define M2M_CTRL_DONE_CLR_MASK          (1 << 7)
1249 #define M2M_CTRL_NOINC_MASK             (1 << 8)
1250 #define M2M_CTRL_PCMCIASWAP_MASK        (1 << 9)
1251 #define M2M_CTRL_SWAPBYTE_MASK          (1 << 10)
1252 #define M2M_CTRL_ENDIAN_MASK            (1 << 11)
1253 
1254 #define M2M_STAT_REG(x)                 ((x) * 0x40 + 0x10)
1255 #define M2M_STAT_DONE                   (1 << 0)
1256 #define M2M_STAT_ERROR                  (1 << 1)
1257 
1258 #define M2M_SRCID_REG(x)                ((x) * 0x40 + 0x14)
1259 #define M2M_DSTID_REG(x)                ((x) * 0x40 + 0x18)
1260 
1261 /*************************************************************************
1262  * _REG relative to RSET_SPI
1263  *************************************************************************/
1264 
1265 /* BCM 6338/6348 SPI core */
1266 #define SPI_6348_CMD                    0x00    /* 16-bits register */
1267 #define SPI_6348_INT_STATUS             0x02
1268 #define SPI_6348_INT_MASK_ST            0x03
1269 #define SPI_6348_INT_MASK               0x04
1270 #define SPI_6348_ST                     0x05
1271 #define SPI_6348_CLK_CFG                0x06
1272 #define SPI_6348_FILL_BYTE              0x07
1273 #define SPI_6348_MSG_TAIL               0x09
1274 #define SPI_6348_RX_TAIL                0x0b
1275 #define SPI_6348_MSG_CTL                0x40    /* 8-bits register */
1276 #define SPI_6348_MSG_CTL_WIDTH          8
1277 #define SPI_6348_MSG_DATA               0x41
1278 #define SPI_6348_MSG_DATA_SIZE          0x3f
1279 #define SPI_6348_RX_DATA                0x80
1280 #define SPI_6348_RX_DATA_SIZE           0x3f
1281 
1282 /* BCM 3368/6358/6262/6368 SPI core */
1283 #define SPI_6358_MSG_CTL                0x00    /* 16-bits register */
1284 #define SPI_6358_MSG_CTL_WIDTH          16
1285 #define SPI_6358_MSG_DATA               0x02
1286 #define SPI_6358_MSG_DATA_SIZE          0x21e
1287 #define SPI_6358_RX_DATA                0x400
1288 #define SPI_6358_RX_DATA_SIZE           0x220
1289 #define SPI_6358_CMD                    0x700   /* 16-bits register */
1290 #define SPI_6358_INT_STATUS             0x702
1291 #define SPI_6358_INT_MASK_ST            0x703
1292 #define SPI_6358_INT_MASK               0x704
1293 #define SPI_6358_ST                     0x705
1294 #define SPI_6358_CLK_CFG                0x706
1295 #define SPI_6358_FILL_BYTE              0x707
1296 #define SPI_6358_MSG_TAIL               0x709
1297 #define SPI_6358_RX_TAIL                0x70B
1298 
1299 /* Shared SPI definitions */
1300 
1301 /* Message configuration */
1302 #define SPI_FD_RW                       0x00
1303 #define SPI_HD_W                        0x01
1304 #define SPI_HD_R                        0x02
1305 #define SPI_BYTE_CNT_SHIFT              0
1306 #define SPI_6348_MSG_TYPE_SHIFT         6
1307 #define SPI_6358_MSG_TYPE_SHIFT         14
1308 
1309 /* Command */
1310 #define SPI_CMD_NOOP                    0x00
1311 #define SPI_CMD_SOFT_RESET              0x01
1312 #define SPI_CMD_HARD_RESET              0x02
1313 #define SPI_CMD_START_IMMEDIATE         0x03
1314 #define SPI_CMD_COMMAND_SHIFT           0
1315 #define SPI_CMD_COMMAND_MASK            0x000f
1316 #define SPI_CMD_DEVICE_ID_SHIFT         4
1317 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
1318 #define SPI_CMD_ONE_BYTE_SHIFT          11
1319 #define SPI_CMD_ONE_WIRE_SHIFT          12
1320 #define SPI_DEV_ID_0                    0
1321 #define SPI_DEV_ID_1                    1
1322 #define SPI_DEV_ID_2                    2
1323 #define SPI_DEV_ID_3                    3
1324 
1325 /* Interrupt mask */
1326 #define SPI_INTR_CMD_DONE               0x01
1327 #define SPI_INTR_RX_OVERFLOW            0x02
1328 #define SPI_INTR_TX_UNDERFLOW           0x04
1329 #define SPI_INTR_TX_OVERFLOW            0x08
1330 #define SPI_INTR_RX_UNDERFLOW           0x10
1331 #define SPI_INTR_CLEAR_ALL              0x1f
1332 
1333 /* Status */
1334 #define SPI_RX_EMPTY                    0x02
1335 #define SPI_CMD_BUSY                    0x04
1336 #define SPI_SERIAL_BUSY                 0x08
1337 
1338 /* Clock configuration */
1339 #define SPI_CLK_20MHZ                   0x00
1340 #define SPI_CLK_0_391MHZ                0x01
1341 #define SPI_CLK_0_781MHZ                0x02 /* default */
1342 #define SPI_CLK_1_563MHZ                0x03
1343 #define SPI_CLK_3_125MHZ                0x04
1344 #define SPI_CLK_6_250MHZ                0x05
1345 #define SPI_CLK_12_50MHZ                0x06
1346 #define SPI_CLK_MASK                    0x07
1347 #define SPI_SSOFFTIME_MASK              0x38
1348 #define SPI_SSOFFTIME_SHIFT             3
1349 #define SPI_BYTE_SWAP                   0x80
1350 
1351 /*************************************************************************
1352  * _REG relative to RSET_MISC
1353  *************************************************************************/
1354 #define MISC_SERDES_CTRL_6328_REG       0x0
1355 #define MISC_SERDES_CTRL_6362_REG       0x4
1356 #define SERDES_PCIE_EN                  (1 << 0)
1357 #define SERDES_PCIE_EXD_EN              (1 << 15)
1358 
1359 #define MISC_STRAPBUS_6362_REG          0x14
1360 #define STRAPBUS_6362_FCVO_SHIFT        1
1361 #define STRAPBUS_6362_HSSPI_CLK_FAST    (1 << 13)
1362 #define STRAPBUS_6362_FCVO_MASK         (0x1f << STRAPBUS_6362_FCVO_SHIFT)
1363 #define STRAPBUS_6362_BOOT_SEL_SERIAL   (1 << 15)
1364 #define STRAPBUS_6362_BOOT_SEL_NAND     (0 << 15)
1365 
1366 #define MISC_STRAPBUS_6328_REG          0x240
1367 #define STRAPBUS_6328_FCVO_SHIFT        7
1368 #define STRAPBUS_6328_FCVO_MASK         (0x1f << STRAPBUS_6328_FCVO_SHIFT)
1369 #define STRAPBUS_6328_BOOT_SEL_SERIAL   (1 << 28)
1370 #define STRAPBUS_6328_BOOT_SEL_NAND     (0 << 28)
1371 
1372 /*************************************************************************
1373  * _REG relative to RSET_PCIE
1374  *************************************************************************/
1375 
1376 #define PCIE_CONFIG2_REG                0x408
1377 #define CONFIG2_BAR1_SIZE_EN            1
1378 #define CONFIG2_BAR1_SIZE_MASK          0xf
1379 
1380 #define PCIE_IDVAL3_REG                 0x43c
1381 #define IDVAL3_CLASS_CODE_MASK          0xffffff
1382 #define IDVAL3_SUBCLASS_SHIFT           8
1383 #define IDVAL3_CLASS_SHIFT              16
1384 
1385 #define PCIE_DLSTATUS_REG               0x1048
1386 #define DLSTATUS_PHYLINKUP              (1 << 13)
1387 
1388 #define PCIE_BRIDGE_OPT1_REG            0x2820
1389 #define OPT1_RD_BE_OPT_EN               (1 << 7)
1390 #define OPT1_RD_REPLY_BE_FIX_EN         (1 << 9)
1391 #define OPT1_PCIE_BRIDGE_HOLE_DET_EN    (1 << 11)
1392 #define OPT1_L1_INT_STATUS_MASK_POL     (1 << 12)
1393 
1394 #define PCIE_BRIDGE_OPT2_REG            0x2824
1395 #define OPT2_UBUS_UR_DECODE_DIS         (1 << 2)
1396 #define OPT2_TX_CREDIT_CHK_EN           (1 << 4)
1397 #define OPT2_CFG_TYPE1_BD_SEL           (1 << 7)
1398 #define OPT2_CFG_TYPE1_BUS_NO_SHIFT     16
1399 #define OPT2_CFG_TYPE1_BUS_NO_MASK      (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
1400 
1401 #define PCIE_BRIDGE_BAR0_BASEMASK_REG   0x2828
1402 #define PCIE_BRIDGE_BAR1_BASEMASK_REG   0x2830
1403 #define BASEMASK_REMAP_EN               (1 << 0)
1404 #define BASEMASK_SWAP_EN                (1 << 1)
1405 #define BASEMASK_MASK_SHIFT             4
1406 #define BASEMASK_MASK_MASK              (0xfff << BASEMASK_MASK_SHIFT)
1407 #define BASEMASK_BASE_SHIFT             20
1408 #define BASEMASK_BASE_MASK              (0xfff << BASEMASK_BASE_SHIFT)
1409 
1410 #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
1411 #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
1412 #define REBASE_ADDR_BASE_SHIFT          20
1413 #define REBASE_ADDR_BASE_MASK           (0xfff << REBASE_ADDR_BASE_SHIFT)
1414 
1415 #define PCIE_BRIDGE_RC_INT_MASK_REG     0x2854
1416 #define PCIE_RC_INT_A                   (1 << 0)
1417 #define PCIE_RC_INT_B                   (1 << 1)
1418 #define PCIE_RC_INT_C                   (1 << 2)
1419 #define PCIE_RC_INT_D                   (1 << 3)
1420 
1421 #define PCIE_DEVICE_OFFSET              0x8000
1422 
1423 /*************************************************************************
1424  * _REG relative to RSET_OTP
1425  *************************************************************************/
1426 
1427 #define OTP_USER_BITS_6328_REG(i)       (0x20 + (i) * 4)
1428 #define   OTP_6328_REG3_TP1_DISABLED    BIT(9)
1429 
1430 #endif /* BCM63XX_REGS_H_ */
1431 

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