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TOMOYO Linux Cross Reference
Linux/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h

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  1 /*
  2  * This program is free software; you can redistribute it and/or modify it
  3  * under the terms of the GNU General Public License version 2 as published
  4  * by the Free Software Foundation.
  5  *
  6  * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  7  */
  8 
  9 #ifndef _LTQ_FALCON_H__
 10 #define _LTQ_FALCON_H__
 11 
 12 #ifdef CONFIG_SOC_FALCON
 13 
 14 #include <linux/pinctrl/pinctrl.h>
 15 #include <lantiq.h>
 16 
 17 /* Chip IDs */
 18 #define SOC_ID_FALCON           0x01B8
 19 
 20 /* SoC Types */
 21 #define SOC_TYPE_FALCON         0x01
 22 
 23 /*
 24  * during early_printk no ioremap possible at this early stage
 25  * lets use KSEG1 instead
 26  */
 27 #define LTQ_ASC0_BASE_ADDR      0x1E100C00
 28 #define LTQ_EARLY_ASC           KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
 29 
 30 /* WDT */
 31 #define LTQ_RST_CAUSE_WDTRST    0x0002
 32 
 33 /* CHIP ID */
 34 #define LTQ_STATUS_BASE_ADDR    0x1E802000
 35 
 36 #define FALCON_CHIPID           ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
 37 #define FALCON_CHIPTYPE         ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
 38 #define FALCON_CHIPCONF         ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
 39 
 40 /* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
 41 #define SYSCTL_SYS1             0
 42 #define SYSCTL_SYSETH           1
 43 #define SYSCTL_SYSGPE           2
 44 
 45 /* BOOT_SEL - find what boot media we have */
 46 #define BS_FLASH                0x1
 47 #define BS_SPI                  0x4
 48 
 49 /* global register ranges */
 50 extern __iomem void *ltq_ebu_membase;
 51 extern __iomem void *ltq_sys1_membase;
 52 #define ltq_ebu_w32(x, y)       ltq_w32((x), ltq_ebu_membase + (y))
 53 #define ltq_ebu_r32(x)          ltq_r32(ltq_ebu_membase + (x))
 54 
 55 #define ltq_sys1_w32(x, y)      ltq_w32((x), ltq_sys1_membase + (y))
 56 #define ltq_sys1_r32(x)         ltq_r32(ltq_sys1_membase + (x))
 57 #define ltq_sys1_w32_mask(clear, set, reg)   \
 58         ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
 59 
 60 /* allow the gpio and pinctrl drivers to talk to eachother */
 61 extern int pinctrl_falcon_get_range_size(int id);
 62 extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
 63 
 64 /*
 65  * to keep the irq code generic we need to define this to 0 as falcon
 66  * has no EIU/EBU
 67  */
 68 #define LTQ_EBU_PCC_ISTAT       0
 69 
 70 #endif /* CONFIG_SOC_FALCON */
 71 #endif /* _LTQ_XWAY_H__ */
 72 

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