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TOMOYO Linux Cross Reference
Linux/arch/mips/include/asm/mipsregs.h

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
  7  * Copyright (C) 2000 Silicon Graphics, Inc.
  8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
  9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
 11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
 12  */
 13 #ifndef _ASM_MIPSREGS_H
 14 #define _ASM_MIPSREGS_H
 15 
 16 #include <linux/linkage.h>
 17 #include <linux/types.h>
 18 #include <asm/hazards.h>
 19 #include <asm/war.h>
 20 
 21 /*
 22  * The following macros are especially useful for __asm__
 23  * inline assembler.
 24  */
 25 #ifndef __STR
 26 #define __STR(x) #x
 27 #endif
 28 #ifndef STR
 29 #define STR(x) __STR(x)
 30 #endif
 31 
 32 /*
 33  *  Configure language
 34  */
 35 #ifdef __ASSEMBLY__
 36 #define _ULCAST_
 37 #else
 38 #define _ULCAST_ (unsigned long)
 39 #endif
 40 
 41 /*
 42  * Coprocessor 0 register names
 43  */
 44 #define CP0_INDEX $0
 45 #define CP0_RANDOM $1
 46 #define CP0_ENTRYLO0 $2
 47 #define CP0_ENTRYLO1 $3
 48 #define CP0_CONF $3
 49 #define CP0_CONTEXT $4
 50 #define CP0_PAGEMASK $5
 51 #define CP0_WIRED $6
 52 #define CP0_INFO $7
 53 #define CP0_BADVADDR $8
 54 #define CP0_COUNT $9
 55 #define CP0_ENTRYHI $10
 56 #define CP0_COMPARE $11
 57 #define CP0_STATUS $12
 58 #define CP0_CAUSE $13
 59 #define CP0_EPC $14
 60 #define CP0_PRID $15
 61 #define CP0_CONFIG $16
 62 #define CP0_LLADDR $17
 63 #define CP0_WATCHLO $18
 64 #define CP0_WATCHHI $19
 65 #define CP0_XCONTEXT $20
 66 #define CP0_FRAMEMASK $21
 67 #define CP0_DIAGNOSTIC $22
 68 #define CP0_DEBUG $23
 69 #define CP0_DEPC $24
 70 #define CP0_PERFORMANCE $25
 71 #define CP0_ECC $26
 72 #define CP0_CACHEERR $27
 73 #define CP0_TAGLO $28
 74 #define CP0_TAGHI $29
 75 #define CP0_ERROREPC $30
 76 #define CP0_DESAVE $31
 77 
 78 /*
 79  * R4640/R4650 cp0 register names.  These registers are listed
 80  * here only for completeness; without MMU these CPUs are not useable
 81  * by Linux.  A future ELKS port might take make Linux run on them
 82  * though ...
 83  */
 84 #define CP0_IBASE $0
 85 #define CP0_IBOUND $1
 86 #define CP0_DBASE $2
 87 #define CP0_DBOUND $3
 88 #define CP0_CALG $17
 89 #define CP0_IWATCH $18
 90 #define CP0_DWATCH $19
 91 
 92 /*
 93  * Coprocessor 0 Set 1 register names
 94  */
 95 #define CP0_S1_DERRADDR0  $26
 96 #define CP0_S1_DERRADDR1  $27
 97 #define CP0_S1_INTCONTROL $20
 98 
 99 /*
100  * Coprocessor 0 Set 2 register names
101  */
102 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
103 
104 /*
105  * Coprocessor 0 Set 3 register names
106  */
107 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
108 
109 /*
110  *  TX39 Series
111  */
112 #define CP0_TX39_CACHE  $7
113 
114 
115 /* Generic EntryLo bit definitions */
116 #define ENTRYLO_G               (_ULCAST_(1) << 0)
117 #define ENTRYLO_V               (_ULCAST_(1) << 1)
118 #define ENTRYLO_D               (_ULCAST_(1) << 2)
119 #define ENTRYLO_C_SHIFT         3
120 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
121 
122 /* R3000 EntryLo bit definitions */
123 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
124 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
125 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
126 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
127 
128 /* MIPS32/64 EntryLo bit definitions */
129 #ifdef CONFIG_64BIT
130 /* as read by dmfc0 */
131 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << 62)
132 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << 63)
133 #else
134 /* as read by mfc0 */
135 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << 30)
136 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << 31)
137 #endif
138 
139 /*
140  * Values for PageMask register
141  */
142 #ifdef CONFIG_CPU_VR41XX
143 
144 /* Why doesn't stupidity hurt ... */
145 
146 #define PM_1K           0x00000000
147 #define PM_4K           0x00001800
148 #define PM_16K          0x00007800
149 #define PM_64K          0x0001f800
150 #define PM_256K         0x0007f800
151 
152 #else
153 
154 #define PM_4K           0x00000000
155 #define PM_8K           0x00002000
156 #define PM_16K          0x00006000
157 #define PM_32K          0x0000e000
158 #define PM_64K          0x0001e000
159 #define PM_128K         0x0003e000
160 #define PM_256K         0x0007e000
161 #define PM_512K         0x000fe000
162 #define PM_1M           0x001fe000
163 #define PM_2M           0x003fe000
164 #define PM_4M           0x007fe000
165 #define PM_8M           0x00ffe000
166 #define PM_16M          0x01ffe000
167 #define PM_32M          0x03ffe000
168 #define PM_64M          0x07ffe000
169 #define PM_256M         0x1fffe000
170 #define PM_1G           0x7fffe000
171 
172 #endif
173 
174 /*
175  * Default page size for a given kernel configuration
176  */
177 #ifdef CONFIG_PAGE_SIZE_4KB
178 #define PM_DEFAULT_MASK PM_4K
179 #elif defined(CONFIG_PAGE_SIZE_8KB)
180 #define PM_DEFAULT_MASK PM_8K
181 #elif defined(CONFIG_PAGE_SIZE_16KB)
182 #define PM_DEFAULT_MASK PM_16K
183 #elif defined(CONFIG_PAGE_SIZE_32KB)
184 #define PM_DEFAULT_MASK PM_32K
185 #elif defined(CONFIG_PAGE_SIZE_64KB)
186 #define PM_DEFAULT_MASK PM_64K
187 #else
188 #error Bad page size configuration!
189 #endif
190 
191 /*
192  * Default huge tlb size for a given kernel configuration
193  */
194 #ifdef CONFIG_PAGE_SIZE_4KB
195 #define PM_HUGE_MASK    PM_1M
196 #elif defined(CONFIG_PAGE_SIZE_8KB)
197 #define PM_HUGE_MASK    PM_4M
198 #elif defined(CONFIG_PAGE_SIZE_16KB)
199 #define PM_HUGE_MASK    PM_16M
200 #elif defined(CONFIG_PAGE_SIZE_32KB)
201 #define PM_HUGE_MASK    PM_64M
202 #elif defined(CONFIG_PAGE_SIZE_64KB)
203 #define PM_HUGE_MASK    PM_256M
204 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
205 #error Bad page size configuration for hugetlbfs!
206 #endif
207 
208 /*
209  * Values used for computation of new tlb entries
210  */
211 #define PL_4K           12
212 #define PL_16K          14
213 #define PL_64K          16
214 #define PL_256K         18
215 #define PL_1M           20
216 #define PL_4M           22
217 #define PL_16M          24
218 #define PL_64M          26
219 #define PL_256M         28
220 
221 /*
222  * PageGrain bits
223  */
224 #define PG_RIE          (_ULCAST_(1) <<  31)
225 #define PG_XIE          (_ULCAST_(1) <<  30)
226 #define PG_ELPA         (_ULCAST_(1) <<  29)
227 #define PG_ESP          (_ULCAST_(1) <<  28)
228 #define PG_IEC          (_ULCAST_(1) <<  27)
229 
230 /* MIPS32/64 EntryHI bit definitions */
231 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
232 
233 /*
234  * R4x00 interrupt enable / cause bits
235  */
236 #define IE_SW0          (_ULCAST_(1) <<  8)
237 #define IE_SW1          (_ULCAST_(1) <<  9)
238 #define IE_IRQ0         (_ULCAST_(1) << 10)
239 #define IE_IRQ1         (_ULCAST_(1) << 11)
240 #define IE_IRQ2         (_ULCAST_(1) << 12)
241 #define IE_IRQ3         (_ULCAST_(1) << 13)
242 #define IE_IRQ4         (_ULCAST_(1) << 14)
243 #define IE_IRQ5         (_ULCAST_(1) << 15)
244 
245 /*
246  * R4x00 interrupt cause bits
247  */
248 #define C_SW0           (_ULCAST_(1) <<  8)
249 #define C_SW1           (_ULCAST_(1) <<  9)
250 #define C_IRQ0          (_ULCAST_(1) << 10)
251 #define C_IRQ1          (_ULCAST_(1) << 11)
252 #define C_IRQ2          (_ULCAST_(1) << 12)
253 #define C_IRQ3          (_ULCAST_(1) << 13)
254 #define C_IRQ4          (_ULCAST_(1) << 14)
255 #define C_IRQ5          (_ULCAST_(1) << 15)
256 
257 /*
258  * Bitfields in the R4xx0 cp0 status register
259  */
260 #define ST0_IE                  0x00000001
261 #define ST0_EXL                 0x00000002
262 #define ST0_ERL                 0x00000004
263 #define ST0_KSU                 0x00000018
264 #  define KSU_USER              0x00000010
265 #  define KSU_SUPERVISOR        0x00000008
266 #  define KSU_KERNEL            0x00000000
267 #define ST0_UX                  0x00000020
268 #define ST0_SX                  0x00000040
269 #define ST0_KX                  0x00000080
270 #define ST0_DE                  0x00010000
271 #define ST0_CE                  0x00020000
272 
273 /*
274  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
275  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
276  * processors.
277  */
278 #define ST0_CO                  0x08000000
279 
280 /*
281  * Bitfields in the R[23]000 cp0 status register.
282  */
283 #define ST0_IEC                 0x00000001
284 #define ST0_KUC                 0x00000002
285 #define ST0_IEP                 0x00000004
286 #define ST0_KUP                 0x00000008
287 #define ST0_IEO                 0x00000010
288 #define ST0_KUO                 0x00000020
289 /* bits 6 & 7 are reserved on R[23]000 */
290 #define ST0_ISC                 0x00010000
291 #define ST0_SWC                 0x00020000
292 #define ST0_CM                  0x00080000
293 
294 /*
295  * Bits specific to the R4640/R4650
296  */
297 #define ST0_UM                  (_ULCAST_(1) <<  4)
298 #define ST0_IL                  (_ULCAST_(1) << 23)
299 #define ST0_DL                  (_ULCAST_(1) << 24)
300 
301 /*
302  * Enable the MIPS MDMX and DSP ASEs
303  */
304 #define ST0_MX                  0x01000000
305 
306 /*
307  * Status register bits available in all MIPS CPUs.
308  */
309 #define ST0_IM                  0x0000ff00
310 #define  STATUSB_IP0            8
311 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
312 #define  STATUSB_IP1            9
313 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
314 #define  STATUSB_IP2            10
315 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
316 #define  STATUSB_IP3            11
317 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
318 #define  STATUSB_IP4            12
319 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
320 #define  STATUSB_IP5            13
321 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
322 #define  STATUSB_IP6            14
323 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
324 #define  STATUSB_IP7            15
325 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
326 #define  STATUSB_IP8            0
327 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
328 #define  STATUSB_IP9            1
329 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
330 #define  STATUSB_IP10           2
331 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
332 #define  STATUSB_IP11           3
333 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
334 #define  STATUSB_IP12           4
335 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
336 #define  STATUSB_IP13           5
337 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
338 #define  STATUSB_IP14           6
339 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
340 #define  STATUSB_IP15           7
341 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
342 #define ST0_CH                  0x00040000
343 #define ST0_NMI                 0x00080000
344 #define ST0_SR                  0x00100000
345 #define ST0_TS                  0x00200000
346 #define ST0_BEV                 0x00400000
347 #define ST0_RE                  0x02000000
348 #define ST0_FR                  0x04000000
349 #define ST0_CU                  0xf0000000
350 #define ST0_CU0                 0x10000000
351 #define ST0_CU1                 0x20000000
352 #define ST0_CU2                 0x40000000
353 #define ST0_CU3                 0x80000000
354 #define ST0_XX                  0x80000000      /* MIPS IV naming */
355 
356 /*
357  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
358  */
359 #define INTCTLB_IPFDC           23
360 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
361 #define INTCTLB_IPPCI           26
362 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
363 #define INTCTLB_IPTI            29
364 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
365 
366 /*
367  * Bitfields and bit numbers in the coprocessor 0 cause register.
368  *
369  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
370  */
371 #define CAUSEB_EXCCODE          2
372 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
373 #define CAUSEB_IP               8
374 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
375 #define  CAUSEB_IP0             8
376 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
377 #define  CAUSEB_IP1             9
378 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
379 #define  CAUSEB_IP2             10
380 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
381 #define  CAUSEB_IP3             11
382 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
383 #define  CAUSEB_IP4             12
384 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
385 #define  CAUSEB_IP5             13
386 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
387 #define  CAUSEB_IP6             14
388 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
389 #define  CAUSEB_IP7             15
390 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
391 #define CAUSEB_FDCI             21
392 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
393 #define CAUSEB_IV               23
394 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
395 #define CAUSEB_PCI              26
396 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
397 #define CAUSEB_CE               28
398 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
399 #define CAUSEB_TI               30
400 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
401 #define CAUSEB_BD               31
402 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
403 
404 /*
405  * Bits in the coprocessor 0 config register.
406  */
407 /* Generic bits.  */
408 #define CONF_CM_CACHABLE_NO_WA          0
409 #define CONF_CM_CACHABLE_WA             1
410 #define CONF_CM_UNCACHED                2
411 #define CONF_CM_CACHABLE_NONCOHERENT    3
412 #define CONF_CM_CACHABLE_CE             4
413 #define CONF_CM_CACHABLE_COW            5
414 #define CONF_CM_CACHABLE_CUW            6
415 #define CONF_CM_CACHABLE_ACCELERATED    7
416 #define CONF_CM_CMASK                   7
417 #define CONF_BE                 (_ULCAST_(1) << 15)
418 
419 /* Bits common to various processors.  */
420 #define CONF_CU                 (_ULCAST_(1) <<  3)
421 #define CONF_DB                 (_ULCAST_(1) <<  4)
422 #define CONF_IB                 (_ULCAST_(1) <<  5)
423 #define CONF_DC                 (_ULCAST_(7) <<  6)
424 #define CONF_IC                 (_ULCAST_(7) <<  9)
425 #define CONF_EB                 (_ULCAST_(1) << 13)
426 #define CONF_EM                 (_ULCAST_(1) << 14)
427 #define CONF_SM                 (_ULCAST_(1) << 16)
428 #define CONF_SC                 (_ULCAST_(1) << 17)
429 #define CONF_EW                 (_ULCAST_(3) << 18)
430 #define CONF_EP                 (_ULCAST_(15)<< 24)
431 #define CONF_EC                 (_ULCAST_(7) << 28)
432 #define CONF_CM                 (_ULCAST_(1) << 31)
433 
434 /* Bits specific to the R4xx0.  */
435 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
436 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
437 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
438 
439 /* Bits specific to the R5000.  */
440 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
441 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
442 
443 /* Bits specific to the RM7000.  */
444 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
445 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
446 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
447 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
448 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
449 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
450 
451 /* Bits specific to the R10000.  */
452 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
453 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
454 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
455 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
456 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
457 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
458 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
459 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
460 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
461 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
462 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
463 
464 /* Bits specific to the VR41xx.  */
465 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
466 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
467 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
468 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
469 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
470 
471 /* Bits specific to the R30xx.  */
472 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
473 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
474 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
475 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
476 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
477 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
478 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
479 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
480 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
481 
482 /* Bits specific to the TX49.  */
483 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
484 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
485 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
486 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
487 
488 /* Bits specific to the MIPS32/64 PRA.  */
489 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
490 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
491 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
492 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
493 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
494 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
495 
496 /*
497  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
498  */
499 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
500 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
501 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
502 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
503 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
504 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
505 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
506 #define MIPS_CONF1_DA_SHF       7
507 #define MIPS_CONF1_DA_SZ        3
508 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
509 #define MIPS_CONF1_DL_SHF       10
510 #define MIPS_CONF1_DL_SZ        3
511 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
512 #define MIPS_CONF1_DS_SHF       13
513 #define MIPS_CONF1_DS_SZ        3
514 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
515 #define MIPS_CONF1_IA_SHF       16
516 #define MIPS_CONF1_IA_SZ        3
517 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
518 #define MIPS_CONF1_IL_SHF       19
519 #define MIPS_CONF1_IL_SZ        3
520 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
521 #define MIPS_CONF1_IS_SHF       22
522 #define MIPS_CONF1_IS_SZ        3
523 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
524 #define MIPS_CONF1_TLBS_SHIFT   (25)
525 #define MIPS_CONF1_TLBS_SIZE    (6)
526 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
527 
528 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
529 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
530 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
531 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
532 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
533 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
534 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
535 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
536 
537 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
538 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
539 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
540 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
541 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
542 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
543 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
544 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
545 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
546 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
547 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
548 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
549 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
550 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
551 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
552 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
553 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
554 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
555 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
556 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
557 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
558 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
559 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
560 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
561 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
562 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
563 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
564 
565 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
566 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
567 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
568 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
569 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
570 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
571 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
572 /* bits 10:8 in FTLB-only configurations */
573 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
574 /* bits 12:8 in VTLB-FTLB only configurations */
575 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
576 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
577 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
578 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
579 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
580 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << 16)
581 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
582 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
583 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
584 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
585 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
586 
587 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
588 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
589 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
590 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
591 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
592 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
593 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
594 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
595 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
596 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
597 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
598 
599 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
600 /* proAptiv FTLB on/off bit */
601 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
602 /* FTLB probability bits */
603 #define MIPS_CONF6_FTLBP_SHIFT  (16)
604 
605 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
606 
607 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
608 
609 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
610 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
611 /* FTLB probability bits for R6 */
612 #define MIPS_CONF7_FTLBP_SHIFT  (18)
613 
614 /* MAAR bit definitions */
615 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
616 #define MIPS_MAAR_ADDR_SHIFT    12
617 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
618 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
619 
620 /* CMGCRBase bit definitions */
621 #define MIPS_CMGCRB_BASE        11
622 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
623 
624 /*
625  * Bits in the MIPS32 Memory Segmentation registers.
626  */
627 #define MIPS_SEGCFG_PA_SHIFT    9
628 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
629 #define MIPS_SEGCFG_AM_SHIFT    4
630 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
631 #define MIPS_SEGCFG_EU_SHIFT    3
632 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
633 #define MIPS_SEGCFG_C_SHIFT     0
634 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
635 
636 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
637 #define MIPS_SEGCFG_USK         _ULCAST_(5)
638 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
639 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
640 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
641 #define MIPS_SEGCFG_MK          _ULCAST_(1)
642 #define MIPS_SEGCFG_UK          _ULCAST_(0)
643 
644 #define MIPS_PWFIELD_GDI_SHIFT  24
645 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
646 #define MIPS_PWFIELD_UDI_SHIFT  18
647 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
648 #define MIPS_PWFIELD_MDI_SHIFT  12
649 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
650 #define MIPS_PWFIELD_PTI_SHIFT  6
651 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
652 #define MIPS_PWFIELD_PTEI_SHIFT 0
653 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
654 
655 #define MIPS_PWSIZE_GDW_SHIFT   24
656 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
657 #define MIPS_PWSIZE_UDW_SHIFT   18
658 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
659 #define MIPS_PWSIZE_MDW_SHIFT   12
660 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
661 #define MIPS_PWSIZE_PTW_SHIFT   6
662 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
663 #define MIPS_PWSIZE_PTEW_SHIFT  0
664 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
665 
666 #define MIPS_PWCTL_PWEN_SHIFT   31
667 #define MIPS_PWCTL_PWEN_MASK    0x80000000
668 #define MIPS_PWCTL_DPH_SHIFT    7
669 #define MIPS_PWCTL_DPH_MASK     0x00000080
670 #define MIPS_PWCTL_HUGEPG_SHIFT 6
671 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
672 #define MIPS_PWCTL_PSN_SHIFT    0
673 #define MIPS_PWCTL_PSN_MASK     0x0000003f
674 
675 /* CDMMBase register bit definitions */
676 #define MIPS_CDMMBASE_SIZE_SHIFT 0
677 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
678 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
679 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
680 #define MIPS_CDMMBASE_ADDR_SHIFT 11
681 #define MIPS_CDMMBASE_ADDR_START 15
682 
683 /*
684  * Bitfields in the TX39 family CP0 Configuration Register 3
685  */
686 #define TX39_CONF_ICS_SHIFT     19
687 #define TX39_CONF_ICS_MASK      0x00380000
688 #define TX39_CONF_ICS_1KB       0x00000000
689 #define TX39_CONF_ICS_2KB       0x00080000
690 #define TX39_CONF_ICS_4KB       0x00100000
691 #define TX39_CONF_ICS_8KB       0x00180000
692 #define TX39_CONF_ICS_16KB      0x00200000
693 
694 #define TX39_CONF_DCS_SHIFT     16
695 #define TX39_CONF_DCS_MASK      0x00070000
696 #define TX39_CONF_DCS_1KB       0x00000000
697 #define TX39_CONF_DCS_2KB       0x00010000
698 #define TX39_CONF_DCS_4KB       0x00020000
699 #define TX39_CONF_DCS_8KB       0x00030000
700 #define TX39_CONF_DCS_16KB      0x00040000
701 
702 #define TX39_CONF_CWFON         0x00004000
703 #define TX39_CONF_WBON          0x00002000
704 #define TX39_CONF_RF_SHIFT      10
705 #define TX39_CONF_RF_MASK       0x00000c00
706 #define TX39_CONF_DOZE          0x00000200
707 #define TX39_CONF_HALT          0x00000100
708 #define TX39_CONF_LOCK          0x00000080
709 #define TX39_CONF_ICE           0x00000020
710 #define TX39_CONF_DCE           0x00000010
711 #define TX39_CONF_IRSIZE_SHIFT  2
712 #define TX39_CONF_IRSIZE_MASK   0x0000000c
713 #define TX39_CONF_DRSIZE_SHIFT  0
714 #define TX39_CONF_DRSIZE_MASK   0x00000003
715 
716 /*
717  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
718  */
719 /* Disable Branch Target Address Cache */
720 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
721 /* Enable Branch Prediction Global History */
722 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
723 /* Disable Branch Return Cache */
724 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
725 
726 /*
727  * Coprocessor 1 (FPU) register names
728  */
729 #define CP1_REVISION    $0
730 #define CP1_UFR         $1
731 #define CP1_UNFR        $4
732 #define CP1_FCCR        $25
733 #define CP1_FEXR        $26
734 #define CP1_FENR        $28
735 #define CP1_STATUS      $31
736 
737 
738 /*
739  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
740  */
741 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
742 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
743 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
744 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
745 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
746 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
747 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
748 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
749 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
750 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
751 
752 /*
753  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
754  */
755 #define MIPS_FCCR_CONDX_S       0
756 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
757 #define MIPS_FCCR_COND0_S       0
758 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
759 #define MIPS_FCCR_COND1_S       1
760 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
761 #define MIPS_FCCR_COND2_S       2
762 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
763 #define MIPS_FCCR_COND3_S       3
764 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
765 #define MIPS_FCCR_COND4_S       4
766 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
767 #define MIPS_FCCR_COND5_S       5
768 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
769 #define MIPS_FCCR_COND6_S       6
770 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
771 #define MIPS_FCCR_COND7_S       7
772 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
773 
774 /*
775  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
776  */
777 #define MIPS_FENR_FS_S          2
778 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
779 
780 /*
781  * FPU Status Register Values
782  */
783 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
784 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
785 
786 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
787 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
788 
789 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
790 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
791 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
792 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
793 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
794 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
795 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
796 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
797 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
798 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
799 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
800 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
801 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
802 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
803 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
804 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
805 
806 /*
807  * Bits 22:20 of the FPU Status Register will be read as 0,
808  * and should be written as zero.
809  */
810 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
811 
812 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
813 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
814 
815 /*
816  * X the exception cause indicator
817  * E the exception enable
818  * S the sticky/flag bit
819 */
820 #define FPU_CSR_ALL_X   0x0003f000
821 #define FPU_CSR_UNI_X   0x00020000
822 #define FPU_CSR_INV_X   0x00010000
823 #define FPU_CSR_DIV_X   0x00008000
824 #define FPU_CSR_OVF_X   0x00004000
825 #define FPU_CSR_UDF_X   0x00002000
826 #define FPU_CSR_INE_X   0x00001000
827 
828 #define FPU_CSR_ALL_E   0x00000f80
829 #define FPU_CSR_INV_E   0x00000800
830 #define FPU_CSR_DIV_E   0x00000400
831 #define FPU_CSR_OVF_E   0x00000200
832 #define FPU_CSR_UDF_E   0x00000100
833 #define FPU_CSR_INE_E   0x00000080
834 
835 #define FPU_CSR_ALL_S   0x0000007c
836 #define FPU_CSR_INV_S   0x00000040
837 #define FPU_CSR_DIV_S   0x00000020
838 #define FPU_CSR_OVF_S   0x00000010
839 #define FPU_CSR_UDF_S   0x00000008
840 #define FPU_CSR_INE_S   0x00000004
841 
842 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
843 #define FPU_CSR_RM      0x00000003
844 #define FPU_CSR_RN      0x0     /* nearest */
845 #define FPU_CSR_RZ      0x1     /* towards zero */
846 #define FPU_CSR_RU      0x2     /* towards +Infinity */
847 #define FPU_CSR_RD      0x3     /* towards -Infinity */
848 
849 
850 #ifndef __ASSEMBLY__
851 
852 /*
853  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
854  */
855 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
856     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
857 #define get_isa16_mode(x)               ((x) & 0x1)
858 #define msk_isa16_mode(x)               ((x) & ~0x1)
859 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
860 #else
861 #define get_isa16_mode(x)               0
862 #define msk_isa16_mode(x)               (x)
863 #define set_isa16_mode(x)               do { } while(0)
864 #endif
865 
866 /*
867  * microMIPS instructions can be 16-bit or 32-bit in length. This
868  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
869  */
870 static inline int mm_insn_16bit(u16 insn)
871 {
872         u16 opcode = (insn >> 10) & 0x7;
873 
874         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
875 }
876 
877 /*
878  * TLB Invalidate Flush
879  */
880 static inline void tlbinvf(void)
881 {
882         __asm__ __volatile__(
883                 ".set push\n\t"
884                 ".set noreorder\n\t"
885                 ".word 0x42000004\n\t" /* tlbinvf */
886                 ".set pop");
887 }
888 
889 
890 /*
891  * Functions to access the R10000 performance counters.  These are basically
892  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
893  * performance counter number encoded into bits 1 ... 5 of the instruction.
894  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
895  * disassembler these will look like an access to sel 0 or 1.
896  */
897 #define read_r10k_perf_cntr(counter)                            \
898 ({                                                              \
899         unsigned int __res;                                     \
900         __asm__ __volatile__(                                   \
901         "mfpc\t%0, %1"                                          \
902         : "=r" (__res)                                          \
903         : "i" (counter));                                       \
904                                                                 \
905         __res;                                                  \
906 })
907 
908 #define write_r10k_perf_cntr(counter,val)                       \
909 do {                                                            \
910         __asm__ __volatile__(                                   \
911         "mtpc\t%0, %1"                                          \
912         :                                                       \
913         : "r" (val), "i" (counter));                            \
914 } while (0)
915 
916 #define read_r10k_perf_event(counter)                           \
917 ({                                                              \
918         unsigned int __res;                                     \
919         __asm__ __volatile__(                                   \
920         "mfps\t%0, %1"                                          \
921         : "=r" (__res)                                          \
922         : "i" (counter));                                       \
923                                                                 \
924         __res;                                                  \
925 })
926 
927 #define write_r10k_perf_cntl(counter,val)                       \
928 do {                                                            \
929         __asm__ __volatile__(                                   \
930         "mtps\t%0, %1"                                          \
931         :                                                       \
932         : "r" (val), "i" (counter));                            \
933 } while (0)
934 
935 
936 /*
937  * Macros to access the system control coprocessor
938  */
939 
940 #define __read_32bit_c0_register(source, sel)                           \
941 ({ unsigned int __res;                                                  \
942         if (sel == 0)                                                   \
943                 __asm__ __volatile__(                                   \
944                         "mfc0\t%0, " #source "\n\t"                     \
945                         : "=r" (__res));                                \
946         else                                                            \
947                 __asm__ __volatile__(                                   \
948                         ".set\tmips32\n\t"                              \
949                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
950                         ".set\tmips0\n\t"                               \
951                         : "=r" (__res));                                \
952         __res;                                                          \
953 })
954 
955 #define __read_64bit_c0_register(source, sel)                           \
956 ({ unsigned long long __res;                                            \
957         if (sizeof(unsigned long) == 4)                                 \
958                 __res = __read_64bit_c0_split(source, sel);             \
959         else if (sel == 0)                                              \
960                 __asm__ __volatile__(                                   \
961                         ".set\tmips3\n\t"                               \
962                         "dmfc0\t%0, " #source "\n\t"                    \
963                         ".set\tmips0"                                   \
964                         : "=r" (__res));                                \
965         else                                                            \
966                 __asm__ __volatile__(                                   \
967                         ".set\tmips64\n\t"                              \
968                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
969                         ".set\tmips0"                                   \
970                         : "=r" (__res));                                \
971         __res;                                                          \
972 })
973 
974 #define __write_32bit_c0_register(register, sel, value)                 \
975 do {                                                                    \
976         if (sel == 0)                                                   \
977                 __asm__ __volatile__(                                   \
978                         "mtc0\t%z0, " #register "\n\t"                  \
979                         : : "Jr" ((unsigned int)(value)));              \
980         else                                                            \
981                 __asm__ __volatile__(                                   \
982                         ".set\tmips32\n\t"                              \
983                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
984                         ".set\tmips0"                                   \
985                         : : "Jr" ((unsigned int)(value)));              \
986 } while (0)
987 
988 #define __write_64bit_c0_register(register, sel, value)                 \
989 do {                                                                    \
990         if (sizeof(unsigned long) == 4)                                 \
991                 __write_64bit_c0_split(register, sel, value);           \
992         else if (sel == 0)                                              \
993                 __asm__ __volatile__(                                   \
994                         ".set\tmips3\n\t"                               \
995                         "dmtc0\t%z0, " #register "\n\t"                 \
996                         ".set\tmips0"                                   \
997                         : : "Jr" (value));                              \
998         else                                                            \
999                 __asm__ __volatile__(                                   \
1000                         ".set\tmips64\n\t"                              \
1001                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1002                         ".set\tmips0"                                   \
1003                         : : "Jr" (value));                              \
1004 } while (0)
1005 
1006 #define __read_ulong_c0_register(reg, sel)                              \
1007         ((sizeof(unsigned long) == 4) ?                                 \
1008         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1009         (unsigned long) __read_64bit_c0_register(reg, sel))
1010 
1011 #define __write_ulong_c0_register(reg, sel, val)                        \
1012 do {                                                                    \
1013         if (sizeof(unsigned long) == 4)                                 \
1014                 __write_32bit_c0_register(reg, sel, val);               \
1015         else                                                            \
1016                 __write_64bit_c0_register(reg, sel, val);               \
1017 } while (0)
1018 
1019 /*
1020  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1021  */
1022 #define __read_32bit_c0_ctrl_register(source)                           \
1023 ({ unsigned int __res;                                                  \
1024         __asm__ __volatile__(                                           \
1025                 "cfc0\t%0, " #source "\n\t"                             \
1026                 : "=r" (__res));                                        \
1027         __res;                                                          \
1028 })
1029 
1030 #define __write_32bit_c0_ctrl_register(register, value)                 \
1031 do {                                                                    \
1032         __asm__ __volatile__(                                           \
1033                 "ctc0\t%z0, " #register "\n\t"                          \
1034                 : : "Jr" ((unsigned int)(value)));                      \
1035 } while (0)
1036 
1037 /*
1038  * These versions are only needed for systems with more than 38 bits of
1039  * physical address space running the 32-bit kernel.  That's none atm :-)
1040  */
1041 #define __read_64bit_c0_split(source, sel)                              \
1042 ({                                                                      \
1043         unsigned long long __val;                                       \
1044         unsigned long __flags;                                          \
1045                                                                         \
1046         local_irq_save(__flags);                                        \
1047         if (sel == 0)                                                   \
1048                 __asm__ __volatile__(                                   \
1049                         ".set\tmips64\n\t"                              \
1050                         "dmfc0\t%M0, " #source "\n\t"                   \
1051                         "dsll\t%L0, %M0, 32\n\t"                        \
1052                         "dsra\t%M0, %M0, 32\n\t"                        \
1053                         "dsra\t%L0, %L0, 32\n\t"                        \
1054                         ".set\tmips0"                                   \
1055                         : "=r" (__val));                                \
1056         else                                                            \
1057                 __asm__ __volatile__(                                   \
1058                         ".set\tmips64\n\t"                              \
1059                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1060                         "dsll\t%L0, %M0, 32\n\t"                        \
1061                         "dsra\t%M0, %M0, 32\n\t"                        \
1062                         "dsra\t%L0, %L0, 32\n\t"                        \
1063                         ".set\tmips0"                                   \
1064                         : "=r" (__val));                                \
1065         local_irq_restore(__flags);                                     \
1066                                                                         \
1067         __val;                                                          \
1068 })
1069 
1070 #define __write_64bit_c0_split(source, sel, val)                        \
1071 do {                                                                    \
1072         unsigned long __flags;                                          \
1073                                                                         \
1074         local_irq_save(__flags);                                        \
1075         if (sel == 0)                                                   \
1076                 __asm__ __volatile__(                                   \
1077                         ".set\tmips64\n\t"                              \
1078                         "dsll\t%L0, %L0, 32\n\t"                        \
1079                         "dsrl\t%L0, %L0, 32\n\t"                        \
1080                         "dsll\t%M0, %M0, 32\n\t"                        \
1081                         "or\t%L0, %L0, %M0\n\t"                         \
1082                         "dmtc0\t%L0, " #source "\n\t"                   \
1083                         ".set\tmips0"                                   \
1084                         : : "r" (val));                                 \
1085         else                                                            \
1086                 __asm__ __volatile__(                                   \
1087                         ".set\tmips64\n\t"                              \
1088                         "dsll\t%L0, %L0, 32\n\t"                        \
1089                         "dsrl\t%L0, %L0, 32\n\t"                        \
1090                         "dsll\t%M0, %M0, 32\n\t"                        \
1091                         "or\t%L0, %L0, %M0\n\t"                         \
1092                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1093                         ".set\tmips0"                                   \
1094                         : : "r" (val));                                 \
1095         local_irq_restore(__flags);                                     \
1096 } while (0)
1097 
1098 #define __readx_32bit_c0_register(source)                               \
1099 ({                                                                      \
1100         unsigned int __res;                                             \
1101                                                                         \
1102         __asm__ __volatile__(                                           \
1103         "       .set    push                                    \n"     \
1104         "       .set    noat                                    \n"     \
1105         "       .set    mips32r2                                \n"     \
1106         "       .insn                                           \n"     \
1107         "       # mfhc0 $1, %1                                  \n"     \
1108         "       .word   (0x40410000 | ((%1 & 0x1f) << 11))      \n"     \
1109         "       move    %0, $1                                  \n"     \
1110         "       .set    pop                                     \n"     \
1111         : "=r" (__res)                                                  \
1112         : "i" (source));                                                \
1113         __res;                                                          \
1114 })
1115 
1116 #define __writex_32bit_c0_register(register, value)                     \
1117 do {                                                                    \
1118         __asm__ __volatile__(                                           \
1119         "       .set    push                                    \n"     \
1120         "       .set    noat                                    \n"     \
1121         "       .set    mips32r2                                \n"     \
1122         "       move    $1, %0                                  \n"     \
1123         "       # mthc0 $1, %1                                  \n"     \
1124         "       .insn                                           \n"     \
1125         "       .word   (0x40c10000 | ((%1 & 0x1f) << 11))      \n"     \
1126         "       .set    pop                                     \n"     \
1127         :                                                               \
1128         : "r" (value), "i" (register));                                 \
1129 } while (0)
1130 
1131 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1132 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1133 
1134 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1135 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1136 
1137 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1138 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1139 
1140 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1141 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1142 
1143 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1144 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1145 
1146 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1147 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1148 
1149 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1150 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1151 
1152 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1153 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1154 
1155 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1156 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1157 
1158 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1159 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1160 
1161 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1162 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1163 
1164 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1165 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1166 
1167 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1168 
1169 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1170 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1171 
1172 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1173 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1174 
1175 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1176 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1177 
1178 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1179 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1180 
1181 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1182 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1183 
1184 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1185 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1186 
1187 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1188 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1189 
1190 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1191 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1192 
1193 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1194 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1195 
1196 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1197 
1198 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1199 
1200 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1201 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1202 
1203 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1204 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1205 
1206 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1207 
1208 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1209 
1210 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1211 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1212 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1213 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1214 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1215 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1216 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1217 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1218 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1219 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1220 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1221 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1222 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1223 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1224 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1225 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1226 
1227 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1228 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1229 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1230 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1231 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1232 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1233 
1234 /*
1235  * The WatchLo register.  There may be up to 8 of them.
1236  */
1237 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1238 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1239 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1240 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1241 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1242 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1243 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1244 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1245 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1246 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1247 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1248 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1249 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1250 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1251 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1252 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1253 
1254 /*
1255  * The WatchHi register.  There may be up to 8 of them.
1256  */
1257 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1258 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1259 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1260 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1261 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1262 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1263 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1264 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1265 
1266 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1267 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1268 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1269 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1270 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1271 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1272 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1273 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1274 
1275 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1276 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1277 
1278 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1279 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1280 
1281 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1282 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1283 
1284 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1285 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1286 
1287 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1288 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1289 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1290 
1291 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1292 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1293 
1294 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1295 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1296 
1297 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1298 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1299 
1300 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1301 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1302 
1303 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1304 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1305 
1306 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1307 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1308 
1309 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1310 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1311 
1312 /*
1313  * MIPS32 / MIPS64 performance counters
1314  */
1315 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1316 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1317 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1318 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1319 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1320 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1321 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1322 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1323 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1324 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1325 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1326 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1327 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1328 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1329 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1330 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1331 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1332 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1333 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1334 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1335 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1336 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1337 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1338 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1339 
1340 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1341 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1342 
1343 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1344 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1345 
1346 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1347 
1348 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1349 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1350 
1351 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1352 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1353 
1354 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1355 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1356 
1357 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1358 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1359 
1360 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1361 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1362 
1363 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1364 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1365 
1366 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1367 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1368 
1369 /* MIPSR2 */
1370 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1371 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1372 
1373 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1374 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1375 
1376 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1377 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1378 
1379 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1380 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1381 
1382 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1383 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1384 
1385 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1386 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1387 
1388 /* MIPSR3 */
1389 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1390 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1391 
1392 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1393 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1394 
1395 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1396 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1397 
1398 /* Hardware Page Table Walker */
1399 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1400 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1401 
1402 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1403 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1404 
1405 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1406 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1407 
1408 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1409 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1410 
1411 /* Cavium OCTEON (cnMIPS) */
1412 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1413 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1414 
1415 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1416 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1417 
1418 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1419 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1420 /*
1421  * The cacheerr registers are not standardized.  On OCTEON, they are
1422  * 64 bits wide.
1423  */
1424 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1425 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1426 
1427 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1428 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1429 
1430 /* BMIPS3300 */
1431 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1432 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1433 
1434 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1435 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1436 
1437 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1438 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1439 
1440 /* BMIPS43xx */
1441 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1442 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1443 
1444 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1445 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1446 
1447 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1448 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1449 
1450 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1451 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1452 
1453 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1454 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1455 
1456 /* BMIPS5000 */
1457 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1458 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1459 
1460 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1461 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1462 
1463 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1464 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1465 
1466 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1467 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1468 
1469 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1470 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1471 
1472 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1473 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1474 
1475 /*
1476  * Macros to access the floating point coprocessor control registers
1477  */
1478 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
1479 ({                                                                      \
1480         unsigned int __res;                                             \
1481                                                                         \
1482         __asm__ __volatile__(                                           \
1483         "       .set    push                                    \n"     \
1484         "       .set    reorder                                 \n"     \
1485         "       # gas fails to assemble cfc1 for some archs,    \n"     \
1486         "       # like Octeon.                                  \n"     \
1487         "       .set    mips1                                   \n"     \
1488         "       "STR(gas_hardfloat)"                            \n"     \
1489         "       cfc1    %0,"STR(source)"                        \n"     \
1490         "       .set    pop                                     \n"     \
1491         : "=r" (__res));                                                \
1492         __res;                                                          \
1493 })
1494 
1495 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
1496 do {                                                                    \
1497         __asm__ __volatile__(                                           \
1498         "       .set    push                                    \n"     \
1499         "       .set    reorder                                 \n"     \
1500         "       "STR(gas_hardfloat)"                            \n"     \
1501         "       ctc1    %0,"STR(dest)"                          \n"     \
1502         "       .set    pop                                     \n"     \
1503         : : "r" (val));                                                 \
1504 } while (0)
1505 
1506 #ifdef GAS_HAS_SET_HARDFLOAT
1507 #define read_32bit_cp1_register(source)                                 \
1508         _read_32bit_cp1_register(source, .set hardfloat)
1509 #define write_32bit_cp1_register(dest, val)                             \
1510         _write_32bit_cp1_register(dest, val, .set hardfloat)
1511 #else
1512 #define read_32bit_cp1_register(source)                                 \
1513         _read_32bit_cp1_register(source, )
1514 #define write_32bit_cp1_register(dest, val)                             \
1515         _write_32bit_cp1_register(dest, val, )
1516 #endif
1517 
1518 #ifdef HAVE_AS_DSP
1519 #define rddsp(mask)                                                     \
1520 ({                                                                      \
1521         unsigned int __dspctl;                                          \
1522                                                                         \
1523         __asm__ __volatile__(                                           \
1524         "       .set push                                       \n"     \
1525         "       .set dsp                                        \n"     \
1526         "       rddsp   %0, %x1                                 \n"     \
1527         "       .set pop                                        \n"     \
1528         : "=r" (__dspctl)                                               \
1529         : "i" (mask));                                                  \
1530         __dspctl;                                                       \
1531 })
1532 
1533 #define wrdsp(val, mask)                                                \
1534 do {                                                                    \
1535         __asm__ __volatile__(                                           \
1536         "       .set push                                       \n"     \
1537         "       .set dsp                                        \n"     \
1538         "       wrdsp   %0, %x1                                 \n"     \
1539         "       .set pop                                        \n"     \
1540         :                                                               \
1541         : "r" (val), "i" (mask));                                       \
1542 } while (0)
1543 
1544 #define mflo0()                                                         \
1545 ({                                                                      \
1546         long mflo0;                                                     \
1547         __asm__(                                                        \
1548         "       .set push                                       \n"     \
1549         "       .set dsp                                        \n"     \
1550         "       mflo %0, $ac0                                   \n"     \
1551         "       .set pop                                        \n"     \
1552         : "=r" (mflo0));                                                \
1553         mflo0;                                                          \
1554 })
1555 
1556 #define mflo1()                                                         \
1557 ({                                                                      \
1558         long mflo1;                                                     \
1559         __asm__(                                                        \
1560         "       .set push                                       \n"     \
1561         "       .set dsp                                        \n"     \
1562         "       mflo %0, $ac1                                   \n"     \
1563         "       .set pop                                        \n"     \
1564         : "=r" (mflo1));                                                \
1565         mflo1;                                                          \
1566 })
1567 
1568 #define mflo2()                                                         \
1569 ({                                                                      \
1570         long mflo2;                                                     \
1571         __asm__(                                                        \
1572         "       .set push                                       \n"     \
1573         "       .set dsp                                        \n"     \
1574         "       mflo %0, $ac2                                   \n"     \
1575         "       .set pop                                        \n"     \
1576         : "=r" (mflo2));                                                \
1577         mflo2;                                                          \
1578 })
1579 
1580 #define mflo3()                                                         \
1581 ({                                                                      \
1582         long mflo3;                                                     \
1583         __asm__(                                                        \
1584         "       .set push                                       \n"     \
1585         "       .set dsp                                        \n"     \
1586         "       mflo %0, $ac3                                   \n"     \
1587         "       .set pop                                        \n"     \
1588         : "=r" (mflo3));                                                \
1589         mflo3;                                                          \
1590 })
1591 
1592 #define mfhi0()                                                         \
1593 ({                                                                      \
1594         long mfhi0;                                                     \
1595         __asm__(                                                        \
1596         "       .set push                                       \n"     \
1597         "       .set dsp                                        \n"     \
1598         "       mfhi %0, $ac0                                   \n"     \
1599         "       .set pop                                        \n"     \
1600         : "=r" (mfhi0));                                                \
1601         mfhi0;                                                          \
1602 })
1603 
1604 #define mfhi1()                                                         \
1605 ({                                                                      \
1606         long mfhi1;                                                     \
1607         __asm__(                                                        \
1608         "       .set push                                       \n"     \
1609         "       .set dsp                                        \n"     \
1610         "       mfhi %0, $ac1                                   \n"     \
1611         "       .set pop                                        \n"     \
1612         : "=r" (mfhi1));                                                \
1613         mfhi1;                                                          \
1614 })
1615 
1616 #define mfhi2()                                                         \
1617 ({                                                                      \
1618         long mfhi2;                                                     \
1619         __asm__(                                                        \
1620         "       .set push                                       \n"     \
1621         "       .set dsp                                        \n"     \
1622         "       mfhi %0, $ac2                                   \n"     \
1623         "       .set pop                                        \n"     \
1624         : "=r" (mfhi2));                                                \
1625         mfhi2;                                                          \
1626 })
1627 
1628 #define mfhi3()                                                         \
1629 ({                                                                      \
1630         long mfhi3;                                                     \
1631         __asm__(                                                        \
1632         "       .set push                                       \n"     \
1633         "       .set dsp                                        \n"     \
1634         "       mfhi %0, $ac3                                   \n"     \
1635         "       .set pop                                        \n"     \
1636         : "=r" (mfhi3));                                                \
1637         mfhi3;                                                          \
1638 })
1639 
1640 
1641 #define mtlo0(x)                                                        \
1642 ({                                                                      \
1643         __asm__(                                                        \
1644         "       .set push                                       \n"     \
1645         "       .set dsp                                        \n"     \
1646         "       mtlo %0, $ac0                                   \n"     \
1647         "       .set pop                                        \n"     \
1648         :                                                               \
1649         : "r" (x));                                                     \
1650 })
1651 
1652 #define mtlo1(x)                                                        \
1653 ({                                                                      \
1654         __asm__(                                                        \
1655         "       .set push                                       \n"     \
1656         "       .set dsp                                        \n"     \
1657         "       mtlo %0, $ac1                                   \n"     \
1658         "       .set pop                                        \n"     \
1659         :                                                               \
1660         : "r" (x));                                                     \
1661 })
1662 
1663 #define mtlo2(x)                                                        \
1664 ({                                                                      \
1665         __asm__(                                                        \
1666         "       .set push                                       \n"     \
1667         "       .set dsp                                        \n"     \
1668         "       mtlo %0, $ac2                                   \n"     \
1669         "       .set pop                                        \n"     \
1670         :                                                               \
1671         : "r" (x));                                                     \
1672 })
1673 
1674 #define mtlo3(x)                                                        \
1675 ({                                                                      \
1676         __asm__(                                                        \
1677         "       .set push                                       \n"     \
1678         "       .set dsp                                        \n"     \
1679         "       mtlo %0, $ac3                                   \n"     \
1680         "       .set pop                                        \n"     \
1681         :                                                               \
1682         : "r" (x));                                                     \
1683 })
1684 
1685 #define mthi0(x)                                                        \
1686 ({                                                                      \
1687         __asm__(                                                        \
1688         "       .set push                                       \n"     \
1689         "       .set dsp                                        \n"     \
1690         "       mthi %0, $ac0                                   \n"     \
1691         "       .set pop                                        \n"     \
1692         :                                                               \
1693         : "r" (x));                                                     \
1694 })
1695 
1696 #define mthi1(x)                                                        \
1697 ({                                                                      \
1698         __asm__(                                                        \
1699         "       .set push                                       \n"     \
1700         "       .set dsp                                        \n"     \
1701         "       mthi %0, $ac1                                   \n"     \
1702         "       .set pop                                        \n"     \
1703         :                                                               \
1704         : "r" (x));                                                     \
1705 })
1706 
1707 #define mthi2(x)                                                        \
1708 ({                                                                      \
1709         __asm__(                                                        \
1710         "       .set push                                       \n"     \
1711         "       .set dsp                                        \n"     \
1712         "       mthi %0, $ac2                                   \n"     \
1713         "       .set pop                                        \n"     \
1714         :                                                               \
1715         : "r" (x));                                                     \
1716 })
1717 
1718 #define mthi3(x)                                                        \
1719 ({                                                                      \
1720         __asm__(                                                        \
1721         "       .set push                                       \n"     \
1722         "       .set dsp                                        \n"     \
1723         "       mthi %0, $ac3                                   \n"     \
1724         "       .set pop                                        \n"     \
1725         :                                                               \
1726         : "r" (x));                                                     \
1727 })
1728 
1729 #else
1730 
1731 #ifdef CONFIG_CPU_MICROMIPS
1732 #define rddsp(mask)                                                     \
1733 ({                                                                      \
1734         unsigned int __res;                                             \
1735                                                                         \
1736         __asm__ __volatile__(                                           \
1737         "       .set    push                                    \n"     \
1738         "       .set    noat                                    \n"     \
1739         "       # rddsp $1, %x1                                 \n"     \
1740         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
1741         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
1742         "       move    %0, $1                                  \n"     \
1743         "       .set    pop                                     \n"     \
1744         : "=r" (__res)                                                  \
1745         : "i" (mask));                                                  \
1746         __res;                                                          \
1747 })
1748 
1749 #define wrdsp(val, mask)                                                \
1750 do {                                                                    \
1751         __asm__ __volatile__(                                           \
1752         "       .set    push                                    \n"     \
1753         "       .set    noat                                    \n"     \
1754         "       move    $1, %0                                  \n"     \
1755         "       # wrdsp $1, %x1                                 \n"     \
1756         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
1757         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
1758         "       .set    pop                                     \n"     \
1759         :                                                               \
1760         : "r" (val), "i" (mask));                                       \
1761 } while (0)
1762 
1763 #define _umips_dsp_mfxxx(ins)                                           \
1764 ({                                                                      \
1765         unsigned long __treg;                                           \
1766                                                                         \
1767         __asm__ __volatile__(                                           \
1768         "       .set    push                                    \n"     \
1769         "       .set    noat                                    \n"     \
1770         "       .hword  0x0001                                  \n"     \
1771         "       .hword  %x1                                     \n"     \
1772         "       move    %0, $1                                  \n"     \
1773         "       .set    pop                                     \n"     \
1774         : "=r" (__treg)                                                 \
1775         : "i" (ins));                                                   \
1776         __treg;                                                         \
1777 })
1778 
1779 #define _umips_dsp_mtxxx(val, ins)                                      \
1780 do {                                                                    \
1781         __asm__ __volatile__(                                           \
1782         "       .set    push                                    \n"     \
1783         "       .set    noat                                    \n"     \
1784         "       move    $1, %0                                  \n"     \
1785         "       .hword  0x0001                                  \n"     \
1786         "       .hword  %x1                                     \n"     \
1787         "       .set    pop                                     \n"     \
1788         :                                                               \
1789         : "r" (val), "i" (ins));                                        \
1790 } while (0)
1791 
1792 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1793 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1794 
1795 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1796 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1797 
1798 #define mflo0() _umips_dsp_mflo(0)
1799 #define mflo1() _umips_dsp_mflo(1)
1800 #define mflo2() _umips_dsp_mflo(2)
1801 #define mflo3() _umips_dsp_mflo(3)
1802 
1803 #define mfhi0() _umips_dsp_mfhi(0)
1804 #define mfhi1() _umips_dsp_mfhi(1)
1805 #define mfhi2() _umips_dsp_mfhi(2)
1806 #define mfhi3() _umips_dsp_mfhi(3)
1807 
1808 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1809 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1810 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1811 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1812 
1813 #define mthi0(x) _umips_dsp_mthi(x, 0)
1814 #define mthi1(x) _umips_dsp_mthi(x, 1)
1815 #define mthi2(x) _umips_dsp_mthi(x, 2)
1816 #define mthi3(x) _umips_dsp_mthi(x, 3)
1817 
1818 #else  /* !CONFIG_CPU_MICROMIPS */
1819 #define rddsp(mask)                                                     \
1820 ({                                                                      \
1821         unsigned int __res;                                             \
1822                                                                         \
1823         __asm__ __volatile__(                                           \
1824         "       .set    push                            \n"             \
1825         "       .set    noat                            \n"             \
1826         "       # rddsp $1, %x1                         \n"             \
1827         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1828         "       move    %0, $1                          \n"             \
1829         "       .set    pop                             \n"             \
1830         : "=r" (__res)                                                  \
1831         : "i" (mask));                                                  \
1832         __res;                                                          \
1833 })
1834 
1835 #define wrdsp(val, mask)                                                \
1836 do {                                                                    \
1837         __asm__ __volatile__(                                           \
1838         "       .set    push                                    \n"     \
1839         "       .set    noat                                    \n"     \
1840         "       move    $1, %0                                  \n"     \
1841         "       # wrdsp $1, %x1                                 \n"     \
1842         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1843         "       .set    pop                                     \n"     \
1844         :                                                               \
1845         : "r" (val), "i" (mask));                                       \
1846 } while (0)
1847 
1848 #define _dsp_mfxxx(ins)                                                 \
1849 ({                                                                      \
1850         unsigned long __treg;                                           \
1851                                                                         \
1852         __asm__ __volatile__(                                           \
1853         "       .set    push                                    \n"     \
1854         "       .set    noat                                    \n"     \
1855         "       .word   (0x00000810 | %1)                       \n"     \
1856         "       move    %0, $1                                  \n"     \
1857         "       .set    pop                                     \n"     \
1858         : "=r" (__treg)                                                 \
1859         : "i" (ins));                                                   \
1860         __treg;                                                         \
1861 })
1862 
1863 #define _dsp_mtxxx(val, ins)                                            \
1864 do {                                                                    \
1865         __asm__ __volatile__(                                           \
1866         "       .set    push                                    \n"     \
1867         "       .set    noat                                    \n"     \
1868         "       move    $1, %0                                  \n"     \
1869         "       .word   (0x00200011 | %1)                       \n"     \
1870         "       .set    pop                                     \n"     \
1871         :                                                               \
1872         : "r" (val), "i" (ins));                                        \
1873 } while (0)
1874 
1875 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1876 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1877 
1878 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1879 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1880 
1881 #define mflo0() _dsp_mflo(0)
1882 #define mflo1() _dsp_mflo(1)
1883 #define mflo2() _dsp_mflo(2)
1884 #define mflo3() _dsp_mflo(3)
1885 
1886 #define mfhi0() _dsp_mfhi(0)
1887 #define mfhi1() _dsp_mfhi(1)
1888 #define mfhi2() _dsp_mfhi(2)
1889 #define mfhi3() _dsp_mfhi(3)
1890 
1891 #define mtlo0(x) _dsp_mtlo(x, 0)
1892 #define mtlo1(x) _dsp_mtlo(x, 1)
1893 #define mtlo2(x) _dsp_mtlo(x, 2)
1894 #define mtlo3(x) _dsp_mtlo(x, 3)
1895 
1896 #define mthi0(x) _dsp_mthi(x, 0)
1897 #define mthi1(x) _dsp_mthi(x, 1)
1898 #define mthi2(x) _dsp_mthi(x, 2)
1899 #define mthi3(x) _dsp_mthi(x, 3)
1900 
1901 #endif /* CONFIG_CPU_MICROMIPS */
1902 #endif
1903 
1904 /*
1905  * TLB operations.
1906  *
1907  * It is responsibility of the caller to take care of any TLB hazards.
1908  */
1909 static inline void tlb_probe(void)
1910 {
1911         __asm__ __volatile__(
1912                 ".set noreorder\n\t"
1913                 "tlbp\n\t"
1914                 ".set reorder");
1915 }
1916 
1917 static inline void tlb_read(void)
1918 {
1919 #if MIPS34K_MISSED_ITLB_WAR
1920         int res = 0;
1921 
1922         __asm__ __volatile__(
1923         "       .set    push                                    \n"
1924         "       .set    noreorder                               \n"
1925         "       .set    noat                                    \n"
1926         "       .set    mips32r2                                \n"
1927         "       .word   0x41610001              # dvpe $1       \n"
1928         "       move    %0, $1                                  \n"
1929         "       ehb                                             \n"
1930         "       .set    pop                                     \n"
1931         : "=r" (res));
1932 
1933         instruction_hazard();
1934 #endif
1935 
1936         __asm__ __volatile__(
1937                 ".set noreorder\n\t"
1938                 "tlbr\n\t"
1939                 ".set reorder");
1940 
1941 #if MIPS34K_MISSED_ITLB_WAR
1942         if ((res & _ULCAST_(1)))
1943                 __asm__ __volatile__(
1944                 "       .set    push                            \n"
1945                 "       .set    noreorder                       \n"
1946                 "       .set    noat                            \n"
1947                 "       .set    mips32r2                        \n"
1948                 "       .word   0x41600021      # evpe          \n"
1949                 "       ehb                                     \n"
1950                 "       .set    pop                             \n");
1951 #endif
1952 }
1953 
1954 static inline void tlb_write_indexed(void)
1955 {
1956         __asm__ __volatile__(
1957                 ".set noreorder\n\t"
1958                 "tlbwi\n\t"
1959                 ".set reorder");
1960 }
1961 
1962 static inline void tlb_write_random(void)
1963 {
1964         __asm__ __volatile__(
1965                 ".set noreorder\n\t"
1966                 "tlbwr\n\t"
1967                 ".set reorder");
1968 }
1969 
1970 /*
1971  * Manipulate bits in a c0 register.
1972  */
1973 #define __BUILD_SET_C0(name)                                    \
1974 static inline unsigned int                                      \
1975 set_c0_##name(unsigned int set)                                 \
1976 {                                                               \
1977         unsigned int res, new;                                  \
1978                                                                 \
1979         res = read_c0_##name();                                 \
1980         new = res | set;                                        \
1981         write_c0_##name(new);                                   \
1982                                                                 \
1983         return res;                                             \
1984 }                                                               \
1985                                                                 \
1986 static inline unsigned int                                      \
1987 clear_c0_##name(unsigned int clear)                             \
1988 {                                                               \
1989         unsigned int res, new;                                  \
1990                                                                 \
1991         res = read_c0_##name();                                 \
1992         new = res & ~clear;                                     \
1993         write_c0_##name(new);                                   \
1994                                                                 \
1995         return res;                                             \
1996 }                                                               \
1997                                                                 \
1998 static inline unsigned int                                      \
1999 change_c0_##name(unsigned int change, unsigned int val)         \
2000 {                                                               \
2001         unsigned int res, new;                                  \
2002                                                                 \
2003         res = read_c0_##name();                                 \
2004         new = res & ~change;                                    \
2005         new |= (val & change);                                  \
2006         write_c0_##name(new);                                   \
2007                                                                 \
2008         return res;                                             \
2009 }
2010 
2011 __BUILD_SET_C0(status)
2012 __BUILD_SET_C0(cause)
2013 __BUILD_SET_C0(config)
2014 __BUILD_SET_C0(config5)
2015 __BUILD_SET_C0(intcontrol)
2016 __BUILD_SET_C0(intctl)
2017 __BUILD_SET_C0(srsmap)
2018 __BUILD_SET_C0(pagegrain)
2019 __BUILD_SET_C0(brcm_config_0)
2020 __BUILD_SET_C0(brcm_bus_pll)
2021 __BUILD_SET_C0(brcm_reset)
2022 __BUILD_SET_C0(brcm_cmt_intr)
2023 __BUILD_SET_C0(brcm_cmt_ctrl)
2024 __BUILD_SET_C0(brcm_config)
2025 __BUILD_SET_C0(brcm_mode)
2026 
2027 /*
2028  * Return low 10 bits of ebase.
2029  * Note that under KVM (MIPSVZ) this returns vcpu id.
2030  */
2031 static inline unsigned int get_ebase_cpunum(void)
2032 {
2033         return read_c0_ebase() & 0x3ff;
2034 }
2035 
2036 #endif /* !__ASSEMBLY__ */
2037 
2038 #endif /* _ASM_MIPSREGS_H */
2039 

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