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TOMOYO Linux Cross Reference
Linux/arch/mips/include/asm/netlogic/xlp-hal/pic.h

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  1 /*
  2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
  3  * reserved.
  4  *
  5  * This software is available to you under a choice of one of two
  6  * licenses.  You may choose to be licensed under the terms of the GNU
  7  * General Public License (GPL) Version 2, available from the file
  8  * COPYING in the main directory of this source tree, or the NetLogic
  9  * license below:
 10  *
 11  * Redistribution and use in source and binary forms, with or without
 12  * modification, are permitted provided that the following conditions
 13  * are met:
 14  *
 15  * 1. Redistributions of source code must retain the above copyright
 16  *    notice, this list of conditions and the following disclaimer.
 17  * 2. Redistributions in binary form must reproduce the above copyright
 18  *    notice, this list of conditions and the following disclaimer in
 19  *    the documentation and/or other materials provided with the
 20  *    distribution.
 21  *
 22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
 23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
 26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33  */
 34 
 35 #ifndef _NLM_HAL_PIC_H
 36 #define _NLM_HAL_PIC_H
 37 
 38 /* PIC Specific registers */
 39 #define PIC_CTRL                0x00
 40 
 41 /* PIC control register defines */
 42 #define PIC_CTRL_ITV            32 /* interrupt timeout value */
 43 #define PIC_CTRL_ICI            19 /* ICI interrupt timeout enable */
 44 #define PIC_CTRL_ITE            18 /* interrupt timeout enable */
 45 #define PIC_CTRL_STE            10 /* system timer interrupt enable */
 46 #define PIC_CTRL_WWR1           8  /* watchdog 1 wraparound count for reset */
 47 #define PIC_CTRL_WWR0           6  /* watchdog 0 wraparound count for reset */
 48 #define PIC_CTRL_WWN1           4  /* watchdog 1 wraparound count for NMI */
 49 #define PIC_CTRL_WWN0           2  /* watchdog 0 wraparound count for NMI */
 50 #define PIC_CTRL_WTE            0  /* watchdog timer enable */
 51 
 52 /* PIC Status register defines */
 53 #define PIC_ICI_STATUS          33 /* ICI interrupt timeout status */
 54 #define PIC_ITE_STATUS          32 /* interrupt timeout status */
 55 #define PIC_STS_STATUS          4  /* System timer interrupt status */
 56 #define PIC_WNS_STATUS          2  /* NMI status for watchdog timers */
 57 #define PIC_WIS_STATUS          0  /* Interrupt status for watchdog timers */
 58 
 59 /* PIC IPI control register offsets */
 60 #define PIC_IPICTRL_NMI         32
 61 #define PIC_IPICTRL_RIV         20 /* received interrupt vector */
 62 #define PIC_IPICTRL_IDB         16 /* interrupt destination base */
 63 #define PIC_IPICTRL_DTE          0 /* interrupt destination thread enables */
 64 
 65 /* PIC IRT register offsets */
 66 #define PIC_IRT_ENABLE          31
 67 #define PIC_IRT_NMI             29
 68 #define PIC_IRT_SCH             28 /* Scheduling scheme */
 69 #define PIC_IRT_RVEC            20 /* Interrupt receive vectors */
 70 #define PIC_IRT_DT              19 /* Destination type */
 71 #define PIC_IRT_DB              16 /* Destination base */
 72 #define PIC_IRT_DTE             0  /* Destination thread enables */
 73 
 74 #define PIC_BYTESWAP            0x02
 75 #define PIC_STATUS              0x04
 76 #define PIC_INTR_TIMEOUT        0x06
 77 #define PIC_ICI0_INTR_TIMEOUT   0x08
 78 #define PIC_ICI1_INTR_TIMEOUT   0x0a
 79 #define PIC_ICI2_INTR_TIMEOUT   0x0c
 80 #define PIC_IPI_CTL             0x0e
 81 #define PIC_INT_ACK             0x10
 82 #define PIC_INT_PENDING0        0x12
 83 #define PIC_INT_PENDING1        0x14
 84 #define PIC_INT_PENDING2        0x16
 85 
 86 #define PIC_WDOG0_MAXVAL        0x18
 87 #define PIC_WDOG0_COUNT         0x1a
 88 #define PIC_WDOG0_ENABLE0       0x1c
 89 #define PIC_WDOG0_ENABLE1       0x1e
 90 #define PIC_WDOG0_BEATCMD       0x20
 91 #define PIC_WDOG0_BEAT0         0x22
 92 #define PIC_WDOG0_BEAT1         0x24
 93 
 94 #define PIC_WDOG1_MAXVAL        0x26
 95 #define PIC_WDOG1_COUNT         0x28
 96 #define PIC_WDOG1_ENABLE0       0x2a
 97 #define PIC_WDOG1_ENABLE1       0x2c
 98 #define PIC_WDOG1_BEATCMD       0x2e
 99 #define PIC_WDOG1_BEAT0         0x30
100 #define PIC_WDOG1_BEAT1         0x32
101 
102 #define PIC_WDOG_MAXVAL(i)      (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
103 #define PIC_WDOG_COUNT(i)       (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
104 #define PIC_WDOG_ENABLE0(i)     (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
105 #define PIC_WDOG_ENABLE1(i)     (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
106 #define PIC_WDOG_BEATCMD(i)     (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
107 #define PIC_WDOG_BEAT0(i)       (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
108 #define PIC_WDOG_BEAT1(i)       (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
109 
110 #define PIC_TIMER0_MAXVAL    0x34
111 #define PIC_TIMER1_MAXVAL    0x36
112 #define PIC_TIMER2_MAXVAL    0x38
113 #define PIC_TIMER3_MAXVAL    0x3a
114 #define PIC_TIMER4_MAXVAL    0x3c
115 #define PIC_TIMER5_MAXVAL    0x3e
116 #define PIC_TIMER6_MAXVAL    0x40
117 #define PIC_TIMER7_MAXVAL    0x42
118 #define PIC_TIMER_MAXVAL(i)  (PIC_TIMER0_MAXVAL + ((i) * 2))
119 
120 #define PIC_TIMER0_COUNT     0x44
121 #define PIC_TIMER1_COUNT     0x46
122 #define PIC_TIMER2_COUNT     0x48
123 #define PIC_TIMER3_COUNT     0x4a
124 #define PIC_TIMER4_COUNT     0x4c
125 #define PIC_TIMER5_COUNT     0x4e
126 #define PIC_TIMER6_COUNT     0x50
127 #define PIC_TIMER7_COUNT     0x52
128 #define PIC_TIMER_COUNT(i)   (PIC_TIMER0_COUNT + ((i) * 2))
129 
130 #define PIC_ITE0_N0_N1          0x54
131 #define PIC_ITE1_N0_N1          0x58
132 #define PIC_ITE2_N0_N1          0x5c
133 #define PIC_ITE3_N0_N1          0x60
134 #define PIC_ITE4_N0_N1          0x64
135 #define PIC_ITE5_N0_N1          0x68
136 #define PIC_ITE6_N0_N1          0x6c
137 #define PIC_ITE7_N0_N1          0x70
138 #define PIC_ITE_N0_N1(i)        (PIC_ITE0_N0_N1 + ((i) * 4))
139 
140 #define PIC_ITE0_N2_N3          0x56
141 #define PIC_ITE1_N2_N3          0x5a
142 #define PIC_ITE2_N2_N3          0x5e
143 #define PIC_ITE3_N2_N3          0x62
144 #define PIC_ITE4_N2_N3          0x66
145 #define PIC_ITE5_N2_N3          0x6a
146 #define PIC_ITE6_N2_N3          0x6e
147 #define PIC_ITE7_N2_N3          0x72
148 #define PIC_ITE_N2_N3(i)        (PIC_ITE0_N2_N3 + ((i) * 4))
149 
150 #define PIC_IRT0                0x74
151 #define PIC_IRT(i)              (PIC_IRT0 + ((i) * 2))
152 
153 #define TIMER_CYCLES_MAXVAL     0xffffffffffffffffULL
154 
155 /*
156  *    IRT Map
157  */
158 #define PIC_NUM_IRTS            160
159 
160 #define PIC_IRT_WD_0_INDEX      0
161 #define PIC_IRT_WD_1_INDEX      1
162 #define PIC_IRT_WD_NMI_0_INDEX  2
163 #define PIC_IRT_WD_NMI_1_INDEX  3
164 #define PIC_IRT_TIMER_0_INDEX   4
165 #define PIC_IRT_TIMER_1_INDEX   5
166 #define PIC_IRT_TIMER_2_INDEX   6
167 #define PIC_IRT_TIMER_3_INDEX   7
168 #define PIC_IRT_TIMER_4_INDEX   8
169 #define PIC_IRT_TIMER_5_INDEX   9
170 #define PIC_IRT_TIMER_6_INDEX   10
171 #define PIC_IRT_TIMER_7_INDEX   11
172 #define PIC_IRT_CLOCK_INDEX     PIC_IRT_TIMER_7_INDEX
173 #define PIC_IRT_TIMER_INDEX(num)        ((num) + PIC_IRT_TIMER_0_INDEX)
174 
175 
176 /* 11 and 12 */
177 #define PIC_NUM_MSG_Q_IRTS      32
178 #define PIC_IRT_MSG_Q0_INDEX    12
179 #define PIC_IRT_MSG_Q_INDEX(qid)        ((qid) + PIC_IRT_MSG_Q0_INDEX)
180 /* 12 to 43 */
181 #define PIC_IRT_MSG_0_INDEX     44
182 #define PIC_IRT_MSG_1_INDEX     45
183 /* 44 and 45 */
184 #define PIC_NUM_PCIE_MSIX_IRTS  32
185 #define PIC_IRT_PCIE_MSIX_0_INDEX       46
186 #define PIC_IRT_PCIE_MSIX_INDEX(num)    ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
187 /* 46 to 77 */
188 #define PIC_NUM_PCIE_LINK_IRTS          4
189 #define PIC_IRT_PCIE_LINK_0_INDEX       78
190 #define PIC_IRT_PCIE_LINK_1_INDEX       79
191 #define PIC_IRT_PCIE_LINK_2_INDEX       80
192 #define PIC_IRT_PCIE_LINK_3_INDEX       81
193 #define PIC_IRT_PCIE_LINK_INDEX(num)    ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
194 
195 #define PIC_CLOCK_TIMER                 7
196 #define PIC_IRQ_BASE                    8
197 
198 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
199 
200 #define PIC_IRT_FIRST_IRQ               (PIC_IRQ_BASE)
201 #define PIC_IRT_LAST_IRQ                63
202 #define PIC_IRQ_IS_IRT(irq)             ((irq) >= PIC_IRT_FIRST_IRQ)
203 
204 /*
205  *   Misc
206  */
207 #define PIC_IRT_VALID                   1
208 #define PIC_LOCAL_SCHEDULING            1
209 #define PIC_GLOBAL_SCHEDULING           0
210 
211 #define PIC_CLK_HZ                      133333333
212 
213 #define nlm_read_pic_reg(b, r)  nlm_read_reg64(b, r)
214 #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
215 #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
216 #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
217 
218 /* IRT and h/w interrupt routines */
219 static inline int
220 nlm_pic_read_irt(uint64_t base, int irt_index)
221 {
222         return nlm_read_pic_reg(base, PIC_IRT(irt_index));
223 }
224 
225 static inline void
226 nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
227 {
228         uint64_t val;
229 
230         val = nlm_read_pic_reg(base, PIC_IRT(irt));
231         /* clear cpuset and mask */
232         val &= ~((0x7ull << 16) | 0xffff);
233         /* set DB, cpuset and cpumask */
234         val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf));
235         nlm_write_pic_reg(base, PIC_IRT(irt), val);
236 }
237 
238 static inline void
239 nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
240         int sch, int vec, int dt, int db, int dte)
241 {
242         uint64_t val;
243 
244         val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
245                         ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
246                         ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
247                         (dte & 0xffff);
248 
249         nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
250 }
251 
252 static inline void
253 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
254         int sch, int vec, int cpu)
255 {
256         nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
257                 (cpu >> 4),             /* thread group */
258                 1 << (cpu & 0xf));      /* thread mask */
259 }
260 
261 static inline uint64_t
262 nlm_pic_read_timer(uint64_t base, int timer)
263 {
264         return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
265 }
266 
267 static inline uint32_t
268 nlm_pic_read_timer32(uint64_t base, int timer)
269 {
270         return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
271 }
272 
273 static inline void
274 nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
275 {
276         nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
277 }
278 
279 static inline void
280 nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
281 {
282         uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
283         int en;
284 
285         en = (irq > 0);
286         nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
287         nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
288                 en, 0, 0, irq, cpu);
289 
290         /* enable the timer */
291         pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
292         nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
293 }
294 
295 static inline void
296 nlm_pic_enable_irt(uint64_t base, int irt)
297 {
298         uint64_t reg;
299 
300         reg = nlm_read_pic_reg(base, PIC_IRT(irt));
301         nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
302 }
303 
304 static inline void
305 nlm_pic_disable_irt(uint64_t base, int irt)
306 {
307         uint64_t reg;
308 
309         reg = nlm_read_pic_reg(base, PIC_IRT(irt));
310         nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
311 }
312 
313 static inline void
314 nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
315 {
316         uint64_t ipi;
317 
318         ipi = (nmi << 31) | (irq << 20);
319         ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */
320         nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
321 }
322 
323 static inline void
324 nlm_pic_ack(uint64_t base, int irt_num)
325 {
326         nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
327 
328         /* Ack the Status register for Watchdog & System timers */
329         if (irt_num < 12)
330                 nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
331 }
332 
333 static inline void
334 nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
335 {
336         nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt);
337 }
338 
339 int nlm_irq_to_irt(int irq);
340 
341 #endif /* __ASSEMBLY__ */
342 #endif /* _NLM_HAL_PIC_H */
343 

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