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Linux/arch/mips/include/asm/smtc.h

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  1 #ifndef _ASM_SMTC_MT_H
  2 #define _ASM_SMTC_MT_H
  3 
  4 /*
  5  * Definitions for SMTC multitasking on MIPS MT cores
  6  */
  7 
  8 #include <asm/mips_mt.h>
  9 #include <asm/smtc_ipi.h>
 10 
 11 /*
 12  * System-wide SMTC status information
 13  */
 14 
 15 extern unsigned int smtc_status;
 16 
 17 #define SMTC_TLB_SHARED 0x00000001
 18 #define SMTC_MTC_ACTIVE 0x00000002
 19 
 20 /*
 21  * TLB/ASID Management information
 22  */
 23 
 24 #define MAX_SMTC_TLBS 2
 25 #define MAX_SMTC_ASIDS 256
 26 #if NR_CPUS <= 8
 27 typedef char asiduse;
 28 #else
 29 #if NR_CPUS <= 16
 30 typedef short asiduse;
 31 #else
 32 typedef long asiduse;
 33 #endif
 34 #endif
 35 
 36 /*
 37  * VPE Management information
 38  */
 39 
 40 #define MAX_SMTC_VPES   MAX_SMTC_TLBS   /* FIXME: May not always be true. */
 41 
 42 extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
 43 
 44 struct mm_struct;
 45 struct task_struct;
 46 
 47 void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
 48 void self_ipi(struct smtc_ipi *);
 49 void smtc_flush_tlb_asid(unsigned long asid);
 50 extern int smtc_build_cpu_map(int startslot);
 51 extern void smtc_prepare_cpus(int cpus);
 52 extern void smtc_smp_finish(void);
 53 extern void smtc_boot_secondary(int cpu, struct task_struct *t);
 54 extern void smtc_cpus_done(void);
 55 extern void smtc_init_secondary(void);
 56 
 57 
 58 /*
 59  * Sharing the TLB between multiple VPEs means that the
 60  * "random" index selection function is not allowed to
 61  * select the current value of the Index register. To
 62  * avoid additional TLB pressure, the Index registers
 63  * are "parked" with an non-Valid value.
 64  */
 65 
 66 #define PARKED_INDEX    ((unsigned int)0x80000000)
 67 
 68 /*
 69  * Define low-level interrupt mask for IPIs, if necessary.
 70  * By default, use SW interrupt 1, which requires no external
 71  * hardware support, but which works only for single-core
 72  * MIPS MT systems.
 73  */
 74 #ifndef MIPS_CPU_IPI_IRQ
 75 #define MIPS_CPU_IPI_IRQ 1
 76 #endif
 77 
 78 #endif /*  _ASM_SMTC_MT_H */
 79 

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