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TOMOYO Linux Cross Reference
Linux/arch/mips/jz4740/gpio.c

Version: ~ [ linux-5.11-rc3 ] ~ [ linux-5.10.7 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.89 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.167 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.215 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.251 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.251 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.85 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3  *  JZ4740 platform GPIO support
  4  *
  5  *  This program is free software; you can redistribute it and/or modify it
  6  *  under  the terms of the GNU General  Public License as published by the
  7  *  Free Software Foundation;  either version 2 of the License, or (at your
  8  *  option) any later version.
  9  *
 10  *  You should have received a copy of the GNU General Public License along
 11  *  with this program; if not, write to the Free Software Foundation, Inc.,
 12  *  675 Mass Ave, Cambridge, MA 02139, USA.
 13  *
 14  */
 15 
 16 #include <linux/kernel.h>
 17 #include <linux/module.h>
 18 #include <linux/init.h>
 19 
 20 #include <linux/io.h>
 21 #include <linux/gpio.h>
 22 #include <linux/delay.h>
 23 #include <linux/interrupt.h>
 24 #include <linux/bitops.h>
 25 
 26 #include <linux/debugfs.h>
 27 #include <linux/seq_file.h>
 28 
 29 #include <asm/mach-jz4740/base.h>
 30 
 31 #include "irq.h"
 32 
 33 #define JZ4740_GPIO_BASE_A (32*0)
 34 #define JZ4740_GPIO_BASE_B (32*1)
 35 #define JZ4740_GPIO_BASE_C (32*2)
 36 #define JZ4740_GPIO_BASE_D (32*3)
 37 
 38 #define JZ4740_GPIO_NUM_A 32
 39 #define JZ4740_GPIO_NUM_B 32
 40 #define JZ4740_GPIO_NUM_C 31
 41 #define JZ4740_GPIO_NUM_D 32
 42 
 43 #define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
 44 #define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
 45 #define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
 46 #define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
 47 
 48 #define JZ_REG_GPIO_PIN                 0x00
 49 #define JZ_REG_GPIO_DATA                0x10
 50 #define JZ_REG_GPIO_DATA_SET            0x14
 51 #define JZ_REG_GPIO_DATA_CLEAR          0x18
 52 #define JZ_REG_GPIO_MASK                0x20
 53 #define JZ_REG_GPIO_MASK_SET            0x24
 54 #define JZ_REG_GPIO_MASK_CLEAR          0x28
 55 #define JZ_REG_GPIO_PULL                0x30
 56 #define JZ_REG_GPIO_PULL_SET            0x34
 57 #define JZ_REG_GPIO_PULL_CLEAR          0x38
 58 #define JZ_REG_GPIO_FUNC                0x40
 59 #define JZ_REG_GPIO_FUNC_SET            0x44
 60 #define JZ_REG_GPIO_FUNC_CLEAR          0x48
 61 #define JZ_REG_GPIO_SELECT              0x50
 62 #define JZ_REG_GPIO_SELECT_SET          0x54
 63 #define JZ_REG_GPIO_SELECT_CLEAR        0x58
 64 #define JZ_REG_GPIO_DIRECTION           0x60
 65 #define JZ_REG_GPIO_DIRECTION_SET       0x64
 66 #define JZ_REG_GPIO_DIRECTION_CLEAR     0x68
 67 #define JZ_REG_GPIO_TRIGGER             0x70
 68 #define JZ_REG_GPIO_TRIGGER_SET         0x74
 69 #define JZ_REG_GPIO_TRIGGER_CLEAR       0x78
 70 #define JZ_REG_GPIO_FLAG                0x80
 71 #define JZ_REG_GPIO_FLAG_CLEAR          0x14
 72 
 73 #define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
 74 #define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
 75 #define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
 76 
 77 struct jz_gpio_chip {
 78         unsigned int irq;
 79         unsigned int irq_base;
 80         uint32_t edge_trigger_both;
 81 
 82         void __iomem *base;
 83 
 84         struct gpio_chip gpio_chip;
 85 };
 86 
 87 static struct jz_gpio_chip jz4740_gpio_chips[];
 88 
 89 static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
 90 {
 91         return &jz4740_gpio_chips[gpio >> 5];
 92 }
 93 
 94 static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip)
 95 {
 96         return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
 97 }
 98 
 99 static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
100 {
101         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
102         return gc->private;
103 }
104 
105 static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
106 {
107         writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
108 }
109 
110 int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
111 {
112         if (function == JZ_GPIO_FUNC_NONE) {
113                 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
114                 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
115                 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
116         } else {
117                 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
118                 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
119                 switch (function) {
120                 case JZ_GPIO_FUNC1:
121                         jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
122                         break;
123                 case JZ_GPIO_FUNC3:
124                         jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
125                 case JZ_GPIO_FUNC2: /* Falltrough */
126                         jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
127                         break;
128                 default:
129                         BUG();
130                         break;
131                 }
132         }
133 
134         return 0;
135 }
136 EXPORT_SYMBOL_GPL(jz_gpio_set_function);
137 
138 int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
139 {
140         size_t i;
141         int ret;
142 
143         for (i = 0; i < num; ++i, ++request) {
144                 ret = gpio_request(request->gpio, request->name);
145                 if (ret)
146                         goto err;
147                 jz_gpio_set_function(request->gpio, request->function);
148         }
149 
150         return 0;
151 
152 err:
153         for (--request; i > 0; --i, --request) {
154                 gpio_free(request->gpio);
155                 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
156         }
157 
158         return ret;
159 }
160 EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
161 
162 void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
163 {
164         size_t i;
165 
166         for (i = 0; i < num; ++i, ++request) {
167                 gpio_free(request->gpio);
168                 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
169         }
170 
171 }
172 EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
173 
174 void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
175 {
176         size_t i;
177 
178         for (i = 0; i < num; ++i, ++request) {
179                 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
180                 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
181                 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
182         }
183 }
184 EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
185 
186 void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
187 {
188         size_t i;
189 
190         for (i = 0; i < num; ++i, ++request)
191                 jz_gpio_set_function(request->gpio, request->function);
192 }
193 EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
194 
195 void jz_gpio_enable_pullup(unsigned gpio)
196 {
197         jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
198 }
199 EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
200 
201 void jz_gpio_disable_pullup(unsigned gpio)
202 {
203         jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
204 }
205 EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
206 
207 static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
208 {
209         return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
210 }
211 
212 static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
213 {
214         uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
215         reg += !value;
216         writel(BIT(gpio), reg);
217 }
218 
219 static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
220         int value)
221 {
222         writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
223         jz_gpio_set_value(chip, gpio, value);
224 
225         return 0;
226 }
227 
228 static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
229 {
230         writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
231 
232         return 0;
233 }
234 
235 int jz_gpio_port_direction_input(int port, uint32_t mask)
236 {
237         writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
238 
239         return 0;
240 }
241 EXPORT_SYMBOL(jz_gpio_port_direction_input);
242 
243 int jz_gpio_port_direction_output(int port, uint32_t mask)
244 {
245         writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
246 
247         return 0;
248 }
249 EXPORT_SYMBOL(jz_gpio_port_direction_output);
250 
251 void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
252 {
253         writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
254         writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
255 }
256 EXPORT_SYMBOL(jz_gpio_port_set_value);
257 
258 uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
259 {
260         uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
261 
262         return value & mask;
263 }
264 EXPORT_SYMBOL(jz_gpio_port_get_value);
265 
266 int gpio_to_irq(unsigned gpio)
267 {
268         return JZ4740_IRQ_GPIO(0) + gpio;
269 }
270 EXPORT_SYMBOL_GPL(gpio_to_irq);
271 
272 int irq_to_gpio(unsigned irq)
273 {
274         return irq - JZ4740_IRQ_GPIO(0);
275 }
276 EXPORT_SYMBOL_GPL(irq_to_gpio);
277 
278 #define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
279 
280 static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
281 {
282         uint32_t value;
283         void __iomem *reg;
284         uint32_t mask = IRQ_TO_BIT(irq);
285 
286         if (!(chip->edge_trigger_both & mask))
287                 return;
288 
289         reg = chip->base;
290 
291         value = readl(chip->base + JZ_REG_GPIO_PIN);
292         if (value & mask)
293                 reg += JZ_REG_GPIO_DIRECTION_CLEAR;
294         else
295                 reg += JZ_REG_GPIO_DIRECTION_SET;
296 
297         writel(mask, reg);
298 }
299 
300 static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
301 {
302         uint32_t flag;
303         unsigned int gpio_irq;
304         struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
305 
306         flag = readl(chip->base + JZ_REG_GPIO_FLAG);
307         if (!flag)
308                 return;
309 
310         gpio_irq = chip->irq_base + __fls(flag);
311 
312         jz_gpio_check_trigger_both(chip, gpio_irq);
313 
314         generic_handle_irq(gpio_irq);
315 };
316 
317 static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
318 {
319         struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
320         writel(IRQ_TO_BIT(data->irq), chip->base + reg);
321 }
322 
323 static void jz_gpio_irq_unmask(struct irq_data *data)
324 {
325         struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
326 
327         jz_gpio_check_trigger_both(chip, data->irq);
328         irq_gc_unmask_enable_reg(data);
329 };
330 
331 /* TODO: Check if function is gpio */
332 static unsigned int jz_gpio_irq_startup(struct irq_data *data)
333 {
334         jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
335         jz_gpio_irq_unmask(data);
336         return 0;
337 }
338 
339 static void jz_gpio_irq_shutdown(struct irq_data *data)
340 {
341         irq_gc_mask_disable_reg(data);
342 
343         /* Set direction to input */
344         jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
345         jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
346 }
347 
348 static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
349 {
350         struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
351         unsigned int irq = data->irq;
352 
353         if (flow_type == IRQ_TYPE_EDGE_BOTH) {
354                 uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
355                 if (value & IRQ_TO_BIT(irq))
356                         flow_type = IRQ_TYPE_EDGE_FALLING;
357                 else
358                         flow_type = IRQ_TYPE_EDGE_RISING;
359                 chip->edge_trigger_both |= IRQ_TO_BIT(irq);
360         } else {
361                 chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
362         }
363 
364         switch (flow_type) {
365         case IRQ_TYPE_EDGE_RISING:
366                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
367                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
368                 break;
369         case IRQ_TYPE_EDGE_FALLING:
370                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
371                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
372                 break;
373         case IRQ_TYPE_LEVEL_HIGH:
374                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
375                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
376                 break;
377         case IRQ_TYPE_LEVEL_LOW:
378                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
379                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
380                 break;
381         default:
382                 return -EINVAL;
383         }
384 
385         return 0;
386 }
387 
388 static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
389 {
390         struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
391 
392         irq_gc_set_wake(data, on);
393         irq_set_irq_wake(chip->irq, on);
394 
395         return 0;
396 }
397 
398 #define JZ4740_GPIO_CHIP(_bank) { \
399         .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
400         .gpio_chip = { \
401                 .label = "Bank " # _bank, \
402                 .owner = THIS_MODULE, \
403                 .set = jz_gpio_set_value, \
404                 .get = jz_gpio_get_value, \
405                 .direction_output = jz_gpio_direction_output, \
406                 .direction_input = jz_gpio_direction_input, \
407                 .base = JZ4740_GPIO_BASE_ ## _bank, \
408                 .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
409         }, \
410 }
411 
412 static struct jz_gpio_chip jz4740_gpio_chips[] = {
413         JZ4740_GPIO_CHIP(A),
414         JZ4740_GPIO_CHIP(B),
415         JZ4740_GPIO_CHIP(C),
416         JZ4740_GPIO_CHIP(D),
417 };
418 
419 static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
420 {
421         struct irq_chip_generic *gc;
422         struct irq_chip_type *ct;
423 
424         chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
425 
426         chip->irq = JZ4740_IRQ_INTC_GPIO(id);
427         irq_set_handler_data(chip->irq, chip);
428         irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
429 
430         gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base,
431                 chip->base, handle_level_irq);
432 
433         gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio);
434         gc->private = chip;
435 
436         ct = gc->chip_types;
437         ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR;
438         ct->regs.disable = JZ_REG_GPIO_MASK_SET;
439         ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR;
440 
441         ct->chip.name = "GPIO";
442         ct->chip.irq_mask = irq_gc_mask_disable_reg;
443         ct->chip.irq_unmask = jz_gpio_irq_unmask;
444         ct->chip.irq_ack = irq_gc_ack_set_bit;
445         ct->chip.irq_suspend = jz4740_irq_suspend;
446         ct->chip.irq_resume = jz4740_irq_resume;
447         ct->chip.irq_startup = jz_gpio_irq_startup;
448         ct->chip.irq_shutdown = jz_gpio_irq_shutdown;
449         ct->chip.irq_set_type = jz_gpio_irq_set_type;
450         ct->chip.irq_set_wake = jz_gpio_irq_set_wake;
451         ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
452 
453         irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio),
454                 IRQ_GC_INIT_NESTED_LOCK, 0, IRQ_NOPROBE | IRQ_LEVEL);
455 
456         gpiochip_add(&chip->gpio_chip);
457 }
458 
459 static int __init jz4740_gpio_init(void)
460 {
461         unsigned int i;
462 
463         for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
464                 jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
465 
466         printk(KERN_INFO "JZ4740 GPIO initialized\n");
467 
468         return 0;
469 }
470 arch_initcall(jz4740_gpio_init);
471 
472 #ifdef CONFIG_DEBUG_FS
473 
474 static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
475         const char *name, unsigned int reg)
476 {
477         seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
478 }
479 
480 static int gpio_regs_show(struct seq_file *s, void *unused)
481 {
482         struct jz_gpio_chip *chip = jz4740_gpio_chips;
483         int i;
484 
485         for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
486                 seq_printf(s, "==GPIO %d==\n", i);
487                 gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
488                 gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
489                 gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
490                 gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
491                 gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
492                 gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
493                 gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
494                 gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
495                 gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
496         }
497 
498         return 0;
499 }
500 
501 static int gpio_regs_open(struct inode *inode, struct file *file)
502 {
503         return single_open(file, gpio_regs_show, NULL);
504 }
505 
506 static const struct file_operations gpio_regs_operations = {
507         .open           = gpio_regs_open,
508         .read           = seq_read,
509         .llseek         = seq_lseek,
510         .release        = single_release,
511 };
512 
513 static int __init gpio_debugfs_init(void)
514 {
515         (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
516                                 NULL, NULL, &gpio_regs_operations);
517         return 0;
518 }
519 subsys_initcall(gpio_debugfs_init);
520 
521 #endif
522 

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