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TOMOYO Linux Cross Reference
Linux/arch/mips/jz4740/gpio.c

Version: ~ [ linux-5.1.2 ] ~ [ linux-5.0.16 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.43 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.119 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.176 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.179 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.139 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.67 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.39.4 ] ~ [ linux-2.6.38.8 ] ~ [ linux-2.6.37.6 ] ~ [ linux-2.6.36.4 ] ~ [ linux-2.6.35.14 ] ~ [ linux-2.6.34.15 ] ~ [ linux-2.6.33.20 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3  *  JZ4740 platform GPIO support
  4  *
  5  *  This program is free software; you can redistribute it and/or modify it
  6  *  under  the terms of the GNU General  Public License as published by the
  7  *  Free Software Foundation;  either version 2 of the License, or (at your
  8  *  option) any later version.
  9  *
 10  *  You should have received a copy of the GNU General Public License along
 11  *  with this program; if not, write to the Free Software Foundation, Inc.,
 12  *  675 Mass Ave, Cambridge, MA 02139, USA.
 13  *
 14  */
 15 
 16 #include <linux/kernel.h>
 17 #include <linux/module.h>
 18 #include <linux/init.h>
 19 
 20 #include <linux/io.h>
 21 #include <linux/gpio/driver.h>
 22 /* FIXME: needed for gpio_request(), try to remove consumer API from driver */
 23 #include <linux/gpio.h>
 24 #include <linux/delay.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/irqchip/ingenic.h>
 27 #include <linux/bitops.h>
 28 
 29 #include <linux/debugfs.h>
 30 #include <linux/seq_file.h>
 31 
 32 #include <asm/mach-jz4740/base.h>
 33 #include <asm/mach-jz4740/gpio.h>
 34 
 35 #define JZ4740_GPIO_BASE_A (32*0)
 36 #define JZ4740_GPIO_BASE_B (32*1)
 37 #define JZ4740_GPIO_BASE_C (32*2)
 38 #define JZ4740_GPIO_BASE_D (32*3)
 39 
 40 #define JZ4740_GPIO_NUM_A 32
 41 #define JZ4740_GPIO_NUM_B 32
 42 #define JZ4740_GPIO_NUM_C 31
 43 #define JZ4740_GPIO_NUM_D 32
 44 
 45 #define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
 46 #define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
 47 #define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
 48 #define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
 49 
 50 #define JZ_REG_GPIO_PIN                 0x00
 51 #define JZ_REG_GPIO_DATA                0x10
 52 #define JZ_REG_GPIO_DATA_SET            0x14
 53 #define JZ_REG_GPIO_DATA_CLEAR          0x18
 54 #define JZ_REG_GPIO_MASK                0x20
 55 #define JZ_REG_GPIO_MASK_SET            0x24
 56 #define JZ_REG_GPIO_MASK_CLEAR          0x28
 57 #define JZ_REG_GPIO_PULL                0x30
 58 #define JZ_REG_GPIO_PULL_SET            0x34
 59 #define JZ_REG_GPIO_PULL_CLEAR          0x38
 60 #define JZ_REG_GPIO_FUNC                0x40
 61 #define JZ_REG_GPIO_FUNC_SET            0x44
 62 #define JZ_REG_GPIO_FUNC_CLEAR          0x48
 63 #define JZ_REG_GPIO_SELECT              0x50
 64 #define JZ_REG_GPIO_SELECT_SET          0x54
 65 #define JZ_REG_GPIO_SELECT_CLEAR        0x58
 66 #define JZ_REG_GPIO_DIRECTION           0x60
 67 #define JZ_REG_GPIO_DIRECTION_SET       0x64
 68 #define JZ_REG_GPIO_DIRECTION_CLEAR     0x68
 69 #define JZ_REG_GPIO_TRIGGER             0x70
 70 #define JZ_REG_GPIO_TRIGGER_SET         0x74
 71 #define JZ_REG_GPIO_TRIGGER_CLEAR       0x78
 72 #define JZ_REG_GPIO_FLAG                0x80
 73 #define JZ_REG_GPIO_FLAG_CLEAR          0x14
 74 
 75 #define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
 76 #define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
 77 #define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
 78 
 79 struct jz_gpio_chip {
 80         unsigned int irq;
 81         unsigned int irq_base;
 82         uint32_t edge_trigger_both;
 83 
 84         void __iomem *base;
 85 
 86         struct gpio_chip gpio_chip;
 87 };
 88 
 89 static struct jz_gpio_chip jz4740_gpio_chips[];
 90 
 91 static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
 92 {
 93         return &jz4740_gpio_chips[gpio >> 5];
 94 }
 95 
 96 static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gc)
 97 {
 98         return gpiochip_get_data(gc);
 99 }
100 
101 static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
102 {
103         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
104         return gc->private;
105 }
106 
107 static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
108 {
109         writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
110 }
111 
112 int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
113 {
114         if (function == JZ_GPIO_FUNC_NONE) {
115                 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
116                 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
117                 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
118         } else {
119                 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
120                 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
121                 switch (function) {
122                 case JZ_GPIO_FUNC1:
123                         jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
124                         break;
125                 case JZ_GPIO_FUNC3:
126                         jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
127                 case JZ_GPIO_FUNC2: /* Falltrough */
128                         jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
129                         break;
130                 default:
131                         BUG();
132                         break;
133                 }
134         }
135 
136         return 0;
137 }
138 EXPORT_SYMBOL_GPL(jz_gpio_set_function);
139 
140 int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
141 {
142         size_t i;
143         int ret;
144 
145         for (i = 0; i < num; ++i, ++request) {
146                 ret = gpio_request(request->gpio, request->name);
147                 if (ret)
148                         goto err;
149                 jz_gpio_set_function(request->gpio, request->function);
150         }
151 
152         return 0;
153 
154 err:
155         for (--request; i > 0; --i, --request) {
156                 gpio_free(request->gpio);
157                 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
158         }
159 
160         return ret;
161 }
162 EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
163 
164 void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
165 {
166         size_t i;
167 
168         for (i = 0; i < num; ++i, ++request) {
169                 gpio_free(request->gpio);
170                 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
171         }
172 
173 }
174 EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
175 
176 void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
177 {
178         size_t i;
179 
180         for (i = 0; i < num; ++i, ++request) {
181                 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
182                 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
183                 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
184         }
185 }
186 EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
187 
188 void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
189 {
190         size_t i;
191 
192         for (i = 0; i < num; ++i, ++request)
193                 jz_gpio_set_function(request->gpio, request->function);
194 }
195 EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
196 
197 void jz_gpio_enable_pullup(unsigned gpio)
198 {
199         jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
200 }
201 EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
202 
203 void jz_gpio_disable_pullup(unsigned gpio)
204 {
205         jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
206 }
207 EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
208 
209 static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
210 {
211         return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
212 }
213 
214 static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
215 {
216         uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
217         reg += !value;
218         writel(BIT(gpio), reg);
219 }
220 
221 static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
222         int value)
223 {
224         writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
225         jz_gpio_set_value(chip, gpio, value);
226 
227         return 0;
228 }
229 
230 static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
231 {
232         writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
233 
234         return 0;
235 }
236 
237 static int jz_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
238 {
239         struct jz_gpio_chip *jz_gpio = gpiochip_get_data(chip);
240 
241         return jz_gpio->irq_base + gpio;
242 }
243 
244 int jz_gpio_port_direction_input(int port, uint32_t mask)
245 {
246         writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
247 
248         return 0;
249 }
250 EXPORT_SYMBOL(jz_gpio_port_direction_input);
251 
252 int jz_gpio_port_direction_output(int port, uint32_t mask)
253 {
254         writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
255 
256         return 0;
257 }
258 EXPORT_SYMBOL(jz_gpio_port_direction_output);
259 
260 void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
261 {
262         writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
263         writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
264 }
265 EXPORT_SYMBOL(jz_gpio_port_set_value);
266 
267 uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
268 {
269         uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
270 
271         return value & mask;
272 }
273 EXPORT_SYMBOL(jz_gpio_port_get_value);
274 
275 #define IRQ_TO_BIT(irq) BIT((irq - JZ4740_IRQ_GPIO(0)) & 0x1f)
276 
277 static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
278 {
279         uint32_t value;
280         void __iomem *reg;
281         uint32_t mask = IRQ_TO_BIT(irq);
282 
283         if (!(chip->edge_trigger_both & mask))
284                 return;
285 
286         reg = chip->base;
287 
288         value = readl(chip->base + JZ_REG_GPIO_PIN);
289         if (value & mask)
290                 reg += JZ_REG_GPIO_DIRECTION_CLEAR;
291         else
292                 reg += JZ_REG_GPIO_DIRECTION_SET;
293 
294         writel(mask, reg);
295 }
296 
297 static void jz_gpio_irq_demux_handler(struct irq_desc *desc)
298 {
299         uint32_t flag;
300         unsigned int gpio_irq;
301         struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
302 
303         flag = readl(chip->base + JZ_REG_GPIO_FLAG);
304         if (!flag)
305                 return;
306 
307         gpio_irq = chip->irq_base + __fls(flag);
308 
309         jz_gpio_check_trigger_both(chip, gpio_irq);
310 
311         generic_handle_irq(gpio_irq);
312 };
313 
314 static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
315 {
316         struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
317         writel(IRQ_TO_BIT(data->irq), chip->base + reg);
318 }
319 
320 static void jz_gpio_irq_unmask(struct irq_data *data)
321 {
322         struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
323 
324         jz_gpio_check_trigger_both(chip, data->irq);
325         irq_gc_unmask_enable_reg(data);
326 };
327 
328 /* TODO: Check if function is gpio */
329 static unsigned int jz_gpio_irq_startup(struct irq_data *data)
330 {
331         jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
332         jz_gpio_irq_unmask(data);
333         return 0;
334 }
335 
336 static void jz_gpio_irq_shutdown(struct irq_data *data)
337 {
338         irq_gc_mask_disable_reg(data);
339 
340         /* Set direction to input */
341         jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
342         jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
343 }
344 
345 static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
346 {
347         struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
348         unsigned int irq = data->irq;
349 
350         if (flow_type == IRQ_TYPE_EDGE_BOTH) {
351                 uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
352                 if (value & IRQ_TO_BIT(irq))
353                         flow_type = IRQ_TYPE_EDGE_FALLING;
354                 else
355                         flow_type = IRQ_TYPE_EDGE_RISING;
356                 chip->edge_trigger_both |= IRQ_TO_BIT(irq);
357         } else {
358                 chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
359         }
360 
361         switch (flow_type) {
362         case IRQ_TYPE_EDGE_RISING:
363                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
364                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
365                 break;
366         case IRQ_TYPE_EDGE_FALLING:
367                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
368                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
369                 break;
370         case IRQ_TYPE_LEVEL_HIGH:
371                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
372                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
373                 break;
374         case IRQ_TYPE_LEVEL_LOW:
375                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
376                 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
377                 break;
378         default:
379                 return -EINVAL;
380         }
381 
382         return 0;
383 }
384 
385 static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
386 {
387         struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
388 
389         irq_gc_set_wake(data, on);
390         irq_set_irq_wake(chip->irq, on);
391 
392         return 0;
393 }
394 
395 #define JZ4740_GPIO_CHIP(_bank) { \
396         .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
397         .gpio_chip = { \
398                 .label = "Bank " # _bank, \
399                 .owner = THIS_MODULE, \
400                 .set = jz_gpio_set_value, \
401                 .get = jz_gpio_get_value, \
402                 .direction_output = jz_gpio_direction_output, \
403                 .direction_input = jz_gpio_direction_input, \
404                 .to_irq = jz_gpio_to_irq, \
405                 .base = JZ4740_GPIO_BASE_ ## _bank, \
406                 .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
407         }, \
408 }
409 
410 static struct jz_gpio_chip jz4740_gpio_chips[] = {
411         JZ4740_GPIO_CHIP(A),
412         JZ4740_GPIO_CHIP(B),
413         JZ4740_GPIO_CHIP(C),
414         JZ4740_GPIO_CHIP(D),
415 };
416 
417 static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
418 {
419         struct irq_chip_generic *gc;
420         struct irq_chip_type *ct;
421 
422         chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
423 
424         chip->irq = JZ4740_IRQ_INTC_GPIO(id);
425         irq_set_chained_handler_and_data(chip->irq,
426                                          jz_gpio_irq_demux_handler, chip);
427 
428         gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base,
429                 chip->base, handle_level_irq);
430 
431         gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio);
432         gc->private = chip;
433 
434         ct = gc->chip_types;
435         ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR;
436         ct->regs.disable = JZ_REG_GPIO_MASK_SET;
437         ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR;
438 
439         ct->chip.name = "GPIO";
440         ct->chip.irq_mask = irq_gc_mask_disable_reg;
441         ct->chip.irq_unmask = jz_gpio_irq_unmask;
442         ct->chip.irq_ack = irq_gc_ack_set_bit;
443         ct->chip.irq_suspend = ingenic_intc_irq_suspend;
444         ct->chip.irq_resume = ingenic_intc_irq_resume;
445         ct->chip.irq_startup = jz_gpio_irq_startup;
446         ct->chip.irq_shutdown = jz_gpio_irq_shutdown;
447         ct->chip.irq_set_type = jz_gpio_irq_set_type;
448         ct->chip.irq_set_wake = jz_gpio_irq_set_wake;
449         ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
450 
451         irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio),
452                 IRQ_GC_INIT_NESTED_LOCK, 0, IRQ_NOPROBE | IRQ_LEVEL);
453 
454         gpiochip_add_data(&chip->gpio_chip, chip);
455 }
456 
457 static int __init jz4740_gpio_init(void)
458 {
459         unsigned int i;
460 
461         for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
462                 jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
463 
464         printk(KERN_INFO "JZ4740 GPIO initialized\n");
465 
466         return 0;
467 }
468 arch_initcall(jz4740_gpio_init);
469 
470 #ifdef CONFIG_DEBUG_FS
471 
472 static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
473         const char *name, unsigned int reg)
474 {
475         seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
476 }
477 
478 static int gpio_regs_show(struct seq_file *s, void *unused)
479 {
480         struct jz_gpio_chip *chip = jz4740_gpio_chips;
481         int i;
482 
483         for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
484                 seq_printf(s, "==GPIO %d==\n", i);
485                 gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
486                 gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
487                 gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
488                 gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
489                 gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
490                 gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
491                 gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
492                 gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
493                 gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
494         }
495 
496         return 0;
497 }
498 
499 static int gpio_regs_open(struct inode *inode, struct file *file)
500 {
501         return single_open(file, gpio_regs_show, NULL);
502 }
503 
504 static const struct file_operations gpio_regs_operations = {
505         .open           = gpio_regs_open,
506         .read           = seq_read,
507         .llseek         = seq_lseek,
508         .release        = single_release,
509 };
510 
511 static int __init gpio_debugfs_init(void)
512 {
513         (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
514                                 NULL, NULL, &gpio_regs_operations);
515         return 0;
516 }
517 subsys_initcall(gpio_debugfs_init);
518 
519 #endif
520 

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