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TOMOYO Linux Cross Reference
Linux/arch/mips/kernel/asm-offsets.c

Version: ~ [ linux-5.9-rc6 ] ~ [ linux-5.8.10 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.66 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.146 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.198 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.236 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.236 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.85 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * asm-offsets.c: Calculate pt_regs and task_struct offsets.
  3  *
  4  * Copyright (C) 1996 David S. Miller
  5  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
  6  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  7  *
  8  * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  9  * Copyright (C) 2000 MIPS Technologies, Inc.
 10  */
 11 #include <linux/compat.h>
 12 #include <linux/types.h>
 13 #include <linux/sched.h>
 14 #include <linux/mm.h>
 15 #include <linux/kbuild.h>
 16 #include <linux/suspend.h>
 17 #include <asm/pm.h>
 18 #include <asm/ptrace.h>
 19 #include <asm/processor.h>
 20 #include <asm/smp-cps.h>
 21 
 22 #include <linux/kvm_host.h>
 23 
 24 void output_ptreg_defines(void)
 25 {
 26         COMMENT("MIPS pt_regs offsets.");
 27         OFFSET(PT_R0, pt_regs, regs[0]);
 28         OFFSET(PT_R1, pt_regs, regs[1]);
 29         OFFSET(PT_R2, pt_regs, regs[2]);
 30         OFFSET(PT_R3, pt_regs, regs[3]);
 31         OFFSET(PT_R4, pt_regs, regs[4]);
 32         OFFSET(PT_R5, pt_regs, regs[5]);
 33         OFFSET(PT_R6, pt_regs, regs[6]);
 34         OFFSET(PT_R7, pt_regs, regs[7]);
 35         OFFSET(PT_R8, pt_regs, regs[8]);
 36         OFFSET(PT_R9, pt_regs, regs[9]);
 37         OFFSET(PT_R10, pt_regs, regs[10]);
 38         OFFSET(PT_R11, pt_regs, regs[11]);
 39         OFFSET(PT_R12, pt_regs, regs[12]);
 40         OFFSET(PT_R13, pt_regs, regs[13]);
 41         OFFSET(PT_R14, pt_regs, regs[14]);
 42         OFFSET(PT_R15, pt_regs, regs[15]);
 43         OFFSET(PT_R16, pt_regs, regs[16]);
 44         OFFSET(PT_R17, pt_regs, regs[17]);
 45         OFFSET(PT_R18, pt_regs, regs[18]);
 46         OFFSET(PT_R19, pt_regs, regs[19]);
 47         OFFSET(PT_R20, pt_regs, regs[20]);
 48         OFFSET(PT_R21, pt_regs, regs[21]);
 49         OFFSET(PT_R22, pt_regs, regs[22]);
 50         OFFSET(PT_R23, pt_regs, regs[23]);
 51         OFFSET(PT_R24, pt_regs, regs[24]);
 52         OFFSET(PT_R25, pt_regs, regs[25]);
 53         OFFSET(PT_R26, pt_regs, regs[26]);
 54         OFFSET(PT_R27, pt_regs, regs[27]);
 55         OFFSET(PT_R28, pt_regs, regs[28]);
 56         OFFSET(PT_R29, pt_regs, regs[29]);
 57         OFFSET(PT_R30, pt_regs, regs[30]);
 58         OFFSET(PT_R31, pt_regs, regs[31]);
 59         OFFSET(PT_LO, pt_regs, lo);
 60         OFFSET(PT_HI, pt_regs, hi);
 61 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 62         OFFSET(PT_ACX, pt_regs, acx);
 63 #endif
 64         OFFSET(PT_EPC, pt_regs, cp0_epc);
 65         OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
 66         OFFSET(PT_STATUS, pt_regs, cp0_status);
 67         OFFSET(PT_CAUSE, pt_regs, cp0_cause);
 68 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 69         OFFSET(PT_MPL, pt_regs, mpl);
 70         OFFSET(PT_MTP, pt_regs, mtp);
 71 #endif /* CONFIG_CPU_CAVIUM_OCTEON */
 72         DEFINE(PT_SIZE, sizeof(struct pt_regs));
 73         BLANK();
 74 }
 75 
 76 void output_task_defines(void)
 77 {
 78         COMMENT("MIPS task_struct offsets.");
 79         OFFSET(TASK_STATE, task_struct, state);
 80         OFFSET(TASK_THREAD_INFO, task_struct, stack);
 81         OFFSET(TASK_FLAGS, task_struct, flags);
 82         OFFSET(TASK_MM, task_struct, mm);
 83         OFFSET(TASK_PID, task_struct, pid);
 84 #if defined(CONFIG_CC_STACKPROTECTOR)
 85         OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
 86 #endif
 87         DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
 88         BLANK();
 89 }
 90 
 91 void output_thread_info_defines(void)
 92 {
 93         COMMENT("MIPS thread_info offsets.");
 94         OFFSET(TI_TASK, thread_info, task);
 95         OFFSET(TI_FLAGS, thread_info, flags);
 96         OFFSET(TI_TP_VALUE, thread_info, tp_value);
 97         OFFSET(TI_CPU, thread_info, cpu);
 98         OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
 99         OFFSET(TI_R2_EMUL_RET, thread_info, r2_emul_return);
100         OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
101         OFFSET(TI_REGS, thread_info, regs);
102         DEFINE(_THREAD_SIZE, THREAD_SIZE);
103         DEFINE(_THREAD_MASK, THREAD_MASK);
104         BLANK();
105 }
106 
107 void output_thread_defines(void)
108 {
109         COMMENT("MIPS specific thread_struct offsets.");
110         OFFSET(THREAD_REG16, task_struct, thread.reg16);
111         OFFSET(THREAD_REG17, task_struct, thread.reg17);
112         OFFSET(THREAD_REG18, task_struct, thread.reg18);
113         OFFSET(THREAD_REG19, task_struct, thread.reg19);
114         OFFSET(THREAD_REG20, task_struct, thread.reg20);
115         OFFSET(THREAD_REG21, task_struct, thread.reg21);
116         OFFSET(THREAD_REG22, task_struct, thread.reg22);
117         OFFSET(THREAD_REG23, task_struct, thread.reg23);
118         OFFSET(THREAD_REG29, task_struct, thread.reg29);
119         OFFSET(THREAD_REG30, task_struct, thread.reg30);
120         OFFSET(THREAD_REG31, task_struct, thread.reg31);
121         OFFSET(THREAD_STATUS, task_struct,
122                thread.cp0_status);
123         OFFSET(THREAD_FPU, task_struct, thread.fpu);
124 
125         OFFSET(THREAD_BVADDR, task_struct, \
126                thread.cp0_badvaddr);
127         OFFSET(THREAD_BUADDR, task_struct, \
128                thread.cp0_baduaddr);
129         OFFSET(THREAD_ECODE, task_struct, \
130                thread.error_code);
131         BLANK();
132 }
133 
134 void output_thread_fpu_defines(void)
135 {
136         OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
137         OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
138         OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
139         OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
140         OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
141         OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
142         OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
143         OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
144         OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
145         OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
146         OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
147         OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
148         OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
149         OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
150         OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
151         OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
152         OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
153         OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
154         OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
155         OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
156         OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
157         OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
158         OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
159         OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
160         OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
161         OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
162         OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
163         OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
164         OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
165         OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
166         OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
167         OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
168 
169         OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
170         OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
171         BLANK();
172 }
173 
174 void output_mm_defines(void)
175 {
176         COMMENT("Size of struct page");
177         DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
178         BLANK();
179         COMMENT("Linux mm_struct offsets.");
180         OFFSET(MM_USERS, mm_struct, mm_users);
181         OFFSET(MM_PGD, mm_struct, pgd);
182         OFFSET(MM_CONTEXT, mm_struct, context);
183         BLANK();
184         DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
185         DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
186         DEFINE(_PTE_T_SIZE, sizeof(pte_t));
187         BLANK();
188         DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
189 #ifndef __PAGETABLE_PMD_FOLDED
190         DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
191 #endif
192         DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
193         BLANK();
194         DEFINE(_PGD_ORDER, PGD_ORDER);
195 #ifndef __PAGETABLE_PMD_FOLDED
196         DEFINE(_PMD_ORDER, PMD_ORDER);
197 #endif
198         DEFINE(_PTE_ORDER, PTE_ORDER);
199         BLANK();
200         DEFINE(_PMD_SHIFT, PMD_SHIFT);
201         DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
202         BLANK();
203         DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
204         DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
205         DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
206         BLANK();
207         DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
208         DEFINE(_PAGE_SIZE, PAGE_SIZE);
209         BLANK();
210 }
211 
212 #ifdef CONFIG_32BIT
213 void output_sc_defines(void)
214 {
215         COMMENT("Linux sigcontext offsets.");
216         OFFSET(SC_REGS, sigcontext, sc_regs);
217         OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
218         OFFSET(SC_ACX, sigcontext, sc_acx);
219         OFFSET(SC_MDHI, sigcontext, sc_mdhi);
220         OFFSET(SC_MDLO, sigcontext, sc_mdlo);
221         OFFSET(SC_PC, sigcontext, sc_pc);
222         OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
223         OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
224         OFFSET(SC_HI1, sigcontext, sc_hi1);
225         OFFSET(SC_LO1, sigcontext, sc_lo1);
226         OFFSET(SC_HI2, sigcontext, sc_hi2);
227         OFFSET(SC_LO2, sigcontext, sc_lo2);
228         OFFSET(SC_HI3, sigcontext, sc_hi3);
229         OFFSET(SC_LO3, sigcontext, sc_lo3);
230         BLANK();
231 }
232 #endif
233 
234 #ifdef CONFIG_64BIT
235 void output_sc_defines(void)
236 {
237         COMMENT("Linux sigcontext offsets.");
238         OFFSET(SC_REGS, sigcontext, sc_regs);
239         OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
240         OFFSET(SC_MDHI, sigcontext, sc_mdhi);
241         OFFSET(SC_MDLO, sigcontext, sc_mdlo);
242         OFFSET(SC_PC, sigcontext, sc_pc);
243         OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
244         BLANK();
245 }
246 #endif
247 
248 #ifdef CONFIG_MIPS32_COMPAT
249 void output_sc32_defines(void)
250 {
251         COMMENT("Linux 32-bit sigcontext offsets.");
252         OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
253         OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
254         OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
255         BLANK();
256 }
257 #endif
258 
259 void output_signal_defined(void)
260 {
261         COMMENT("Linux signal numbers.");
262         DEFINE(_SIGHUP, SIGHUP);
263         DEFINE(_SIGINT, SIGINT);
264         DEFINE(_SIGQUIT, SIGQUIT);
265         DEFINE(_SIGILL, SIGILL);
266         DEFINE(_SIGTRAP, SIGTRAP);
267         DEFINE(_SIGIOT, SIGIOT);
268         DEFINE(_SIGABRT, SIGABRT);
269         DEFINE(_SIGEMT, SIGEMT);
270         DEFINE(_SIGFPE, SIGFPE);
271         DEFINE(_SIGKILL, SIGKILL);
272         DEFINE(_SIGBUS, SIGBUS);
273         DEFINE(_SIGSEGV, SIGSEGV);
274         DEFINE(_SIGSYS, SIGSYS);
275         DEFINE(_SIGPIPE, SIGPIPE);
276         DEFINE(_SIGALRM, SIGALRM);
277         DEFINE(_SIGTERM, SIGTERM);
278         DEFINE(_SIGUSR1, SIGUSR1);
279         DEFINE(_SIGUSR2, SIGUSR2);
280         DEFINE(_SIGCHLD, SIGCHLD);
281         DEFINE(_SIGPWR, SIGPWR);
282         DEFINE(_SIGWINCH, SIGWINCH);
283         DEFINE(_SIGURG, SIGURG);
284         DEFINE(_SIGIO, SIGIO);
285         DEFINE(_SIGSTOP, SIGSTOP);
286         DEFINE(_SIGTSTP, SIGTSTP);
287         DEFINE(_SIGCONT, SIGCONT);
288         DEFINE(_SIGTTIN, SIGTTIN);
289         DEFINE(_SIGTTOU, SIGTTOU);
290         DEFINE(_SIGVTALRM, SIGVTALRM);
291         DEFINE(_SIGPROF, SIGPROF);
292         DEFINE(_SIGXCPU, SIGXCPU);
293         DEFINE(_SIGXFSZ, SIGXFSZ);
294         BLANK();
295 }
296 
297 #ifdef CONFIG_CPU_CAVIUM_OCTEON
298 void output_octeon_cop2_state_defines(void)
299 {
300         COMMENT("Octeon specific octeon_cop2_state offsets.");
301         OFFSET(OCTEON_CP2_CRC_IV,       octeon_cop2_state, cop2_crc_iv);
302         OFFSET(OCTEON_CP2_CRC_LENGTH,   octeon_cop2_state, cop2_crc_length);
303         OFFSET(OCTEON_CP2_CRC_POLY,     octeon_cop2_state, cop2_crc_poly);
304         OFFSET(OCTEON_CP2_LLM_DAT,      octeon_cop2_state, cop2_llm_dat);
305         OFFSET(OCTEON_CP2_3DES_IV,      octeon_cop2_state, cop2_3des_iv);
306         OFFSET(OCTEON_CP2_3DES_KEY,     octeon_cop2_state, cop2_3des_key);
307         OFFSET(OCTEON_CP2_3DES_RESULT,  octeon_cop2_state, cop2_3des_result);
308         OFFSET(OCTEON_CP2_AES_INP0,     octeon_cop2_state, cop2_aes_inp0);
309         OFFSET(OCTEON_CP2_AES_IV,       octeon_cop2_state, cop2_aes_iv);
310         OFFSET(OCTEON_CP2_AES_KEY,      octeon_cop2_state, cop2_aes_key);
311         OFFSET(OCTEON_CP2_AES_KEYLEN,   octeon_cop2_state, cop2_aes_keylen);
312         OFFSET(OCTEON_CP2_AES_RESULT,   octeon_cop2_state, cop2_aes_result);
313         OFFSET(OCTEON_CP2_GFM_MULT,     octeon_cop2_state, cop2_gfm_mult);
314         OFFSET(OCTEON_CP2_GFM_POLY,     octeon_cop2_state, cop2_gfm_poly);
315         OFFSET(OCTEON_CP2_GFM_RESULT,   octeon_cop2_state, cop2_gfm_result);
316         OFFSET(OCTEON_CP2_HSH_DATW,     octeon_cop2_state, cop2_hsh_datw);
317         OFFSET(OCTEON_CP2_HSH_IVW,      octeon_cop2_state, cop2_hsh_ivw);
318         OFFSET(OCTEON_CP2_SHA3,         octeon_cop2_state, cop2_sha3);
319         OFFSET(THREAD_CP2,      task_struct, thread.cp2);
320         OFFSET(THREAD_CVMSEG,   task_struct, thread.cvmseg.cvmseg);
321         BLANK();
322 }
323 #endif
324 
325 #ifdef CONFIG_HIBERNATION
326 void output_pbe_defines(void)
327 {
328         COMMENT(" Linux struct pbe offsets. ");
329         OFFSET(PBE_ADDRESS, pbe, address);
330         OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
331         OFFSET(PBE_NEXT, pbe, next);
332         DEFINE(PBE_SIZE, sizeof(struct pbe));
333         BLANK();
334 }
335 #endif
336 
337 #ifdef CONFIG_CPU_PM
338 void output_pm_defines(void)
339 {
340         COMMENT(" PM offsets. ");
341 #ifdef CONFIG_EVA
342         OFFSET(SSS_SEGCTL0,     mips_static_suspend_state, segctl[0]);
343         OFFSET(SSS_SEGCTL1,     mips_static_suspend_state, segctl[1]);
344         OFFSET(SSS_SEGCTL2,     mips_static_suspend_state, segctl[2]);
345 #endif
346         OFFSET(SSS_SP,          mips_static_suspend_state, sp);
347         BLANK();
348 }
349 #endif
350 
351 void output_kvm_defines(void)
352 {
353         COMMENT(" KVM/MIPS Specfic offsets. ");
354         DEFINE(VCPU_ARCH_SIZE, sizeof(struct kvm_vcpu_arch));
355         OFFSET(VCPU_RUN, kvm_vcpu, run);
356         OFFSET(VCPU_HOST_ARCH, kvm_vcpu, arch);
357 
358         OFFSET(VCPU_HOST_EBASE, kvm_vcpu_arch, host_ebase);
359         OFFSET(VCPU_GUEST_EBASE, kvm_vcpu_arch, guest_ebase);
360 
361         OFFSET(VCPU_HOST_STACK, kvm_vcpu_arch, host_stack);
362         OFFSET(VCPU_HOST_GP, kvm_vcpu_arch, host_gp);
363 
364         OFFSET(VCPU_HOST_CP0_BADVADDR, kvm_vcpu_arch, host_cp0_badvaddr);
365         OFFSET(VCPU_HOST_CP0_CAUSE, kvm_vcpu_arch, host_cp0_cause);
366         OFFSET(VCPU_HOST_EPC, kvm_vcpu_arch, host_cp0_epc);
367         OFFSET(VCPU_HOST_ENTRYHI, kvm_vcpu_arch, host_cp0_entryhi);
368 
369         OFFSET(VCPU_GUEST_INST, kvm_vcpu_arch, guest_inst);
370 
371         OFFSET(VCPU_R0, kvm_vcpu_arch, gprs[0]);
372         OFFSET(VCPU_R1, kvm_vcpu_arch, gprs[1]);
373         OFFSET(VCPU_R2, kvm_vcpu_arch, gprs[2]);
374         OFFSET(VCPU_R3, kvm_vcpu_arch, gprs[3]);
375         OFFSET(VCPU_R4, kvm_vcpu_arch, gprs[4]);
376         OFFSET(VCPU_R5, kvm_vcpu_arch, gprs[5]);
377         OFFSET(VCPU_R6, kvm_vcpu_arch, gprs[6]);
378         OFFSET(VCPU_R7, kvm_vcpu_arch, gprs[7]);
379         OFFSET(VCPU_R8, kvm_vcpu_arch, gprs[8]);
380         OFFSET(VCPU_R9, kvm_vcpu_arch, gprs[9]);
381         OFFSET(VCPU_R10, kvm_vcpu_arch, gprs[10]);
382         OFFSET(VCPU_R11, kvm_vcpu_arch, gprs[11]);
383         OFFSET(VCPU_R12, kvm_vcpu_arch, gprs[12]);
384         OFFSET(VCPU_R13, kvm_vcpu_arch, gprs[13]);
385         OFFSET(VCPU_R14, kvm_vcpu_arch, gprs[14]);
386         OFFSET(VCPU_R15, kvm_vcpu_arch, gprs[15]);
387         OFFSET(VCPU_R16, kvm_vcpu_arch, gprs[16]);
388         OFFSET(VCPU_R17, kvm_vcpu_arch, gprs[17]);
389         OFFSET(VCPU_R18, kvm_vcpu_arch, gprs[18]);
390         OFFSET(VCPU_R19, kvm_vcpu_arch, gprs[19]);
391         OFFSET(VCPU_R20, kvm_vcpu_arch, gprs[20]);
392         OFFSET(VCPU_R21, kvm_vcpu_arch, gprs[21]);
393         OFFSET(VCPU_R22, kvm_vcpu_arch, gprs[22]);
394         OFFSET(VCPU_R23, kvm_vcpu_arch, gprs[23]);
395         OFFSET(VCPU_R24, kvm_vcpu_arch, gprs[24]);
396         OFFSET(VCPU_R25, kvm_vcpu_arch, gprs[25]);
397         OFFSET(VCPU_R26, kvm_vcpu_arch, gprs[26]);
398         OFFSET(VCPU_R27, kvm_vcpu_arch, gprs[27]);
399         OFFSET(VCPU_R28, kvm_vcpu_arch, gprs[28]);
400         OFFSET(VCPU_R29, kvm_vcpu_arch, gprs[29]);
401         OFFSET(VCPU_R30, kvm_vcpu_arch, gprs[30]);
402         OFFSET(VCPU_R31, kvm_vcpu_arch, gprs[31]);
403         OFFSET(VCPU_LO, kvm_vcpu_arch, lo);
404         OFFSET(VCPU_HI, kvm_vcpu_arch, hi);
405         OFFSET(VCPU_PC, kvm_vcpu_arch, pc);
406         BLANK();
407 
408         OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]);
409         OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]);
410         OFFSET(VCPU_FPR2, kvm_vcpu_arch, fpu.fpr[2]);
411         OFFSET(VCPU_FPR3, kvm_vcpu_arch, fpu.fpr[3]);
412         OFFSET(VCPU_FPR4, kvm_vcpu_arch, fpu.fpr[4]);
413         OFFSET(VCPU_FPR5, kvm_vcpu_arch, fpu.fpr[5]);
414         OFFSET(VCPU_FPR6, kvm_vcpu_arch, fpu.fpr[6]);
415         OFFSET(VCPU_FPR7, kvm_vcpu_arch, fpu.fpr[7]);
416         OFFSET(VCPU_FPR8, kvm_vcpu_arch, fpu.fpr[8]);
417         OFFSET(VCPU_FPR9, kvm_vcpu_arch, fpu.fpr[9]);
418         OFFSET(VCPU_FPR10, kvm_vcpu_arch, fpu.fpr[10]);
419         OFFSET(VCPU_FPR11, kvm_vcpu_arch, fpu.fpr[11]);
420         OFFSET(VCPU_FPR12, kvm_vcpu_arch, fpu.fpr[12]);
421         OFFSET(VCPU_FPR13, kvm_vcpu_arch, fpu.fpr[13]);
422         OFFSET(VCPU_FPR14, kvm_vcpu_arch, fpu.fpr[14]);
423         OFFSET(VCPU_FPR15, kvm_vcpu_arch, fpu.fpr[15]);
424         OFFSET(VCPU_FPR16, kvm_vcpu_arch, fpu.fpr[16]);
425         OFFSET(VCPU_FPR17, kvm_vcpu_arch, fpu.fpr[17]);
426         OFFSET(VCPU_FPR18, kvm_vcpu_arch, fpu.fpr[18]);
427         OFFSET(VCPU_FPR19, kvm_vcpu_arch, fpu.fpr[19]);
428         OFFSET(VCPU_FPR20, kvm_vcpu_arch, fpu.fpr[20]);
429         OFFSET(VCPU_FPR21, kvm_vcpu_arch, fpu.fpr[21]);
430         OFFSET(VCPU_FPR22, kvm_vcpu_arch, fpu.fpr[22]);
431         OFFSET(VCPU_FPR23, kvm_vcpu_arch, fpu.fpr[23]);
432         OFFSET(VCPU_FPR24, kvm_vcpu_arch, fpu.fpr[24]);
433         OFFSET(VCPU_FPR25, kvm_vcpu_arch, fpu.fpr[25]);
434         OFFSET(VCPU_FPR26, kvm_vcpu_arch, fpu.fpr[26]);
435         OFFSET(VCPU_FPR27, kvm_vcpu_arch, fpu.fpr[27]);
436         OFFSET(VCPU_FPR28, kvm_vcpu_arch, fpu.fpr[28]);
437         OFFSET(VCPU_FPR29, kvm_vcpu_arch, fpu.fpr[29]);
438         OFFSET(VCPU_FPR30, kvm_vcpu_arch, fpu.fpr[30]);
439         OFFSET(VCPU_FPR31, kvm_vcpu_arch, fpu.fpr[31]);
440 
441         OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31);
442         OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr);
443         BLANK();
444 
445         OFFSET(VCPU_COP0, kvm_vcpu_arch, cop0);
446         OFFSET(VCPU_GUEST_KERNEL_ASID, kvm_vcpu_arch, guest_kernel_asid);
447         OFFSET(VCPU_GUEST_USER_ASID, kvm_vcpu_arch, guest_user_asid);
448 
449         OFFSET(COP0_TLB_HI, mips_coproc, reg[MIPS_CP0_TLB_HI][0]);
450         OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
451         BLANK();
452 }
453 
454 #ifdef CONFIG_MIPS_CPS
455 void output_cps_defines(void)
456 {
457         COMMENT(" MIPS CPS offsets. ");
458 
459         OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
460         OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
461         DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
462 
463         OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
464         OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
465         OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
466         DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
467 }
468 #endif
469 

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