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Linux/arch/mips/kernel/cevt-sb1250.c

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  1 /*
  2  * Copyright (C) 2000, 2001 Broadcom Corporation
  3  *
  4  * This program is free software; you can redistribute it and/or
  5  * modify it under the terms of the GNU General Public License
  6  * as published by the Free Software Foundation; either version 2
  7  * of the License, or (at your option) any later version.
  8  *
  9  * This program is distributed in the hope that it will be useful,
 10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12  * GNU General Public License for more details.
 13  *
 14  * You should have received a copy of the GNU General Public License
 15  * along with this program; if not, write to the Free Software
 16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 17  */
 18 #include <linux/clockchips.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/irq.h>
 21 #include <linux/percpu.h>
 22 #include <linux/smp.h>
 23 
 24 #include <asm/addrspace.h>
 25 #include <asm/io.h>
 26 #include <asm/time.h>
 27 
 28 #include <asm/sibyte/sb1250.h>
 29 #include <asm/sibyte/sb1250_regs.h>
 30 #include <asm/sibyte/sb1250_int.h>
 31 #include <asm/sibyte/sb1250_scd.h>
 32 
 33 #define IMR_IP2_VAL     K_INT_MAP_I0
 34 #define IMR_IP3_VAL     K_INT_MAP_I1
 35 #define IMR_IP4_VAL     K_INT_MAP_I2
 36 
 37 /*
 38  * The general purpose timer ticks at 1MHz independent if
 39  * the rest of the system
 40  */
 41 static void sibyte_set_mode(enum clock_event_mode mode,
 42                            struct clock_event_device *evt)
 43 {
 44         unsigned int cpu = smp_processor_id();
 45         void __iomem *cfg, *init;
 46 
 47         cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
 48         init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
 49 
 50         switch (mode) {
 51         case CLOCK_EVT_MODE_PERIODIC:
 52                 __raw_writeq(0, cfg);
 53                 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
 54                 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
 55                              cfg);
 56                 break;
 57 
 58         case CLOCK_EVT_MODE_ONESHOT:
 59                 /* Stop the timer until we actually program a shot */
 60         case CLOCK_EVT_MODE_SHUTDOWN:
 61                 __raw_writeq(0, cfg);
 62                 break;
 63 
 64         case CLOCK_EVT_MODE_UNUSED:     /* shuddup gcc */
 65         case CLOCK_EVT_MODE_RESUME:
 66                 ;
 67         }
 68 }
 69 
 70 static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
 71 {
 72         unsigned int cpu = smp_processor_id();
 73         void __iomem *cfg, *init;
 74 
 75         cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
 76         init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
 77 
 78         __raw_writeq(0, cfg);
 79         __raw_writeq(delta - 1, init);
 80         __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
 81 
 82         return 0;
 83 }
 84 
 85 static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
 86 {
 87         unsigned int cpu = smp_processor_id();
 88         struct clock_event_device *cd = dev_id;
 89         void __iomem *cfg;
 90         unsigned long tmode;
 91 
 92         if (cd->mode == CLOCK_EVT_MODE_PERIODIC)
 93                 tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS;
 94         else
 95                 tmode = 0;
 96 
 97         /* ACK interrupt */
 98         cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
 99         ____raw_writeq(tmode, cfg);
100 
101         cd->event_handler(cd);
102 
103         return IRQ_HANDLED;
104 }
105 
106 static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
107 static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
108 static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
109 
110 void sb1250_clockevent_init(void)
111 {
112         unsigned int cpu = smp_processor_id();
113         unsigned int irq = K_INT_TIMER_0 + cpu;
114         struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
115         struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
116         unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
117 
118         /* Only have 4 general purpose timers, and we use last one as hpt */
119         BUG_ON(cpu > 2);
120 
121         sprintf(name, "sb1250-counter-%d", cpu);
122         cd->name                = name;
123         cd->features            = CLOCK_EVT_FEAT_PERIODIC |
124                                   CLOCK_EVT_FEAT_ONESHOT;
125         clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
126         cd->max_delta_ns        = clockevent_delta2ns(0x7fffff, cd);
127         cd->min_delta_ns        = clockevent_delta2ns(2, cd);
128         cd->rating              = 200;
129         cd->irq                 = irq;
130         cd->cpumask             = cpumask_of(cpu);
131         cd->set_next_event      = sibyte_next_event;
132         cd->set_mode            = sibyte_set_mode;
133         clockevents_register_device(cd);
134 
135         sb1250_mask_irq(cpu, irq);
136 
137         /*
138          * Map the timer interrupt to IP[4] of this cpu
139          */
140         __raw_writeq(IMR_IP4_VAL,
141                      IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
142                             (irq << 3)));
143 
144         sb1250_unmask_irq(cpu, irq);
145 
146         action->handler = sibyte_counter_handler;
147         action->flags   = IRQF_PERCPU | IRQF_TIMER;
148         action->name    = name;
149         action->dev_id  = cd;
150 
151         irq_set_affinity(irq, cpumask_of(cpu));
152         setup_irq(irq, action);
153 }
154 

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