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Linux/arch/mips/kernel/i8253.c

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  1 /*
  2  * i8253.c  8253/PIT functions
  3  *
  4  */
  5 #include <linux/clockchips.h>
  6 #include <linux/init.h>
  7 #include <linux/interrupt.h>
  8 #include <linux/jiffies.h>
  9 #include <linux/module.h>
 10 #include <linux/smp.h>
 11 #include <linux/spinlock.h>
 12 
 13 #include <asm/delay.h>
 14 #include <asm/i8253.h>
 15 #include <asm/io.h>
 16 #include <asm/time.h>
 17 
 18 DEFINE_SPINLOCK(i8253_lock);
 19 EXPORT_SYMBOL(i8253_lock);
 20 
 21 /*
 22  * Initialize the PIT timer.
 23  *
 24  * This is also called after resume to bring the PIT into operation again.
 25  */
 26 static void init_pit_timer(enum clock_event_mode mode,
 27                            struct clock_event_device *evt)
 28 {
 29         spin_lock(&i8253_lock);
 30 
 31         switch(mode) {
 32         case CLOCK_EVT_MODE_PERIODIC:
 33                 /* binary, mode 2, LSB/MSB, ch 0 */
 34                 outb_p(0x34, PIT_MODE);
 35                 outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
 36                 outb(LATCH >> 8 , PIT_CH0);     /* MSB */
 37                 break;
 38 
 39         case CLOCK_EVT_MODE_SHUTDOWN:
 40         case CLOCK_EVT_MODE_UNUSED:
 41                 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
 42                     evt->mode == CLOCK_EVT_MODE_ONESHOT) {
 43                         outb_p(0x30, PIT_MODE);
 44                         outb_p(0, PIT_CH0);
 45                         outb_p(0, PIT_CH0);
 46                 }
 47                 break;
 48 
 49         case CLOCK_EVT_MODE_ONESHOT:
 50                 /* One shot setup */
 51                 outb_p(0x38, PIT_MODE);
 52                 break;
 53 
 54         case CLOCK_EVT_MODE_RESUME:
 55                 /* Nothing to do here */
 56                 break;
 57         }
 58         spin_unlock(&i8253_lock);
 59 }
 60 
 61 /*
 62  * Program the next event in oneshot mode
 63  *
 64  * Delta is given in PIT ticks
 65  */
 66 static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
 67 {
 68         spin_lock(&i8253_lock);
 69         outb_p(delta & 0xff , PIT_CH0); /* LSB */
 70         outb(delta >> 8 , PIT_CH0);     /* MSB */
 71         spin_unlock(&i8253_lock);
 72 
 73         return 0;
 74 }
 75 
 76 /*
 77  * On UP the PIT can serve all of the possible timer functions. On SMP systems
 78  * it can be solely used for the global tick.
 79  *
 80  * The profiling and update capabilites are switched off once the local apic is
 81  * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
 82  * !using_apic_timer decisions in do_timer_interrupt_hook()
 83  */
 84 static struct clock_event_device pit_clockevent = {
 85         .name           = "pit",
 86         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 87         .set_mode       = init_pit_timer,
 88         .set_next_event = pit_next_event,
 89         .irq            = 0,
 90 };
 91 
 92 static irqreturn_t timer_interrupt(int irq, void *dev_id)
 93 {
 94         pit_clockevent.event_handler(&pit_clockevent);
 95 
 96         return IRQ_HANDLED;
 97 }
 98 
 99 static struct irqaction irq0  = {
100         .handler = timer_interrupt,
101         .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
102         .name = "timer"
103 };
104 
105 /*
106  * Initialize the conversion factor and the min/max deltas of the clock event
107  * structure and register the clock event source with the framework.
108  */
109 void __init setup_pit_timer(void)
110 {
111         struct clock_event_device *cd = &pit_clockevent;
112         unsigned int cpu = smp_processor_id();
113 
114         /*
115          * Start pit with the boot cpu mask and make it global after the
116          * IO_APIC has been initialized.
117          */
118         cd->cpumask = cpumask_of(cpu);
119         clockevent_set_clock(cd, CLOCK_TICK_RATE);
120         cd->max_delta_ns = clockevent_delta2ns(0x7FFF, cd);
121         cd->min_delta_ns = clockevent_delta2ns(0xF, cd);
122         clockevents_register_device(cd);
123 
124         setup_irq(0, &irq0);
125 }
126 
127 /*
128  * Since the PIT overflows every tick, its not very useful
129  * to just read by itself. So use jiffies to emulate a free
130  * running counter:
131  */
132 static cycle_t pit_read(struct clocksource *cs)
133 {
134         unsigned long flags;
135         int count;
136         u32 jifs;
137         static int old_count;
138         static u32 old_jifs;
139 
140         spin_lock_irqsave(&i8253_lock, flags);
141         /*
142          * Although our caller may have the read side of xtime_lock,
143          * this is now a seqlock, and we are cheating in this routine
144          * by having side effects on state that we cannot undo if
145          * there is a collision on the seqlock and our caller has to
146          * retry.  (Namely, old_jifs and old_count.)  So we must treat
147          * jiffies as volatile despite the lock.  We read jiffies
148          * before latching the timer count to guarantee that although
149          * the jiffies value might be older than the count (that is,
150          * the counter may underflow between the last point where
151          * jiffies was incremented and the point where we latch the
152          * count), it cannot be newer.
153          */
154         jifs = jiffies;
155         outb_p(0x00, PIT_MODE); /* latch the count ASAP */
156         count = inb_p(PIT_CH0); /* read the latched count */
157         count |= inb_p(PIT_CH0) << 8;
158 
159         /* VIA686a test code... reset the latch if count > max + 1 */
160         if (count > LATCH) {
161                 outb_p(0x34, PIT_MODE);
162                 outb_p(LATCH & 0xff, PIT_CH0);
163                 outb(LATCH >> 8, PIT_CH0);
164                 count = LATCH - 1;
165         }
166 
167         /*
168          * It's possible for count to appear to go the wrong way for a
169          * couple of reasons:
170          *
171          *  1. The timer counter underflows, but we haven't handled the
172          *     resulting interrupt and incremented jiffies yet.
173          *  2. Hardware problem with the timer, not giving us continuous time,
174          *     the counter does small "jumps" upwards on some Pentium systems,
175          *     (see c't 95/10 page 335 for Neptun bug.)
176          *
177          * Previous attempts to handle these cases intelligently were
178          * buggy, so we just do the simple thing now.
179          */
180         if (count > old_count && jifs == old_jifs) {
181                 count = old_count;
182         }
183         old_count = count;
184         old_jifs = jifs;
185 
186         spin_unlock_irqrestore(&i8253_lock, flags);
187 
188         count = (LATCH - 1) - count;
189 
190         return (cycle_t)(jifs * LATCH) + count;
191 }
192 
193 static struct clocksource clocksource_pit = {
194         .name   = "pit",
195         .rating = 110,
196         .read   = pit_read,
197         .mask   = CLOCKSOURCE_MASK(32),
198         .mult   = 0,
199         .shift  = 20,
200 };
201 
202 static int __init init_pit_clocksource(void)
203 {
204         if (num_possible_cpus() > 1) /* PIT does not scale! */
205                 return 0;
206 
207         clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
208         return clocksource_register(&clocksource_pit);
209 }
210 arch_initcall(init_pit_clocksource);
211 

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