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Linux/arch/mips/kernel/mips-r2-to-r6-emul.c

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Copyright (c) 2014 Imagination Technologies Ltd.
  7  * Author: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
  8  * Author: Markos Chandras <markos.chandras@imgtec.com>
  9  *
 10  *      MIPS R2 user space instruction emulator for MIPS R6
 11  *
 12  */
 13 #include <linux/bug.h>
 14 #include <linux/compiler.h>
 15 #include <linux/debugfs.h>
 16 #include <linux/init.h>
 17 #include <linux/kernel.h>
 18 #include <linux/ptrace.h>
 19 #include <linux/seq_file.h>
 20 
 21 #include <asm/asm.h>
 22 #include <asm/branch.h>
 23 #include <asm/break.h>
 24 #include <asm/debug.h>
 25 #include <asm/fpu.h>
 26 #include <asm/fpu_emulator.h>
 27 #include <asm/inst.h>
 28 #include <asm/mips-r2-to-r6-emul.h>
 29 #include <asm/local.h>
 30 #include <asm/mipsregs.h>
 31 #include <asm/ptrace.h>
 32 #include <linux/uaccess.h>
 33 
 34 #ifdef CONFIG_64BIT
 35 #define ADDIU   "daddiu "
 36 #define INS     "dins "
 37 #define EXT     "dext "
 38 #else
 39 #define ADDIU   "addiu "
 40 #define INS     "ins "
 41 #define EXT     "ext "
 42 #endif /* CONFIG_64BIT */
 43 
 44 #define SB      "sb "
 45 #define LB      "lb "
 46 #define LL      "ll "
 47 #define SC      "sc "
 48 
 49 #ifdef CONFIG_DEBUG_FS
 50 static DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2emustats);
 51 static DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2bdemustats);
 52 static DEFINE_PER_CPU(struct mips_r2br_emulator_stats, mipsr2bremustats);
 53 #endif
 54 
 55 extern const unsigned int fpucondbit[8];
 56 
 57 #define MIPS_R2_EMUL_TOTAL_PASS 10
 58 
 59 int mipsr2_emulation = 0;
 60 
 61 static int __init mipsr2emu_enable(char *s)
 62 {
 63         mipsr2_emulation = 1;
 64 
 65         pr_info("MIPS R2-to-R6 Emulator Enabled!");
 66 
 67         return 1;
 68 }
 69 __setup("mipsr2emu", mipsr2emu_enable);
 70 
 71 /**
 72  * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
 73  * for performance instead of the traditional way of using a stack trampoline
 74  * which is rather slow.
 75  * @regs: Process register set
 76  * @ir: Instruction
 77  */
 78 static inline int mipsr6_emul(struct pt_regs *regs, u32 ir)
 79 {
 80         switch (MIPSInst_OPCODE(ir)) {
 81         case addiu_op:
 82                 if (MIPSInst_RT(ir))
 83                         regs->regs[MIPSInst_RT(ir)] =
 84                                 (s32)regs->regs[MIPSInst_RS(ir)] +
 85                                 (s32)MIPSInst_SIMM(ir);
 86                 return 0;
 87         case daddiu_op:
 88                 if (IS_ENABLED(CONFIG_32BIT))
 89                         break;
 90 
 91                 if (MIPSInst_RT(ir))
 92                         regs->regs[MIPSInst_RT(ir)] =
 93                                 (s64)regs->regs[MIPSInst_RS(ir)] +
 94                                 (s64)MIPSInst_SIMM(ir);
 95                 return 0;
 96         case lwc1_op:
 97         case swc1_op:
 98         case cop1_op:
 99         case cop1x_op:
100                 /* FPU instructions in delay slot */
101                 return -SIGFPE;
102         case spec_op:
103                 switch (MIPSInst_FUNC(ir)) {
104                 case or_op:
105                         if (MIPSInst_RD(ir))
106                                 regs->regs[MIPSInst_RD(ir)] =
107                                         regs->regs[MIPSInst_RS(ir)] |
108                                         regs->regs[MIPSInst_RT(ir)];
109                         return 0;
110                 case sll_op:
111                         if (MIPSInst_RS(ir))
112                                 break;
113 
114                         if (MIPSInst_RD(ir))
115                                 regs->regs[MIPSInst_RD(ir)] =
116                                         (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) <<
117                                                 MIPSInst_FD(ir));
118                         return 0;
119                 case srl_op:
120                         if (MIPSInst_RS(ir))
121                                 break;
122 
123                         if (MIPSInst_RD(ir))
124                                 regs->regs[MIPSInst_RD(ir)] =
125                                         (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >>
126                                                 MIPSInst_FD(ir));
127                         return 0;
128                 case addu_op:
129                         if (MIPSInst_FD(ir))
130                                 break;
131 
132                         if (MIPSInst_RD(ir))
133                                 regs->regs[MIPSInst_RD(ir)] =
134                                         (s32)((u32)regs->regs[MIPSInst_RS(ir)] +
135                                               (u32)regs->regs[MIPSInst_RT(ir)]);
136                         return 0;
137                 case subu_op:
138                         if (MIPSInst_FD(ir))
139                                 break;
140 
141                         if (MIPSInst_RD(ir))
142                                 regs->regs[MIPSInst_RD(ir)] =
143                                         (s32)((u32)regs->regs[MIPSInst_RS(ir)] -
144                                               (u32)regs->regs[MIPSInst_RT(ir)]);
145                         return 0;
146                 case dsll_op:
147                         if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_RS(ir))
148                                 break;
149 
150                         if (MIPSInst_RD(ir))
151                                 regs->regs[MIPSInst_RD(ir)] =
152                                         (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) <<
153                                                 MIPSInst_FD(ir));
154                         return 0;
155                 case dsrl_op:
156                         if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_RS(ir))
157                                 break;
158 
159                         if (MIPSInst_RD(ir))
160                                 regs->regs[MIPSInst_RD(ir)] =
161                                         (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >>
162                                                 MIPSInst_FD(ir));
163                         return 0;
164                 case daddu_op:
165                         if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_FD(ir))
166                                 break;
167 
168                         if (MIPSInst_RD(ir))
169                                 regs->regs[MIPSInst_RD(ir)] =
170                                         (u64)regs->regs[MIPSInst_RS(ir)] +
171                                         (u64)regs->regs[MIPSInst_RT(ir)];
172                         return 0;
173                 case dsubu_op:
174                         if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_FD(ir))
175                                 break;
176 
177                         if (MIPSInst_RD(ir))
178                                 regs->regs[MIPSInst_RD(ir)] =
179                                         (s64)((u64)regs->regs[MIPSInst_RS(ir)] -
180                                               (u64)regs->regs[MIPSInst_RT(ir)]);
181                         return 0;
182                 }
183                 break;
184         default:
185                 pr_debug("No fastpath BD emulation for instruction 0x%08x (op: %02x)\n",
186                          ir, MIPSInst_OPCODE(ir));
187         }
188 
189         return SIGILL;
190 }
191 
192 /**
193  * movf_func - Emulate a MOVF instruction
194  * @regs: Process register set
195  * @ir: Instruction
196  *
197  * Returns 0 since it always succeeds.
198  */
199 static int movf_func(struct pt_regs *regs, u32 ir)
200 {
201         u32 csr;
202         u32 cond;
203 
204         csr = current->thread.fpu.fcr31;
205         cond = fpucondbit[MIPSInst_RT(ir) >> 2];
206 
207         if (((csr & cond) == 0) && MIPSInst_RD(ir))
208                 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
209 
210         MIPS_R2_STATS(movs);
211 
212         return 0;
213 }
214 
215 /**
216  * movt_func - Emulate a MOVT instruction
217  * @regs: Process register set
218  * @ir: Instruction
219  *
220  * Returns 0 since it always succeeds.
221  */
222 static int movt_func(struct pt_regs *regs, u32 ir)
223 {
224         u32 csr;
225         u32 cond;
226 
227         csr = current->thread.fpu.fcr31;
228         cond = fpucondbit[MIPSInst_RT(ir) >> 2];
229 
230         if (((csr & cond) != 0) && MIPSInst_RD(ir))
231                 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
232 
233         MIPS_R2_STATS(movs);
234 
235         return 0;
236 }
237 
238 /**
239  * jr_func - Emulate a JR instruction.
240  * @pt_regs: Process register set
241  * @ir: Instruction
242  *
243  * Returns SIGILL if JR was in delay slot, SIGEMT if we
244  * can't compute the EPC, SIGSEGV if we can't access the
245  * userland instruction or 0 on success.
246  */
247 static int jr_func(struct pt_regs *regs, u32 ir)
248 {
249         int err;
250         unsigned long cepc, epc, nepc;
251         u32 nir;
252 
253         if (delay_slot(regs))
254                 return SIGILL;
255 
256         /* EPC after the RI/JR instruction */
257         nepc = regs->cp0_epc;
258         /* Roll back to the reserved R2 JR instruction */
259         regs->cp0_epc -= 4;
260         epc = regs->cp0_epc;
261         err = __compute_return_epc(regs);
262 
263         if (err < 0)
264                 return SIGEMT;
265 
266 
267         /* Computed EPC */
268         cepc = regs->cp0_epc;
269 
270         /* Get DS instruction */
271         err = __get_user(nir, (u32 __user *)nepc);
272         if (err)
273                 return SIGSEGV;
274 
275         MIPS_R2BR_STATS(jrs);
276 
277         /* If nir == 0(NOP), then nothing else to do */
278         if (nir) {
279                 /*
280                  * Negative err means FPU instruction in BD-slot,
281                  * Zero err means 'BD-slot emulation done'
282                  * For anything else we go back to trampoline emulation.
283                  */
284                 err = mipsr6_emul(regs, nir);
285                 if (err > 0) {
286                         regs->cp0_epc = nepc;
287                         err = mips_dsemul(regs, nir, epc, cepc);
288                         if (err == SIGILL)
289                                 err = SIGEMT;
290                         MIPS_R2_STATS(dsemul);
291                 }
292         }
293 
294         return err;
295 }
296 
297 /**
298  * movz_func - Emulate a MOVZ instruction
299  * @regs: Process register set
300  * @ir: Instruction
301  *
302  * Returns 0 since it always succeeds.
303  */
304 static int movz_func(struct pt_regs *regs, u32 ir)
305 {
306         if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir))
307                 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
308         MIPS_R2_STATS(movs);
309 
310         return 0;
311 }
312 
313 /**
314  * movn_func - Emulate a MOVZ instruction
315  * @regs: Process register set
316  * @ir: Instruction
317  *
318  * Returns 0 since it always succeeds.
319  */
320 static int movn_func(struct pt_regs *regs, u32 ir)
321 {
322         if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir))
323                 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
324         MIPS_R2_STATS(movs);
325 
326         return 0;
327 }
328 
329 /**
330  * mfhi_func - Emulate a MFHI instruction
331  * @regs: Process register set
332  * @ir: Instruction
333  *
334  * Returns 0 since it always succeeds.
335  */
336 static int mfhi_func(struct pt_regs *regs, u32 ir)
337 {
338         if (MIPSInst_RD(ir))
339                 regs->regs[MIPSInst_RD(ir)] = regs->hi;
340 
341         MIPS_R2_STATS(hilo);
342 
343         return 0;
344 }
345 
346 /**
347  * mthi_func - Emulate a MTHI instruction
348  * @regs: Process register set
349  * @ir: Instruction
350  *
351  * Returns 0 since it always succeeds.
352  */
353 static int mthi_func(struct pt_regs *regs, u32 ir)
354 {
355         regs->hi = regs->regs[MIPSInst_RS(ir)];
356 
357         MIPS_R2_STATS(hilo);
358 
359         return 0;
360 }
361 
362 /**
363  * mflo_func - Emulate a MFLO instruction
364  * @regs: Process register set
365  * @ir: Instruction
366  *
367  * Returns 0 since it always succeeds.
368  */
369 static int mflo_func(struct pt_regs *regs, u32 ir)
370 {
371         if (MIPSInst_RD(ir))
372                 regs->regs[MIPSInst_RD(ir)] = regs->lo;
373 
374         MIPS_R2_STATS(hilo);
375 
376         return 0;
377 }
378 
379 /**
380  * mtlo_func - Emulate a MTLO instruction
381  * @regs: Process register set
382  * @ir: Instruction
383  *
384  * Returns 0 since it always succeeds.
385  */
386 static int mtlo_func(struct pt_regs *regs, u32 ir)
387 {
388         regs->lo = regs->regs[MIPSInst_RS(ir)];
389 
390         MIPS_R2_STATS(hilo);
391 
392         return 0;
393 }
394 
395 /**
396  * mult_func - Emulate a MULT instruction
397  * @regs: Process register set
398  * @ir: Instruction
399  *
400  * Returns 0 since it always succeeds.
401  */
402 static int mult_func(struct pt_regs *regs, u32 ir)
403 {
404         s64 res;
405         s32 rt, rs;
406 
407         rt = regs->regs[MIPSInst_RT(ir)];
408         rs = regs->regs[MIPSInst_RS(ir)];
409         res = (s64)rt * (s64)rs;
410 
411         rs = res;
412         regs->lo = (s64)rs;
413         rt = res >> 32;
414         res = (s64)rt;
415         regs->hi = res;
416 
417         MIPS_R2_STATS(muls);
418 
419         return 0;
420 }
421 
422 /**
423  * multu_func - Emulate a MULTU instruction
424  * @regs: Process register set
425  * @ir: Instruction
426  *
427  * Returns 0 since it always succeeds.
428  */
429 static int multu_func(struct pt_regs *regs, u32 ir)
430 {
431         u64 res;
432         u32 rt, rs;
433 
434         rt = regs->regs[MIPSInst_RT(ir)];
435         rs = regs->regs[MIPSInst_RS(ir)];
436         res = (u64)rt * (u64)rs;
437         rt = res;
438         regs->lo = (s64)(s32)rt;
439         regs->hi = (s64)(s32)(res >> 32);
440 
441         MIPS_R2_STATS(muls);
442 
443         return 0;
444 }
445 
446 /**
447  * div_func - Emulate a DIV instruction
448  * @regs: Process register set
449  * @ir: Instruction
450  *
451  * Returns 0 since it always succeeds.
452  */
453 static int div_func(struct pt_regs *regs, u32 ir)
454 {
455         s32 rt, rs;
456 
457         rt = regs->regs[MIPSInst_RT(ir)];
458         rs = regs->regs[MIPSInst_RS(ir)];
459 
460         regs->lo = (s64)(rs / rt);
461         regs->hi = (s64)(rs % rt);
462 
463         MIPS_R2_STATS(divs);
464 
465         return 0;
466 }
467 
468 /**
469  * divu_func - Emulate a DIVU instruction
470  * @regs: Process register set
471  * @ir: Instruction
472  *
473  * Returns 0 since it always succeeds.
474  */
475 static int divu_func(struct pt_regs *regs, u32 ir)
476 {
477         u32 rt, rs;
478 
479         rt = regs->regs[MIPSInst_RT(ir)];
480         rs = regs->regs[MIPSInst_RS(ir)];
481 
482         regs->lo = (s64)(rs / rt);
483         regs->hi = (s64)(rs % rt);
484 
485         MIPS_R2_STATS(divs);
486 
487         return 0;
488 }
489 
490 /**
491  * dmult_func - Emulate a DMULT instruction
492  * @regs: Process register set
493  * @ir: Instruction
494  *
495  * Returns 0 on success or SIGILL for 32-bit kernels.
496  */
497 static int dmult_func(struct pt_regs *regs, u32 ir)
498 {
499         s64 res;
500         s64 rt, rs;
501 
502         if (IS_ENABLED(CONFIG_32BIT))
503                 return SIGILL;
504 
505         rt = regs->regs[MIPSInst_RT(ir)];
506         rs = regs->regs[MIPSInst_RS(ir)];
507         res = rt * rs;
508 
509         regs->lo = res;
510         __asm__ __volatile__(
511                 "dmuh %0, %1, %2\t\n"
512                 : "=r"(res)
513                 : "r"(rt), "r"(rs));
514 
515         regs->hi = res;
516 
517         MIPS_R2_STATS(muls);
518 
519         return 0;
520 }
521 
522 /**
523  * dmultu_func - Emulate a DMULTU instruction
524  * @regs: Process register set
525  * @ir: Instruction
526  *
527  * Returns 0 on success or SIGILL for 32-bit kernels.
528  */
529 static int dmultu_func(struct pt_regs *regs, u32 ir)
530 {
531         u64 res;
532         u64 rt, rs;
533 
534         if (IS_ENABLED(CONFIG_32BIT))
535                 return SIGILL;
536 
537         rt = regs->regs[MIPSInst_RT(ir)];
538         rs = regs->regs[MIPSInst_RS(ir)];
539         res = rt * rs;
540 
541         regs->lo = res;
542         __asm__ __volatile__(
543                 "dmuhu %0, %1, %2\t\n"
544                 : "=r"(res)
545                 : "r"(rt), "r"(rs));
546 
547         regs->hi = res;
548 
549         MIPS_R2_STATS(muls);
550 
551         return 0;
552 }
553 
554 /**
555  * ddiv_func - Emulate a DDIV instruction
556  * @regs: Process register set
557  * @ir: Instruction
558  *
559  * Returns 0 on success or SIGILL for 32-bit kernels.
560  */
561 static int ddiv_func(struct pt_regs *regs, u32 ir)
562 {
563         s64 rt, rs;
564 
565         if (IS_ENABLED(CONFIG_32BIT))
566                 return SIGILL;
567 
568         rt = regs->regs[MIPSInst_RT(ir)];
569         rs = regs->regs[MIPSInst_RS(ir)];
570 
571         regs->lo = rs / rt;
572         regs->hi = rs % rt;
573 
574         MIPS_R2_STATS(divs);
575 
576         return 0;
577 }
578 
579 /**
580  * ddivu_func - Emulate a DDIVU instruction
581  * @regs: Process register set
582  * @ir: Instruction
583  *
584  * Returns 0 on success or SIGILL for 32-bit kernels.
585  */
586 static int ddivu_func(struct pt_regs *regs, u32 ir)
587 {
588         u64 rt, rs;
589 
590         if (IS_ENABLED(CONFIG_32BIT))
591                 return SIGILL;
592 
593         rt = regs->regs[MIPSInst_RT(ir)];
594         rs = regs->regs[MIPSInst_RS(ir)];
595 
596         regs->lo = rs / rt;
597         regs->hi = rs % rt;
598 
599         MIPS_R2_STATS(divs);
600 
601         return 0;
602 }
603 
604 /* R6 removed instructions for the SPECIAL opcode */
605 static const struct r2_decoder_table spec_op_table[] = {
606         { 0xfc1ff83f, 0x00000008, jr_func },
607         { 0xfc00ffff, 0x00000018, mult_func },
608         { 0xfc00ffff, 0x00000019, multu_func },
609         { 0xfc00ffff, 0x0000001c, dmult_func },
610         { 0xfc00ffff, 0x0000001d, dmultu_func },
611         { 0xffff07ff, 0x00000010, mfhi_func },
612         { 0xfc1fffff, 0x00000011, mthi_func },
613         { 0xffff07ff, 0x00000012, mflo_func },
614         { 0xfc1fffff, 0x00000013, mtlo_func },
615         { 0xfc0307ff, 0x00000001, movf_func },
616         { 0xfc0307ff, 0x00010001, movt_func },
617         { 0xfc0007ff, 0x0000000a, movz_func },
618         { 0xfc0007ff, 0x0000000b, movn_func },
619         { 0xfc00ffff, 0x0000001a, div_func },
620         { 0xfc00ffff, 0x0000001b, divu_func },
621         { 0xfc00ffff, 0x0000001e, ddiv_func },
622         { 0xfc00ffff, 0x0000001f, ddivu_func },
623         {}
624 };
625 
626 /**
627  * madd_func - Emulate a MADD instruction
628  * @regs: Process register set
629  * @ir: Instruction
630  *
631  * Returns 0 since it always succeeds.
632  */
633 static int madd_func(struct pt_regs *regs, u32 ir)
634 {
635         s64 res;
636         s32 rt, rs;
637 
638         rt = regs->regs[MIPSInst_RT(ir)];
639         rs = regs->regs[MIPSInst_RS(ir)];
640         res = (s64)rt * (s64)rs;
641         rt = regs->hi;
642         rs = regs->lo;
643         res += ((((s64)rt) << 32) | (u32)rs);
644 
645         rt = res;
646         regs->lo = (s64)rt;
647         rs = res >> 32;
648         regs->hi = (s64)rs;
649 
650         MIPS_R2_STATS(dsps);
651 
652         return 0;
653 }
654 
655 /**
656  * maddu_func - Emulate a MADDU instruction
657  * @regs: Process register set
658  * @ir: Instruction
659  *
660  * Returns 0 since it always succeeds.
661  */
662 static int maddu_func(struct pt_regs *regs, u32 ir)
663 {
664         u64 res;
665         u32 rt, rs;
666 
667         rt = regs->regs[MIPSInst_RT(ir)];
668         rs = regs->regs[MIPSInst_RS(ir)];
669         res = (u64)rt * (u64)rs;
670         rt = regs->hi;
671         rs = regs->lo;
672         res += ((((s64)rt) << 32) | (u32)rs);
673 
674         rt = res;
675         regs->lo = (s64)(s32)rt;
676         rs = res >> 32;
677         regs->hi = (s64)(s32)rs;
678 
679         MIPS_R2_STATS(dsps);
680 
681         return 0;
682 }
683 
684 /**
685  * msub_func - Emulate a MSUB instruction
686  * @regs: Process register set
687  * @ir: Instruction
688  *
689  * Returns 0 since it always succeeds.
690  */
691 static int msub_func(struct pt_regs *regs, u32 ir)
692 {
693         s64 res;
694         s32 rt, rs;
695 
696         rt = regs->regs[MIPSInst_RT(ir)];
697         rs = regs->regs[MIPSInst_RS(ir)];
698         res = (s64)rt * (s64)rs;
699         rt = regs->hi;
700         rs = regs->lo;
701         res = ((((s64)rt) << 32) | (u32)rs) - res;
702 
703         rt = res;
704         regs->lo = (s64)rt;
705         rs = res >> 32;
706         regs->hi = (s64)rs;
707 
708         MIPS_R2_STATS(dsps);
709 
710         return 0;
711 }
712 
713 /**
714  * msubu_func - Emulate a MSUBU instruction
715  * @regs: Process register set
716  * @ir: Instruction
717  *
718  * Returns 0 since it always succeeds.
719  */
720 static int msubu_func(struct pt_regs *regs, u32 ir)
721 {
722         u64 res;
723         u32 rt, rs;
724 
725         rt = regs->regs[MIPSInst_RT(ir)];
726         rs = regs->regs[MIPSInst_RS(ir)];
727         res = (u64)rt * (u64)rs;
728         rt = regs->hi;
729         rs = regs->lo;
730         res = ((((s64)rt) << 32) | (u32)rs) - res;
731 
732         rt = res;
733         regs->lo = (s64)(s32)rt;
734         rs = res >> 32;
735         regs->hi = (s64)(s32)rs;
736 
737         MIPS_R2_STATS(dsps);
738 
739         return 0;
740 }
741 
742 /**
743  * mul_func - Emulate a MUL instruction
744  * @regs: Process register set
745  * @ir: Instruction
746  *
747  * Returns 0 since it always succeeds.
748  */
749 static int mul_func(struct pt_regs *regs, u32 ir)
750 {
751         s64 res;
752         s32 rt, rs;
753 
754         if (!MIPSInst_RD(ir))
755                 return 0;
756         rt = regs->regs[MIPSInst_RT(ir)];
757         rs = regs->regs[MIPSInst_RS(ir)];
758         res = (s64)rt * (s64)rs;
759 
760         rs = res;
761         regs->regs[MIPSInst_RD(ir)] = (s64)rs;
762 
763         MIPS_R2_STATS(muls);
764 
765         return 0;
766 }
767 
768 /**
769  * clz_func - Emulate a CLZ instruction
770  * @regs: Process register set
771  * @ir: Instruction
772  *
773  * Returns 0 since it always succeeds.
774  */
775 static int clz_func(struct pt_regs *regs, u32 ir)
776 {
777         u32 res;
778         u32 rs;
779 
780         if (!MIPSInst_RD(ir))
781                 return 0;
782 
783         rs = regs->regs[MIPSInst_RS(ir)];
784         __asm__ __volatile__("clz %0, %1" : "=r"(res) : "r"(rs));
785         regs->regs[MIPSInst_RD(ir)] = res;
786 
787         MIPS_R2_STATS(bops);
788 
789         return 0;
790 }
791 
792 /**
793  * clo_func - Emulate a CLO instruction
794  * @regs: Process register set
795  * @ir: Instruction
796  *
797  * Returns 0 since it always succeeds.
798  */
799 
800 static int clo_func(struct pt_regs *regs, u32 ir)
801 {
802         u32 res;
803         u32 rs;
804 
805         if (!MIPSInst_RD(ir))
806                 return 0;
807 
808         rs = regs->regs[MIPSInst_RS(ir)];
809         __asm__ __volatile__("clo %0, %1" : "=r"(res) : "r"(rs));
810         regs->regs[MIPSInst_RD(ir)] = res;
811 
812         MIPS_R2_STATS(bops);
813 
814         return 0;
815 }
816 
817 /**
818  * dclz_func - Emulate a DCLZ instruction
819  * @regs: Process register set
820  * @ir: Instruction
821  *
822  * Returns 0 since it always succeeds.
823  */
824 static int dclz_func(struct pt_regs *regs, u32 ir)
825 {
826         u64 res;
827         u64 rs;
828 
829         if (IS_ENABLED(CONFIG_32BIT))
830                 return SIGILL;
831 
832         if (!MIPSInst_RD(ir))
833                 return 0;
834 
835         rs = regs->regs[MIPSInst_RS(ir)];
836         __asm__ __volatile__("dclz %0, %1" : "=r"(res) : "r"(rs));
837         regs->regs[MIPSInst_RD(ir)] = res;
838 
839         MIPS_R2_STATS(bops);
840 
841         return 0;
842 }
843 
844 /**
845  * dclo_func - Emulate a DCLO instruction
846  * @regs: Process register set
847  * @ir: Instruction
848  *
849  * Returns 0 since it always succeeds.
850  */
851 static int dclo_func(struct pt_regs *regs, u32 ir)
852 {
853         u64 res;
854         u64 rs;
855 
856         if (IS_ENABLED(CONFIG_32BIT))
857                 return SIGILL;
858 
859         if (!MIPSInst_RD(ir))
860                 return 0;
861 
862         rs = regs->regs[MIPSInst_RS(ir)];
863         __asm__ __volatile__("dclo %0, %1" : "=r"(res) : "r"(rs));
864         regs->regs[MIPSInst_RD(ir)] = res;
865 
866         MIPS_R2_STATS(bops);
867 
868         return 0;
869 }
870 
871 /* R6 removed instructions for the SPECIAL2 opcode */
872 static const struct r2_decoder_table spec2_op_table[] = {
873         { 0xfc00ffff, 0x70000000, madd_func },
874         { 0xfc00ffff, 0x70000001, maddu_func },
875         { 0xfc0007ff, 0x70000002, mul_func },
876         { 0xfc00ffff, 0x70000004, msub_func },
877         { 0xfc00ffff, 0x70000005, msubu_func },
878         { 0xfc0007ff, 0x70000020, clz_func },
879         { 0xfc0007ff, 0x70000021, clo_func },
880         { 0xfc0007ff, 0x70000024, dclz_func },
881         { 0xfc0007ff, 0x70000025, dclo_func },
882         { }
883 };
884 
885 static inline int mipsr2_find_op_func(struct pt_regs *regs, u32 inst,
886                                       const struct r2_decoder_table *table)
887 {
888         const struct r2_decoder_table *p;
889         int err;
890 
891         for (p = table; p->func; p++) {
892                 if ((inst & p->mask) == p->code) {
893                         err = (p->func)(regs, inst);
894                         return err;
895                 }
896         }
897         return SIGILL;
898 }
899 
900 /**
901  * mipsr2_decoder: Decode and emulate a MIPS R2 instruction
902  * @regs: Process register set
903  * @inst: Instruction to decode and emulate
904  * @fcr31: Floating Point Control and Status Register Cause bits returned
905  */
906 int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
907 {
908         int err = 0;
909         unsigned long vaddr;
910         u32 nir;
911         unsigned long cpc, epc, nepc, r31, res, rs, rt;
912 
913         void __user *fault_addr = NULL;
914         int pass = 0;
915 
916 repeat:
917         r31 = regs->regs[31];
918         epc = regs->cp0_epc;
919         err = compute_return_epc(regs);
920         if (err < 0) {
921                 BUG();
922                 return SIGEMT;
923         }
924         pr_debug("Emulating the 0x%08x R2 instruction @ 0x%08lx (pass=%d))\n",
925                  inst, epc, pass);
926 
927         switch (MIPSInst_OPCODE(inst)) {
928         case spec_op:
929                 err = mipsr2_find_op_func(regs, inst, spec_op_table);
930                 if (err < 0) {
931                         /* FPU instruction under JR */
932                         regs->cp0_cause |= CAUSEF_BD;
933                         goto fpu_emul;
934                 }
935                 break;
936         case spec2_op:
937                 err = mipsr2_find_op_func(regs, inst, spec2_op_table);
938                 break;
939         case bcond_op:
940                 rt = MIPSInst_RT(inst);
941                 rs = MIPSInst_RS(inst);
942                 switch (rt) {
943                 case tgei_op:
944                         if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst))
945                                 do_trap_or_bp(regs, 0, 0, "TGEI");
946 
947                         MIPS_R2_STATS(traps);
948 
949                         break;
950                 case tgeiu_op:
951                         if (regs->regs[rs] >= MIPSInst_UIMM(inst))
952                                 do_trap_or_bp(regs, 0, 0, "TGEIU");
953 
954                         MIPS_R2_STATS(traps);
955 
956                         break;
957                 case tlti_op:
958                         if ((long)regs->regs[rs] < MIPSInst_SIMM(inst))
959                                 do_trap_or_bp(regs, 0, 0, "TLTI");
960 
961                         MIPS_R2_STATS(traps);
962 
963                         break;
964                 case tltiu_op:
965                         if (regs->regs[rs] < MIPSInst_UIMM(inst))
966                                 do_trap_or_bp(regs, 0, 0, "TLTIU");
967 
968                         MIPS_R2_STATS(traps);
969 
970                         break;
971                 case teqi_op:
972                         if (regs->regs[rs] == MIPSInst_SIMM(inst))
973                                 do_trap_or_bp(regs, 0, 0, "TEQI");
974 
975                         MIPS_R2_STATS(traps);
976 
977                         break;
978                 case tnei_op:
979                         if (regs->regs[rs] != MIPSInst_SIMM(inst))
980                                 do_trap_or_bp(regs, 0, 0, "TNEI");
981 
982                         MIPS_R2_STATS(traps);
983 
984                         break;
985                 case bltzl_op:
986                 case bgezl_op:
987                 case bltzall_op:
988                 case bgezall_op:
989                         if (delay_slot(regs)) {
990                                 err = SIGILL;
991                                 break;
992                         }
993                         regs->regs[31] = r31;
994                         regs->cp0_epc = epc;
995                         err = __compute_return_epc(regs);
996                         if (err < 0)
997                                 return SIGEMT;
998                         if (err != BRANCH_LIKELY_TAKEN)
999                                 break;
1000                         cpc = regs->cp0_epc;
1001                         nepc = epc + 4;
1002                         err = __get_user(nir, (u32 __user *)nepc);
1003                         if (err) {
1004                                 err = SIGSEGV;
1005                                 break;
1006                         }
1007                         /*
1008                          * This will probably be optimized away when
1009                          * CONFIG_DEBUG_FS is not enabled
1010                          */
1011                         switch (rt) {
1012                         case bltzl_op:
1013                                 MIPS_R2BR_STATS(bltzl);
1014                                 break;
1015                         case bgezl_op:
1016                                 MIPS_R2BR_STATS(bgezl);
1017                                 break;
1018                         case bltzall_op:
1019                                 MIPS_R2BR_STATS(bltzall);
1020                                 break;
1021                         case bgezall_op:
1022                                 MIPS_R2BR_STATS(bgezall);
1023                                 break;
1024                         }
1025 
1026                         switch (MIPSInst_OPCODE(nir)) {
1027                         case cop1_op:
1028                         case cop1x_op:
1029                         case lwc1_op:
1030                         case swc1_op:
1031                                 regs->cp0_cause |= CAUSEF_BD;
1032                                 goto fpu_emul;
1033                         }
1034                         if (nir) {
1035                                 err = mipsr6_emul(regs, nir);
1036                                 if (err > 0) {
1037                                         err = mips_dsemul(regs, nir, epc, cpc);
1038                                         if (err == SIGILL)
1039                                                 err = SIGEMT;
1040                                         MIPS_R2_STATS(dsemul);
1041                                 }
1042                         }
1043                         break;
1044                 case bltzal_op:
1045                 case bgezal_op:
1046                         if (delay_slot(regs)) {
1047                                 err = SIGILL;
1048                                 break;
1049                         }
1050                         regs->regs[31] = r31;
1051                         regs->cp0_epc = epc;
1052                         err = __compute_return_epc(regs);
1053                         if (err < 0)
1054                                 return SIGEMT;
1055                         cpc = regs->cp0_epc;
1056                         nepc = epc + 4;
1057                         err = __get_user(nir, (u32 __user *)nepc);
1058                         if (err) {
1059                                 err = SIGSEGV;
1060                                 break;
1061                         }
1062                         /*
1063                          * This will probably be optimized away when
1064                          * CONFIG_DEBUG_FS is not enabled
1065                          */
1066                         switch (rt) {
1067                         case bltzal_op:
1068                                 MIPS_R2BR_STATS(bltzal);
1069                                 break;
1070                         case bgezal_op:
1071                                 MIPS_R2BR_STATS(bgezal);
1072                                 break;
1073                         }
1074 
1075                         switch (MIPSInst_OPCODE(nir)) {
1076                         case cop1_op:
1077                         case cop1x_op:
1078                         case lwc1_op:
1079                         case swc1_op:
1080                                 regs->cp0_cause |= CAUSEF_BD;
1081                                 goto fpu_emul;
1082                         }
1083                         if (nir) {
1084                                 err = mipsr6_emul(regs, nir);
1085                                 if (err > 0) {
1086                                         err = mips_dsemul(regs, nir, epc, cpc);
1087                                         if (err == SIGILL)
1088                                                 err = SIGEMT;
1089                                         MIPS_R2_STATS(dsemul);
1090                                 }
1091                         }
1092                         break;
1093                 default:
1094                         regs->regs[31] = r31;
1095                         regs->cp0_epc = epc;
1096                         err = SIGILL;
1097                         break;
1098                 }
1099                 break;
1100 
1101         case blezl_op:
1102         case bgtzl_op:
1103                 /*
1104                  * For BLEZL and BGTZL, rt field must be set to 0. If this
1105                  * is not the case, this may be an encoding of a MIPS R6
1106                  * instruction, so return to CPU execution if this occurs
1107                  */
1108                 if (MIPSInst_RT(inst)) {
1109                         err = SIGILL;
1110                         break;
1111                 }
1112                 /* fall through */
1113         case beql_op:
1114         case bnel_op:
1115                 if (delay_slot(regs)) {
1116                         err = SIGILL;
1117                         break;
1118                 }
1119                 regs->regs[31] = r31;
1120                 regs->cp0_epc = epc;
1121                 err = __compute_return_epc(regs);
1122                 if (err < 0)
1123                         return SIGEMT;
1124                 if (err != BRANCH_LIKELY_TAKEN)
1125                         break;
1126                 cpc = regs->cp0_epc;
1127                 nepc = epc + 4;
1128                 err = __get_user(nir, (u32 __user *)nepc);
1129                 if (err) {
1130                         err = SIGSEGV;
1131                         break;
1132                 }
1133                 /*
1134                  * This will probably be optimized away when
1135                  * CONFIG_DEBUG_FS is not enabled
1136                  */
1137                 switch (MIPSInst_OPCODE(inst)) {
1138                 case beql_op:
1139                         MIPS_R2BR_STATS(beql);
1140                         break;
1141                 case bnel_op:
1142                         MIPS_R2BR_STATS(bnel);
1143                         break;
1144                 case blezl_op:
1145                         MIPS_R2BR_STATS(blezl);
1146                         break;
1147                 case bgtzl_op:
1148                         MIPS_R2BR_STATS(bgtzl);
1149                         break;
1150                 }
1151 
1152                 switch (MIPSInst_OPCODE(nir)) {
1153                 case cop1_op:
1154                 case cop1x_op:
1155                 case lwc1_op:
1156                 case swc1_op:
1157                         regs->cp0_cause |= CAUSEF_BD;
1158                         goto fpu_emul;
1159                 }
1160                 if (nir) {
1161                         err = mipsr6_emul(regs, nir);
1162                         if (err > 0) {
1163                                 err = mips_dsemul(regs, nir, epc, cpc);
1164                                 if (err == SIGILL)
1165                                         err = SIGEMT;
1166                                 MIPS_R2_STATS(dsemul);
1167                         }
1168                 }
1169                 break;
1170         case lwc1_op:
1171         case swc1_op:
1172         case cop1_op:
1173         case cop1x_op:
1174 fpu_emul:
1175                 regs->regs[31] = r31;
1176                 regs->cp0_epc = epc;
1177                 if (!used_math()) {     /* First time FPU user.  */
1178                         preempt_disable();
1179                         err = init_fpu();
1180                         preempt_enable();
1181                         set_used_math();
1182                 }
1183                 lose_fpu(1);    /* Save FPU state for the emulator. */
1184 
1185                 err = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1186                                                &fault_addr);
1187 
1188                 /*
1189                  * We can't allow the emulated instruction to leave any
1190                  * enabled Cause bits set in $fcr31.
1191                  */
1192                 *fcr31 = res = mask_fcr31_x(current->thread.fpu.fcr31);
1193                 current->thread.fpu.fcr31 &= ~res;
1194 
1195                 /*
1196                  * this is a tricky issue - lose_fpu() uses LL/SC atomics
1197                  * if FPU is owned and effectively cancels user level LL/SC.
1198                  * So, it could be logical to don't restore FPU ownership here.
1199                  * But the sequence of multiple FPU instructions is much much
1200                  * more often than LL-FPU-SC and I prefer loop here until
1201                  * next scheduler cycle cancels FPU ownership
1202                  */
1203                 own_fpu(1);     /* Restore FPU state. */
1204 
1205                 if (err)
1206                         current->thread.cp0_baduaddr = (unsigned long)fault_addr;
1207 
1208                 MIPS_R2_STATS(fpus);
1209 
1210                 break;
1211 
1212         case lwl_op:
1213                 rt = regs->regs[MIPSInst_RT(inst)];
1214                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1215                 if (!access_ok(VERIFY_READ, (void __user *)vaddr, 4)) {
1216                         current->thread.cp0_baduaddr = vaddr;
1217                         err = SIGSEGV;
1218                         break;
1219                 }
1220                 __asm__ __volatile__(
1221                         "       .set    push\n"
1222                         "       .set    reorder\n"
1223 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1224                         "1:"    LB      "%1, 0(%2)\n"
1225                                 INS     "%0, %1, 24, 8\n"
1226                         "       andi    %1, %2, 0x3\n"
1227                         "       beq     $0, %1, 9f\n"
1228                                 ADDIU   "%2, %2, -1\n"
1229                         "2:"    LB      "%1, 0(%2)\n"
1230                                 INS     "%0, %1, 16, 8\n"
1231                         "       andi    %1, %2, 0x3\n"
1232                         "       beq     $0, %1, 9f\n"
1233                                 ADDIU   "%2, %2, -1\n"
1234                         "3:"    LB      "%1, 0(%2)\n"
1235                                 INS     "%0, %1, 8, 8\n"
1236                         "       andi    %1, %2, 0x3\n"
1237                         "       beq     $0, %1, 9f\n"
1238                                 ADDIU   "%2, %2, -1\n"
1239                         "4:"    LB      "%1, 0(%2)\n"
1240                                 INS     "%0, %1, 0, 8\n"
1241 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1242                         "1:"    LB      "%1, 0(%2)\n"
1243                                 INS     "%0, %1, 24, 8\n"
1244                                 ADDIU   "%2, %2, 1\n"
1245                         "       andi    %1, %2, 0x3\n"
1246                         "       beq     $0, %1, 9f\n"
1247                         "2:"    LB      "%1, 0(%2)\n"
1248                                 INS     "%0, %1, 16, 8\n"
1249                                 ADDIU   "%2, %2, 1\n"
1250                         "       andi    %1, %2, 0x3\n"
1251                         "       beq     $0, %1, 9f\n"
1252                         "3:"    LB      "%1, 0(%2)\n"
1253                                 INS     "%0, %1, 8, 8\n"
1254                                 ADDIU   "%2, %2, 1\n"
1255                         "       andi    %1, %2, 0x3\n"
1256                         "       beq     $0, %1, 9f\n"
1257                         "4:"    LB      "%1, 0(%2)\n"
1258                                 INS     "%0, %1, 0, 8\n"
1259 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1260                         "9:     sll     %0, %0, 0\n"
1261                         "10:\n"
1262                         "       .insn\n"
1263                         "       .section        .fixup,\"ax\"\n"
1264                         "8:     li      %3,%4\n"
1265                         "       j       10b\n"
1266                         "       .previous\n"
1267                         "       .section        __ex_table,\"a\"\n"
1268                         STR(PTR) " 1b,8b\n"
1269                         STR(PTR) " 2b,8b\n"
1270                         STR(PTR) " 3b,8b\n"
1271                         STR(PTR) " 4b,8b\n"
1272                         "       .previous\n"
1273                         "       .set    pop\n"
1274                         : "+&r"(rt), "=&r"(rs),
1275                           "+&r"(vaddr), "+&r"(err)
1276                         : "i"(SIGSEGV));
1277 
1278                 if (MIPSInst_RT(inst) && !err)
1279                         regs->regs[MIPSInst_RT(inst)] = rt;
1280 
1281                 MIPS_R2_STATS(loads);
1282 
1283                 break;
1284 
1285         case lwr_op:
1286                 rt = regs->regs[MIPSInst_RT(inst)];
1287                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1288                 if (!access_ok(VERIFY_READ, (void __user *)vaddr, 4)) {
1289                         current->thread.cp0_baduaddr = vaddr;
1290                         err = SIGSEGV;
1291                         break;
1292                 }
1293                 __asm__ __volatile__(
1294                         "       .set    push\n"
1295                         "       .set    reorder\n"
1296 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1297                         "1:"    LB      "%1, 0(%2)\n"
1298                                 INS     "%0, %1, 0, 8\n"
1299                                 ADDIU   "%2, %2, 1\n"
1300                         "       andi    %1, %2, 0x3\n"
1301                         "       beq     $0, %1, 9f\n"
1302                         "2:"    LB      "%1, 0(%2)\n"
1303                                 INS     "%0, %1, 8, 8\n"
1304                                 ADDIU   "%2, %2, 1\n"
1305                         "       andi    %1, %2, 0x3\n"
1306                         "       beq     $0, %1, 9f\n"
1307                         "3:"    LB      "%1, 0(%2)\n"
1308                                 INS     "%0, %1, 16, 8\n"
1309                                 ADDIU   "%2, %2, 1\n"
1310                         "       andi    %1, %2, 0x3\n"
1311                         "       beq     $0, %1, 9f\n"
1312                         "4:"    LB      "%1, 0(%2)\n"
1313                                 INS     "%0, %1, 24, 8\n"
1314                         "       sll     %0, %0, 0\n"
1315 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1316                         "1:"    LB      "%1, 0(%2)\n"
1317                                 INS     "%0, %1, 0, 8\n"
1318                         "       andi    %1, %2, 0x3\n"
1319                         "       beq     $0, %1, 9f\n"
1320                                 ADDIU   "%2, %2, -1\n"
1321                         "2:"    LB      "%1, 0(%2)\n"
1322                                 INS     "%0, %1, 8, 8\n"
1323                         "       andi    %1, %2, 0x3\n"
1324                         "       beq     $0, %1, 9f\n"
1325                                 ADDIU   "%2, %2, -1\n"
1326                         "3:"    LB      "%1, 0(%2)\n"
1327                                 INS     "%0, %1, 16, 8\n"
1328                         "       andi    %1, %2, 0x3\n"
1329                         "       beq     $0, %1, 9f\n"
1330                                 ADDIU   "%2, %2, -1\n"
1331                         "4:"    LB      "%1, 0(%2)\n"
1332                                 INS     "%0, %1, 24, 8\n"
1333                         "       sll     %0, %0, 0\n"
1334 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1335                         "9:\n"
1336                         "10:\n"
1337                         "       .insn\n"
1338                         "       .section        .fixup,\"ax\"\n"
1339                         "8:     li      %3,%4\n"
1340                         "       j       10b\n"
1341                         "       .previous\n"
1342                         "       .section        __ex_table,\"a\"\n"
1343                         STR(PTR) " 1b,8b\n"
1344                         STR(PTR) " 2b,8b\n"
1345                         STR(PTR) " 3b,8b\n"
1346                         STR(PTR) " 4b,8b\n"
1347                         "       .previous\n"
1348                         "       .set    pop\n"
1349                         : "+&r"(rt), "=&r"(rs),
1350                           "+&r"(vaddr), "+&r"(err)
1351                         : "i"(SIGSEGV));
1352                 if (MIPSInst_RT(inst) && !err)
1353                         regs->regs[MIPSInst_RT(inst)] = rt;
1354 
1355                 MIPS_R2_STATS(loads);
1356 
1357                 break;
1358 
1359         case swl_op:
1360                 rt = regs->regs[MIPSInst_RT(inst)];
1361                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1362                 if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 4)) {
1363                         current->thread.cp0_baduaddr = vaddr;
1364                         err = SIGSEGV;
1365                         break;
1366                 }
1367                 __asm__ __volatile__(
1368                         "       .set    push\n"
1369                         "       .set    reorder\n"
1370 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1371                                 EXT     "%1, %0, 24, 8\n"
1372                         "1:"    SB      "%1, 0(%2)\n"
1373                         "       andi    %1, %2, 0x3\n"
1374                         "       beq     $0, %1, 9f\n"
1375                                 ADDIU   "%2, %2, -1\n"
1376                                 EXT     "%1, %0, 16, 8\n"
1377                         "2:"    SB      "%1, 0(%2)\n"
1378                         "       andi    %1, %2, 0x3\n"
1379                         "       beq     $0, %1, 9f\n"
1380                                 ADDIU   "%2, %2, -1\n"
1381                                 EXT     "%1, %0, 8, 8\n"
1382                         "3:"    SB      "%1, 0(%2)\n"
1383                         "       andi    %1, %2, 0x3\n"
1384                         "       beq     $0, %1, 9f\n"
1385                                 ADDIU   "%2, %2, -1\n"
1386                                 EXT     "%1, %0, 0, 8\n"
1387                         "4:"    SB      "%1, 0(%2)\n"
1388 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1389                                 EXT     "%1, %0, 24, 8\n"
1390                         "1:"    SB      "%1, 0(%2)\n"
1391                                 ADDIU   "%2, %2, 1\n"
1392                         "       andi    %1, %2, 0x3\n"
1393                         "       beq     $0, %1, 9f\n"
1394                                 EXT     "%1, %0, 16, 8\n"
1395                         "2:"    SB      "%1, 0(%2)\n"
1396                                 ADDIU   "%2, %2, 1\n"
1397                         "       andi    %1, %2, 0x3\n"
1398                         "       beq     $0, %1, 9f\n"
1399                                 EXT     "%1, %0, 8, 8\n"
1400                         "3:"    SB      "%1, 0(%2)\n"
1401                                 ADDIU   "%2, %2, 1\n"
1402                         "       andi    %1, %2, 0x3\n"
1403                         "       beq     $0, %1, 9f\n"
1404                                 EXT     "%1, %0, 0, 8\n"
1405                         "4:"    SB      "%1, 0(%2)\n"
1406 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1407                         "9:\n"
1408                         "       .insn\n"
1409                         "       .section        .fixup,\"ax\"\n"
1410                         "8:     li      %3,%4\n"
1411                         "       j       9b\n"
1412                         "       .previous\n"
1413                         "       .section        __ex_table,\"a\"\n"
1414                         STR(PTR) " 1b,8b\n"
1415                         STR(PTR) " 2b,8b\n"
1416                         STR(PTR) " 3b,8b\n"
1417                         STR(PTR) " 4b,8b\n"
1418                         "       .previous\n"
1419                         "       .set    pop\n"
1420                         : "+&r"(rt), "=&r"(rs),
1421                           "+&r"(vaddr), "+&r"(err)
1422                         : "i"(SIGSEGV)
1423                         : "memory");
1424 
1425                 MIPS_R2_STATS(stores);
1426 
1427                 break;
1428 
1429         case swr_op:
1430                 rt = regs->regs[MIPSInst_RT(inst)];
1431                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1432                 if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 4)) {
1433                         current->thread.cp0_baduaddr = vaddr;
1434                         err = SIGSEGV;
1435                         break;
1436                 }
1437                 __asm__ __volatile__(
1438                         "       .set    push\n"
1439                         "       .set    reorder\n"
1440 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1441                                 EXT     "%1, %0, 0, 8\n"
1442                         "1:"    SB      "%1, 0(%2)\n"
1443                                 ADDIU   "%2, %2, 1\n"
1444                         "       andi    %1, %2, 0x3\n"
1445                         "       beq     $0, %1, 9f\n"
1446                                 EXT     "%1, %0, 8, 8\n"
1447                         "2:"    SB      "%1, 0(%2)\n"
1448                                 ADDIU   "%2, %2, 1\n"
1449                         "       andi    %1, %2, 0x3\n"
1450                         "       beq     $0, %1, 9f\n"
1451                                 EXT     "%1, %0, 16, 8\n"
1452                         "3:"    SB      "%1, 0(%2)\n"
1453                                 ADDIU   "%2, %2, 1\n"
1454                         "       andi    %1, %2, 0x3\n"
1455                         "       beq     $0, %1, 9f\n"
1456                                 EXT     "%1, %0, 24, 8\n"
1457                         "4:"    SB      "%1, 0(%2)\n"
1458 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1459                                 EXT     "%1, %0, 0, 8\n"
1460                         "1:"    SB      "%1, 0(%2)\n"
1461                         "       andi    %1, %2, 0x3\n"
1462                         "       beq     $0, %1, 9f\n"
1463                                 ADDIU   "%2, %2, -1\n"
1464                                 EXT     "%1, %0, 8, 8\n"
1465                         "2:"    SB      "%1, 0(%2)\n"
1466                         "       andi    %1, %2, 0x3\n"
1467                         "       beq     $0, %1, 9f\n"
1468                                 ADDIU   "%2, %2, -1\n"
1469                                 EXT     "%1, %0, 16, 8\n"
1470                         "3:"    SB      "%1, 0(%2)\n"
1471                         "       andi    %1, %2, 0x3\n"
1472                         "       beq     $0, %1, 9f\n"
1473                                 ADDIU   "%2, %2, -1\n"
1474                                 EXT     "%1, %0, 24, 8\n"
1475                         "4:"    SB      "%1, 0(%2)\n"
1476 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1477                         "9:\n"
1478                         "       .insn\n"
1479                         "       .section        .fixup,\"ax\"\n"
1480                         "8:     li      %3,%4\n"
1481                         "       j       9b\n"
1482                         "       .previous\n"
1483                         "       .section        __ex_table,\"a\"\n"
1484                         STR(PTR) " 1b,8b\n"
1485                         STR(PTR) " 2b,8b\n"
1486                         STR(PTR) " 3b,8b\n"
1487                         STR(PTR) " 4b,8b\n"
1488                         "       .previous\n"
1489                         "       .set    pop\n"
1490                         : "+&r"(rt), "=&r"(rs),
1491                           "+&r"(vaddr), "+&r"(err)
1492                         : "i"(SIGSEGV)
1493                         : "memory");
1494 
1495                 MIPS_R2_STATS(stores);
1496 
1497                 break;
1498 
1499         case ldl_op:
1500                 if (IS_ENABLED(CONFIG_32BIT)) {
1501                     err = SIGILL;
1502                     break;
1503                 }
1504 
1505                 rt = regs->regs[MIPSInst_RT(inst)];
1506                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1507                 if (!access_ok(VERIFY_READ, (void __user *)vaddr, 8)) {
1508                         current->thread.cp0_baduaddr = vaddr;
1509                         err = SIGSEGV;
1510                         break;
1511                 }
1512                 __asm__ __volatile__(
1513                         "       .set    push\n"
1514                         "       .set    reorder\n"
1515 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1516                         "1:     lb      %1, 0(%2)\n"
1517                         "       dinsu   %0, %1, 56, 8\n"
1518                         "       andi    %1, %2, 0x7\n"
1519                         "       beq     $0, %1, 9f\n"
1520                         "       daddiu  %2, %2, -1\n"
1521                         "2:     lb      %1, 0(%2)\n"
1522                         "       dinsu   %0, %1, 48, 8\n"
1523                         "       andi    %1, %2, 0x7\n"
1524                         "       beq     $0, %1, 9f\n"
1525                         "       daddiu  %2, %2, -1\n"
1526                         "3:     lb      %1, 0(%2)\n"
1527                         "       dinsu   %0, %1, 40, 8\n"
1528                         "       andi    %1, %2, 0x7\n"
1529                         "       beq     $0, %1, 9f\n"
1530                         "       daddiu  %2, %2, -1\n"
1531                         "4:     lb      %1, 0(%2)\n"
1532                         "       dinsu   %0, %1, 32, 8\n"
1533                         "       andi    %1, %2, 0x7\n"
1534                         "       beq     $0, %1, 9f\n"
1535                         "       daddiu  %2, %2, -1\n"
1536                         "5:     lb      %1, 0(%2)\n"
1537                         "       dins    %0, %1, 24, 8\n"
1538                         "       andi    %1, %2, 0x7\n"
1539                         "       beq     $0, %1, 9f\n"
1540                         "       daddiu  %2, %2, -1\n"
1541                         "6:     lb      %1, 0(%2)\n"
1542                         "       dins    %0, %1, 16, 8\n"
1543                         "       andi    %1, %2, 0x7\n"
1544                         "       beq     $0, %1, 9f\n"
1545                         "       daddiu  %2, %2, -1\n"
1546                         "7:     lb      %1, 0(%2)\n"
1547                         "       dins    %0, %1, 8, 8\n"
1548                         "       andi    %1, %2, 0x7\n"
1549                         "       beq     $0, %1, 9f\n"
1550                         "       daddiu  %2, %2, -1\n"
1551                         "0:     lb      %1, 0(%2)\n"
1552                         "       dins    %0, %1, 0, 8\n"
1553 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1554                         "1:     lb      %1, 0(%2)\n"
1555                         "       dinsu   %0, %1, 56, 8\n"
1556                         "       daddiu  %2, %2, 1\n"
1557                         "       andi    %1, %2, 0x7\n"
1558                         "       beq     $0, %1, 9f\n"
1559                         "2:     lb      %1, 0(%2)\n"
1560                         "       dinsu   %0, %1, 48, 8\n"
1561                         "       daddiu  %2, %2, 1\n"
1562                         "       andi    %1, %2, 0x7\n"
1563                         "       beq     $0, %1, 9f\n"
1564                         "3:     lb      %1, 0(%2)\n"
1565                         "       dinsu   %0, %1, 40, 8\n"
1566                         "       daddiu  %2, %2, 1\n"
1567                         "       andi    %1, %2, 0x7\n"
1568                         "       beq     $0, %1, 9f\n"
1569                         "4:     lb      %1, 0(%2)\n"
1570                         "       dinsu   %0, %1, 32, 8\n"
1571                         "       daddiu  %2, %2, 1\n"
1572                         "       andi    %1, %2, 0x7\n"
1573                         "       beq     $0, %1, 9f\n"
1574                         "5:     lb      %1, 0(%2)\n"
1575                         "       dins    %0, %1, 24, 8\n"
1576                         "       daddiu  %2, %2, 1\n"
1577                         "       andi    %1, %2, 0x7\n"
1578                         "       beq     $0, %1, 9f\n"
1579                         "6:     lb      %1, 0(%2)\n"
1580                         "       dins    %0, %1, 16, 8\n"
1581                         "       daddiu  %2, %2, 1\n"
1582                         "       andi    %1, %2, 0x7\n"
1583                         "       beq     $0, %1, 9f\n"
1584                         "7:     lb      %1, 0(%2)\n"
1585                         "       dins    %0, %1, 8, 8\n"
1586                         "       daddiu  %2, %2, 1\n"
1587                         "       andi    %1, %2, 0x7\n"
1588                         "       beq     $0, %1, 9f\n"
1589                         "0:     lb      %1, 0(%2)\n"
1590                         "       dins    %0, %1, 0, 8\n"
1591 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1592                         "9:\n"
1593                         "       .insn\n"
1594                         "       .section        .fixup,\"ax\"\n"
1595                         "8:     li      %3,%4\n"
1596                         "       j       9b\n"
1597                         "       .previous\n"
1598                         "       .section        __ex_table,\"a\"\n"
1599                         STR(PTR) " 1b,8b\n"
1600                         STR(PTR) " 2b,8b\n"
1601                         STR(PTR) " 3b,8b\n"
1602                         STR(PTR) " 4b,8b\n"
1603                         STR(PTR) " 5b,8b\n"
1604                         STR(PTR) " 6b,8b\n"
1605                         STR(PTR) " 7b,8b\n"
1606                         STR(PTR) " 0b,8b\n"
1607                         "       .previous\n"
1608                         "       .set    pop\n"
1609                         : "+&r"(rt), "=&r"(rs),
1610                           "+&r"(vaddr), "+&r"(err)
1611                         : "i"(SIGSEGV));
1612                 if (MIPSInst_RT(inst) && !err)
1613                         regs->regs[MIPSInst_RT(inst)] = rt;
1614 
1615                 MIPS_R2_STATS(loads);
1616                 break;
1617 
1618         case ldr_op:
1619                 if (IS_ENABLED(CONFIG_32BIT)) {
1620                     err = SIGILL;
1621                     break;
1622                 }
1623 
1624                 rt = regs->regs[MIPSInst_RT(inst)];
1625                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1626                 if (!access_ok(VERIFY_READ, (void __user *)vaddr, 8)) {
1627                         current->thread.cp0_baduaddr = vaddr;
1628                         err = SIGSEGV;
1629                         break;
1630                 }
1631                 __asm__ __volatile__(
1632                         "       .set    push\n"
1633                         "       .set    reorder\n"
1634 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1635                         "1:     lb      %1, 0(%2)\n"
1636                         "       dins   %0, %1, 0, 8\n"
1637                         "       daddiu  %2, %2, 1\n"
1638                         "       andi    %1, %2, 0x7\n"
1639                         "       beq     $0, %1, 9f\n"
1640                         "2:     lb      %1, 0(%2)\n"
1641                         "       dins   %0, %1, 8, 8\n"
1642                         "       daddiu  %2, %2, 1\n"
1643                         "       andi    %1, %2, 0x7\n"
1644                         "       beq     $0, %1, 9f\n"
1645                         "3:     lb      %1, 0(%2)\n"
1646                         "       dins   %0, %1, 16, 8\n"
1647                         "       daddiu  %2, %2, 1\n"
1648                         "       andi    %1, %2, 0x7\n"
1649                         "       beq     $0, %1, 9f\n"
1650                         "4:     lb      %1, 0(%2)\n"
1651                         "       dins   %0, %1, 24, 8\n"
1652                         "       daddiu  %2, %2, 1\n"
1653                         "       andi    %1, %2, 0x7\n"
1654                         "       beq     $0, %1, 9f\n"
1655                         "5:     lb      %1, 0(%2)\n"
1656                         "       dinsu    %0, %1, 32, 8\n"
1657                         "       daddiu  %2, %2, 1\n"
1658                         "       andi    %1, %2, 0x7\n"
1659                         "       beq     $0, %1, 9f\n"
1660                         "6:     lb      %1, 0(%2)\n"
1661                         "       dinsu    %0, %1, 40, 8\n"
1662                         "       daddiu  %2, %2, 1\n"
1663                         "       andi    %1, %2, 0x7\n"
1664                         "       beq     $0, %1, 9f\n"
1665                         "7:     lb      %1, 0(%2)\n"
1666                         "       dinsu    %0, %1, 48, 8\n"
1667                         "       daddiu  %2, %2, 1\n"
1668                         "       andi    %1, %2, 0x7\n"
1669                         "       beq     $0, %1, 9f\n"
1670                         "0:     lb      %1, 0(%2)\n"
1671                         "       dinsu    %0, %1, 56, 8\n"
1672 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1673                         "1:     lb      %1, 0(%2)\n"
1674                         "       dins   %0, %1, 0, 8\n"
1675                         "       andi    %1, %2, 0x7\n"
1676                         "       beq     $0, %1, 9f\n"
1677                         "       daddiu  %2, %2, -1\n"
1678                         "2:     lb      %1, 0(%2)\n"
1679                         "       dins   %0, %1, 8, 8\n"
1680                         "       andi    %1, %2, 0x7\n"
1681                         "       beq     $0, %1, 9f\n"
1682                         "       daddiu  %2, %2, -1\n"
1683                         "3:     lb      %1, 0(%2)\n"
1684                         "       dins   %0, %1, 16, 8\n"
1685                         "       andi    %1, %2, 0x7\n"
1686                         "       beq     $0, %1, 9f\n"
1687                         "       daddiu  %2, %2, -1\n"
1688                         "4:     lb      %1, 0(%2)\n"
1689                         "       dins   %0, %1, 24, 8\n"
1690                         "       andi    %1, %2, 0x7\n"
1691                         "       beq     $0, %1, 9f\n"
1692                         "       daddiu  %2, %2, -1\n"
1693                         "5:     lb      %1, 0(%2)\n"
1694                         "       dinsu    %0, %1, 32, 8\n"
1695                         "       andi    %1, %2, 0x7\n"
1696                         "       beq     $0, %1, 9f\n"
1697                         "       daddiu  %2, %2, -1\n"
1698                         "6:     lb      %1, 0(%2)\n"
1699                         "       dinsu    %0, %1, 40, 8\n"
1700                         "       andi    %1, %2, 0x7\n"
1701                         "       beq     $0, %1, 9f\n"
1702                         "       daddiu  %2, %2, -1\n"
1703                         "7:     lb      %1, 0(%2)\n"
1704                         "       dinsu    %0, %1, 48, 8\n"
1705                         "       andi    %1, %2, 0x7\n"
1706                         "       beq     $0, %1, 9f\n"
1707                         "       daddiu  %2, %2, -1\n"
1708                         "0:     lb      %1, 0(%2)\n"
1709                         "       dinsu    %0, %1, 56, 8\n"
1710 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1711                         "9:\n"
1712                         "       .insn\n"
1713                         "       .section        .fixup,\"ax\"\n"
1714                         "8:     li     %3,%4\n"
1715                         "       j      9b\n"
1716                         "       .previous\n"
1717                         "       .section        __ex_table,\"a\"\n"
1718                         STR(PTR) " 1b,8b\n"
1719                         STR(PTR) " 2b,8b\n"
1720                         STR(PTR) " 3b,8b\n"
1721                         STR(PTR) " 4b,8b\n"
1722                         STR(PTR) " 5b,8b\n"
1723                         STR(PTR) " 6b,8b\n"
1724                         STR(PTR) " 7b,8b\n"
1725                         STR(PTR) " 0b,8b\n"
1726                         "       .previous\n"
1727                         "       .set    pop\n"
1728                         : "+&r"(rt), "=&r"(rs),
1729                           "+&r"(vaddr), "+&r"(err)
1730                         : "i"(SIGSEGV));
1731                 if (MIPSInst_RT(inst) && !err)
1732                         regs->regs[MIPSInst_RT(inst)] = rt;
1733 
1734                 MIPS_R2_STATS(loads);
1735                 break;
1736 
1737         case sdl_op:
1738                 if (IS_ENABLED(CONFIG_32BIT)) {
1739                     err = SIGILL;
1740                     break;
1741                 }
1742 
1743                 rt = regs->regs[MIPSInst_RT(inst)];
1744                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1745                 if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 8)) {
1746                         current->thread.cp0_baduaddr = vaddr;
1747                         err = SIGSEGV;
1748                         break;
1749                 }
1750                 __asm__ __volatile__(
1751                         "       .set    push\n"
1752                         "       .set    reorder\n"
1753 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1754                         "       dextu   %1, %0, 56, 8\n"
1755                         "1:     sb      %1, 0(%2)\n"
1756                         "       andi    %1, %2, 0x7\n"
1757                         "       beq     $0, %1, 9f\n"
1758                         "       daddiu  %2, %2, -1\n"
1759                         "       dextu   %1, %0, 48, 8\n"
1760                         "2:     sb      %1, 0(%2)\n"
1761                         "       andi    %1, %2, 0x7\n"
1762                         "       beq     $0, %1, 9f\n"
1763                         "       daddiu  %2, %2, -1\n"
1764                         "       dextu   %1, %0, 40, 8\n"
1765                         "3:     sb      %1, 0(%2)\n"
1766                         "       andi    %1, %2, 0x7\n"
1767                         "       beq     $0, %1, 9f\n"
1768                         "       daddiu  %2, %2, -1\n"
1769                         "       dextu   %1, %0, 32, 8\n"
1770                         "4:     sb      %1, 0(%2)\n"
1771                         "       andi    %1, %2, 0x7\n"
1772                         "       beq     $0, %1, 9f\n"
1773                         "       daddiu  %2, %2, -1\n"
1774                         "       dext    %1, %0, 24, 8\n"
1775                         "5:     sb      %1, 0(%2)\n"
1776                         "       andi    %1, %2, 0x7\n"
1777                         "       beq     $0, %1, 9f\n"
1778                         "       daddiu  %2, %2, -1\n"
1779                         "       dext    %1, %0, 16, 8\n"
1780                         "6:     sb      %1, 0(%2)\n"
1781                         "       andi    %1, %2, 0x7\n"
1782                         "       beq     $0, %1, 9f\n"
1783                         "       daddiu  %2, %2, -1\n"
1784                         "       dext    %1, %0, 8, 8\n"
1785                         "7:     sb      %1, 0(%2)\n"
1786                         "       andi    %1, %2, 0x7\n"
1787                         "       beq     $0, %1, 9f\n"
1788                         "       daddiu  %2, %2, -1\n"
1789                         "       dext    %1, %0, 0, 8\n"
1790                         "0:     sb      %1, 0(%2)\n"
1791 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1792                         "       dextu   %1, %0, 56, 8\n"
1793                         "1:     sb      %1, 0(%2)\n"
1794                         "       daddiu  %2, %2, 1\n"
1795                         "       andi    %1, %2, 0x7\n"
1796                         "       beq     $0, %1, 9f\n"
1797                         "       dextu   %1, %0, 48, 8\n"
1798                         "2:     sb      %1, 0(%2)\n"
1799                         "       daddiu  %2, %2, 1\n"
1800                         "       andi    %1, %2, 0x7\n"
1801                         "       beq     $0, %1, 9f\n"
1802                         "       dextu   %1, %0, 40, 8\n"
1803                         "3:     sb      %1, 0(%2)\n"
1804                         "       daddiu  %2, %2, 1\n"
1805                         "       andi    %1, %2, 0x7\n"
1806                         "       beq     $0, %1, 9f\n"
1807                         "       dextu   %1, %0, 32, 8\n"
1808                         "4:     sb      %1, 0(%2)\n"
1809                         "       daddiu  %2, %2, 1\n"
1810                         "       andi    %1, %2, 0x7\n"
1811                         "       beq     $0, %1, 9f\n"
1812                         "       dext    %1, %0, 24, 8\n"
1813                         "5:     sb      %1, 0(%2)\n"
1814                         "       daddiu  %2, %2, 1\n"
1815                         "       andi    %1, %2, 0x7\n"
1816                         "       beq     $0, %1, 9f\n"
1817                         "       dext    %1, %0, 16, 8\n"
1818                         "6:     sb      %1, 0(%2)\n"
1819                         "       daddiu  %2, %2, 1\n"
1820                         "       andi    %1, %2, 0x7\n"
1821                         "       beq     $0, %1, 9f\n"
1822                         "       dext    %1, %0, 8, 8\n"
1823                         "7:     sb      %1, 0(%2)\n"
1824                         "       daddiu  %2, %2, 1\n"
1825                         "       andi    %1, %2, 0x7\n"
1826                         "       beq     $0, %1, 9f\n"
1827                         "       dext    %1, %0, 0, 8\n"
1828                         "0:     sb      %1, 0(%2)\n"
1829 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1830                         "9:\n"
1831                         "       .insn\n"
1832                         "       .section        .fixup,\"ax\"\n"
1833                         "8:     li      %3,%4\n"
1834                         "       j       9b\n"
1835                         "       .previous\n"
1836                         "       .section        __ex_table,\"a\"\n"
1837                         STR(PTR) " 1b,8b\n"
1838                         STR(PTR) " 2b,8b\n"
1839                         STR(PTR) " 3b,8b\n"
1840                         STR(PTR) " 4b,8b\n"
1841                         STR(PTR) " 5b,8b\n"
1842                         STR(PTR) " 6b,8b\n"
1843                         STR(PTR) " 7b,8b\n"
1844                         STR(PTR) " 0b,8b\n"
1845                         "       .previous\n"
1846                         "       .set    pop\n"
1847                         : "+&r"(rt), "=&r"(rs),
1848                           "+&r"(vaddr), "+&r"(err)
1849                         : "i"(SIGSEGV)
1850                         : "memory");
1851 
1852                 MIPS_R2_STATS(stores);
1853                 break;
1854 
1855         case sdr_op:
1856                 if (IS_ENABLED(CONFIG_32BIT)) {
1857                     err = SIGILL;
1858                     break;
1859                 }
1860 
1861                 rt = regs->regs[MIPSInst_RT(inst)];
1862                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1863                 if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 8)) {
1864                         current->thread.cp0_baduaddr = vaddr;
1865                         err = SIGSEGV;
1866                         break;
1867                 }
1868                 __asm__ __volatile__(
1869                         "       .set    push\n"
1870                         "       .set    reorder\n"
1871 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1872                         "       dext    %1, %0, 0, 8\n"
1873                         "1:     sb      %1, 0(%2)\n"
1874                         "       daddiu  %2, %2, 1\n"
1875                         "       andi    %1, %2, 0x7\n"
1876                         "       beq     $0, %1, 9f\n"
1877                         "       dext    %1, %0, 8, 8\n"
1878                         "2:     sb      %1, 0(%2)\n"
1879                         "       daddiu  %2, %2, 1\n"
1880                         "       andi    %1, %2, 0x7\n"
1881                         "       beq     $0, %1, 9f\n"
1882                         "       dext    %1, %0, 16, 8\n"
1883                         "3:     sb      %1, 0(%2)\n"
1884                         "       daddiu  %2, %2, 1\n"
1885                         "       andi    %1, %2, 0x7\n"
1886                         "       beq     $0, %1, 9f\n"
1887                         "       dext    %1, %0, 24, 8\n"
1888                         "4:     sb      %1, 0(%2)\n"
1889                         "       daddiu  %2, %2, 1\n"
1890                         "       andi    %1, %2, 0x7\n"
1891                         "       beq     $0, %1, 9f\n"
1892                         "       dextu   %1, %0, 32, 8\n"
1893                         "5:     sb      %1, 0(%2)\n"
1894                         "       daddiu  %2, %2, 1\n"
1895                         "       andi    %1, %2, 0x7\n"
1896                         "       beq     $0, %1, 9f\n"
1897                         "       dextu   %1, %0, 40, 8\n"
1898                         "6:     sb      %1, 0(%2)\n"
1899                         "       daddiu  %2, %2, 1\n"
1900                         "       andi    %1, %2, 0x7\n"
1901                         "       beq     $0, %1, 9f\n"
1902                         "       dextu   %1, %0, 48, 8\n"
1903                         "7:     sb      %1, 0(%2)\n"
1904                         "       daddiu  %2, %2, 1\n"
1905                         "       andi    %1, %2, 0x7\n"
1906                         "       beq     $0, %1, 9f\n"
1907                         "       dextu   %1, %0, 56, 8\n"
1908                         "0:     sb      %1, 0(%2)\n"
1909 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1910                         "       dext    %1, %0, 0, 8\n"
1911                         "1:     sb      %1, 0(%2)\n"
1912                         "       andi    %1, %2, 0x7\n"
1913                         "       beq     $0, %1, 9f\n"
1914                         "       daddiu  %2, %2, -1\n"
1915                         "       dext    %1, %0, 8, 8\n"
1916                         "2:     sb      %1, 0(%2)\n"
1917                         "       andi    %1, %2, 0x7\n"
1918                         "       beq     $0, %1, 9f\n"
1919                         "       daddiu  %2, %2, -1\n"
1920                         "       dext    %1, %0, 16, 8\n"
1921                         "3:     sb      %1, 0(%2)\n"
1922                         "       andi    %1, %2, 0x7\n"
1923                         "       beq     $0, %1, 9f\n"
1924                         "       daddiu  %2, %2, -1\n"
1925                         "       dext    %1, %0, 24, 8\n"
1926                         "4:     sb      %1, 0(%2)\n"
1927                         "       andi    %1, %2, 0x7\n"
1928                         "       beq     $0, %1, 9f\n"
1929                         "       daddiu  %2, %2, -1\n"
1930                         "       dextu   %1, %0, 32, 8\n"
1931                         "5:     sb      %1, 0(%2)\n"
1932                         "       andi    %1, %2, 0x7\n"
1933                         "       beq     $0, %1, 9f\n"
1934                         "       daddiu  %2, %2, -1\n"
1935                         "       dextu   %1, %0, 40, 8\n"
1936                         "6:     sb      %1, 0(%2)\n"
1937                         "       andi    %1, %2, 0x7\n"
1938                         "       beq     $0, %1, 9f\n"
1939                         "       daddiu  %2, %2, -1\n"
1940                         "       dextu   %1, %0, 48, 8\n"
1941                         "7:     sb      %1, 0(%2)\n"
1942                         "       andi    %1, %2, 0x7\n"
1943                         "       beq     $0, %1, 9f\n"
1944                         "       daddiu  %2, %2, -1\n"
1945                         "       dextu   %1, %0, 56, 8\n"
1946                         "0:     sb      %1, 0(%2)\n"
1947 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1948                         "9:\n"
1949                         "       .insn\n"
1950                         "       .section        .fixup,\"ax\"\n"
1951                         "8:     li      %3,%4\n"
1952                         "       j       9b\n"
1953                         "       .previous\n"
1954                         "       .section        __ex_table,\"a\"\n"
1955                         STR(PTR) " 1b,8b\n"
1956                         STR(PTR) " 2b,8b\n"
1957                         STR(PTR) " 3b,8b\n"
1958                         STR(PTR) " 4b,8b\n"
1959                         STR(PTR) " 5b,8b\n"
1960                         STR(PTR) " 6b,8b\n"
1961                         STR(PTR) " 7b,8b\n"
1962                         STR(PTR) " 0b,8b\n"
1963                         "       .previous\n"
1964                         "       .set    pop\n"
1965                         : "+&r"(rt), "=&r"(rs),
1966                           "+&r"(vaddr), "+&r"(err)
1967                         : "i"(SIGSEGV)
1968                         : "memory");
1969 
1970                 MIPS_R2_STATS(stores);
1971 
1972                 break;
1973         case ll_op:
1974                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1975                 if (vaddr & 0x3) {
1976                         current->thread.cp0_baduaddr = vaddr;
1977                         err = SIGBUS;
1978                         break;
1979                 }
1980                 if (!access_ok(VERIFY_READ, (void __user *)vaddr, 4)) {
1981                         current->thread.cp0_baduaddr = vaddr;
1982                         err = SIGBUS;
1983                         break;
1984                 }
1985 
1986                 if (!cpu_has_rw_llb) {
1987                         /*
1988                          * An LL/SC block can't be safely emulated without
1989                          * a Config5/LLB availability. So it's probably time to
1990                          * kill our process before things get any worse. This is
1991                          * because Config5/LLB allows us to use ERETNC so that
1992                          * the LLAddr/LLB bit is not cleared when we return from
1993                          * an exception. MIPS R2 LL/SC instructions trap with an
1994                          * RI exception so once we emulate them here, we return
1995                          * back to userland with ERETNC. That preserves the
1996                          * LLAddr/LLB so the subsequent SC instruction will
1997                          * succeed preserving the atomic semantics of the LL/SC
1998                          * block. Without that, there is no safe way to emulate
1999                          * an LL/SC block in MIPSR2 userland.
2000                          */
2001                         pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2002                         err = SIGKILL;
2003                         break;
2004                 }
2005 
2006                 __asm__ __volatile__(
2007                         "1:\n"
2008                         "ll     %0, 0(%2)\n"
2009                         "2:\n"
2010                         ".insn\n"
2011                         ".section        .fixup,\"ax\"\n"
2012                         "3:\n"
2013                         "li     %1, %3\n"
2014                         "j      2b\n"
2015                         ".previous\n"
2016                         ".section        __ex_table,\"a\"\n"
2017                         STR(PTR) " 1b,3b\n"
2018                         ".previous\n"
2019                         : "=&r"(res), "+&r"(err)
2020                         : "r"(vaddr), "i"(SIGSEGV)
2021                         : "memory");
2022 
2023                 if (MIPSInst_RT(inst) && !err)
2024                         regs->regs[MIPSInst_RT(inst)] = res;
2025                 MIPS_R2_STATS(llsc);
2026 
2027                 break;
2028 
2029         case sc_op:
2030                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2031                 if (vaddr & 0x3) {
2032                         current->thread.cp0_baduaddr = vaddr;
2033                         err = SIGBUS;
2034                         break;
2035                 }
2036                 if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 4)) {
2037                         current->thread.cp0_baduaddr = vaddr;
2038                         err = SIGBUS;
2039                         break;
2040                 }
2041 
2042                 if (!cpu_has_rw_llb) {
2043                         /*
2044                          * An LL/SC block can't be safely emulated without
2045                          * a Config5/LLB availability. So it's probably time to
2046                          * kill our process before things get any worse. This is
2047                          * because Config5/LLB allows us to use ERETNC so that
2048                          * the LLAddr/LLB bit is not cleared when we return from
2049                          * an exception. MIPS R2 LL/SC instructions trap with an
2050                          * RI exception so once we emulate them here, we return
2051                          * back to userland with ERETNC. That preserves the
2052                          * LLAddr/LLB so the subsequent SC instruction will
2053                          * succeed preserving the atomic semantics of the LL/SC
2054                          * block. Without that, there is no safe way to emulate
2055                          * an LL/SC block in MIPSR2 userland.
2056                          */
2057                         pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2058                         err = SIGKILL;
2059                         break;
2060                 }
2061 
2062                 res = regs->regs[MIPSInst_RT(inst)];
2063 
2064                 __asm__ __volatile__(
2065                         "1:\n"
2066                         "sc     %0, 0(%2)\n"
2067                         "2:\n"
2068                         ".insn\n"
2069                         ".section        .fixup,\"ax\"\n"
2070                         "3:\n"
2071                         "li     %1, %3\n"
2072                         "j      2b\n"
2073                         ".previous\n"
2074                         ".section        __ex_table,\"a\"\n"
2075                         STR(PTR) " 1b,3b\n"
2076                         ".previous\n"
2077                         : "+&r"(res), "+&r"(err)
2078                         : "r"(vaddr), "i"(SIGSEGV));
2079 
2080                 if (MIPSInst_RT(inst) && !err)
2081                         regs->regs[MIPSInst_RT(inst)] = res;
2082 
2083                 MIPS_R2_STATS(llsc);
2084 
2085                 break;
2086 
2087         case lld_op:
2088                 if (IS_ENABLED(CONFIG_32BIT)) {
2089                     err = SIGILL;
2090                     break;
2091                 }
2092 
2093                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2094                 if (vaddr & 0x7) {
2095                         current->thread.cp0_baduaddr = vaddr;
2096                         err = SIGBUS;
2097                         break;
2098                 }
2099                 if (!access_ok(VERIFY_READ, (void __user *)vaddr, 8)) {
2100                         current->thread.cp0_baduaddr = vaddr;
2101                         err = SIGBUS;
2102                         break;
2103                 }
2104 
2105                 if (!cpu_has_rw_llb) {
2106                         /*
2107                          * An LL/SC block can't be safely emulated without
2108                          * a Config5/LLB availability. So it's probably time to
2109                          * kill our process before things get any worse. This is
2110                          * because Config5/LLB allows us to use ERETNC so that
2111                          * the LLAddr/LLB bit is not cleared when we return from
2112                          * an exception. MIPS R2 LL/SC instructions trap with an
2113                          * RI exception so once we emulate them here, we return
2114                          * back to userland with ERETNC. That preserves the
2115                          * LLAddr/LLB so the subsequent SC instruction will
2116                          * succeed preserving the atomic semantics of the LL/SC
2117                          * block. Without that, there is no safe way to emulate
2118                          * an LL/SC block in MIPSR2 userland.
2119                          */
2120                         pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2121                         err = SIGKILL;
2122                         break;
2123                 }
2124 
2125                 __asm__ __volatile__(
2126                         "1:\n"
2127                         "lld    %0, 0(%2)\n"
2128                         "2:\n"
2129                         ".insn\n"
2130                         ".section        .fixup,\"ax\"\n"
2131                         "3:\n"
2132                         "li     %1, %3\n"
2133                         "j      2b\n"
2134                         ".previous\n"
2135                         ".section        __ex_table,\"a\"\n"
2136                         STR(PTR) " 1b,3b\n"
2137                         ".previous\n"
2138                         : "=&r"(res), "+&r"(err)
2139                         : "r"(vaddr), "i"(SIGSEGV)
2140                         : "memory");
2141                 if (MIPSInst_RT(inst) && !err)
2142                         regs->regs[MIPSInst_RT(inst)] = res;
2143 
2144                 MIPS_R2_STATS(llsc);
2145 
2146                 break;
2147 
2148         case scd_op:
2149                 if (IS_ENABLED(CONFIG_32BIT)) {
2150                     err = SIGILL;
2151                     break;
2152                 }
2153 
2154                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2155                 if (vaddr & 0x7) {
2156                         current->thread.cp0_baduaddr = vaddr;
2157                         err = SIGBUS;
2158                         break;
2159                 }
2160                 if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 8)) {
2161                         current->thread.cp0_baduaddr = vaddr;
2162                         err = SIGBUS;
2163                         break;
2164                 }
2165 
2166                 if (!cpu_has_rw_llb) {
2167                         /*
2168                          * An LL/SC block can't be safely emulated without
2169                          * a Config5/LLB availability. So it's probably time to
2170                          * kill our process before things get any worse. This is
2171                          * because Config5/LLB allows us to use ERETNC so that
2172                          * the LLAddr/LLB bit is not cleared when we return from
2173                          * an exception. MIPS R2 LL/SC instructions trap with an
2174                          * RI exception so once we emulate them here, we return
2175                          * back to userland with ERETNC. That preserves the
2176                          * LLAddr/LLB so the subsequent SC instruction will
2177                          * succeed preserving the atomic semantics of the LL/SC
2178                          * block. Without that, there is no safe way to emulate
2179                          * an LL/SC block in MIPSR2 userland.
2180                          */
2181                         pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2182                         err = SIGKILL;
2183                         break;
2184                 }
2185 
2186                 res = regs->regs[MIPSInst_RT(inst)];
2187 
2188                 __asm__ __volatile__(
2189                         "1:\n"
2190                         "scd    %0, 0(%2)\n"
2191                         "2:\n"
2192                         ".insn\n"
2193                         ".section        .fixup,\"ax\"\n"
2194                         "3:\n"
2195                         "li     %1, %3\n"
2196                         "j      2b\n"
2197                         ".previous\n"
2198                         ".section        __ex_table,\"a\"\n"
2199                         STR(PTR) " 1b,3b\n"
2200                         ".previous\n"
2201                         : "+&r"(res), "+&r"(err)
2202                         : "r"(vaddr), "i"(SIGSEGV));
2203 
2204                 if (MIPSInst_RT(inst) && !err)
2205                         regs->regs[MIPSInst_RT(inst)] = res;
2206 
2207                 MIPS_R2_STATS(llsc);
2208 
2209                 break;
2210         case pref_op:
2211                 /* skip it */
2212                 break;
2213         default:
2214                 err = SIGILL;
2215         }
2216 
2217         /*
2218          * Let's not return to userland just yet. It's costly and
2219          * it's likely we have more R2 instructions to emulate
2220          */
2221         if (!err && (pass++ < MIPS_R2_EMUL_TOTAL_PASS)) {
2222                 regs->cp0_cause &= ~CAUSEF_BD;
2223                 err = get_user(inst, (u32 __user *)regs->cp0_epc);
2224                 if (!err)
2225                         goto repeat;
2226 
2227                 if (err < 0)
2228                         err = SIGSEGV;
2229         }
2230 
2231         if (err && (err != SIGEMT)) {
2232                 regs->regs[31] = r31;
2233                 regs->cp0_epc = epc;
2234         }
2235 
2236         /* Likely a MIPS R6 compatible instruction */
2237         if (pass && (err == SIGILL))
2238                 err = 0;
2239 
2240         return err;
2241 }
2242 
2243 #ifdef CONFIG_DEBUG_FS
2244 
2245 static int mipsr2_stats_show(struct seq_file *s, void *unused)
2246 {
2247 
2248         seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n");
2249         seq_printf(s, "movs\t\t%ld\t%ld\n",
2250                    (unsigned long)__this_cpu_read(mipsr2emustats.movs),
2251                    (unsigned long)__this_cpu_read(mipsr2bdemustats.movs));
2252         seq_printf(s, "hilo\t\t%ld\t%ld\n",
2253                    (unsigned long)__this_cpu_read(mipsr2emustats.hilo),
2254                    (unsigned long)__this_cpu_read(mipsr2bdemustats.hilo));
2255         seq_printf(s, "muls\t\t%ld\t%ld\n",
2256                    (unsigned long)__this_cpu_read(mipsr2emustats.muls),
2257                    (unsigned long)__this_cpu_read(mipsr2bdemustats.muls));
2258         seq_printf(s, "divs\t\t%ld\t%ld\n",
2259                    (unsigned long)__this_cpu_read(mipsr2emustats.divs),
2260                    (unsigned long)__this_cpu_read(mipsr2bdemustats.divs));
2261         seq_printf(s, "dsps\t\t%ld\t%ld\n",
2262                    (unsigned long)__this_cpu_read(mipsr2emustats.dsps),
2263                    (unsigned long)__this_cpu_read(mipsr2bdemustats.dsps));
2264         seq_printf(s, "bops\t\t%ld\t%ld\n",
2265                    (unsigned long)__this_cpu_read(mipsr2emustats.bops),
2266                    (unsigned long)__this_cpu_read(mipsr2bdemustats.bops));
2267         seq_printf(s, "traps\t\t%ld\t%ld\n",
2268                    (unsigned long)__this_cpu_read(mipsr2emustats.traps),
2269                    (unsigned long)__this_cpu_read(mipsr2bdemustats.traps));
2270         seq_printf(s, "fpus\t\t%ld\t%ld\n",
2271                    (unsigned long)__this_cpu_read(mipsr2emustats.fpus),
2272                    (unsigned long)__this_cpu_read(mipsr2bdemustats.fpus));
2273         seq_printf(s, "loads\t\t%ld\t%ld\n",
2274                    (unsigned long)__this_cpu_read(mipsr2emustats.loads),
2275                    (unsigned long)__this_cpu_read(mipsr2bdemustats.loads));
2276         seq_printf(s, "stores\t\t%ld\t%ld\n",
2277                    (unsigned long)__this_cpu_read(mipsr2emustats.stores),
2278                    (unsigned long)__this_cpu_read(mipsr2bdemustats.stores));
2279         seq_printf(s, "llsc\t\t%ld\t%ld\n",
2280                    (unsigned long)__this_cpu_read(mipsr2emustats.llsc),
2281                    (unsigned long)__this_cpu_read(mipsr2bdemustats.llsc));
2282         seq_printf(s, "dsemul\t\t%ld\t%ld\n",
2283                    (unsigned long)__this_cpu_read(mipsr2emustats.dsemul),
2284                    (unsigned long)__this_cpu_read(mipsr2bdemustats.dsemul));
2285         seq_printf(s, "jr\t\t%ld\n",
2286                    (unsigned long)__this_cpu_read(mipsr2bremustats.jrs));
2287         seq_printf(s, "bltzl\t\t%ld\n",
2288                    (unsigned long)__this_cpu_read(mipsr2bremustats.bltzl));
2289         seq_printf(s, "bgezl\t\t%ld\n",
2290                    (unsigned long)__this_cpu_read(mipsr2bremustats.bgezl));
2291         seq_printf(s, "bltzll\t\t%ld\n",
2292                    (unsigned long)__this_cpu_read(mipsr2bremustats.bltzll));
2293         seq_printf(s, "bgezll\t\t%ld\n",
2294                    (unsigned long)__this_cpu_read(mipsr2bremustats.bgezll));
2295         seq_printf(s, "bltzal\t\t%ld\n",
2296                    (unsigned long)__this_cpu_read(mipsr2bremustats.bltzal));
2297         seq_printf(s, "bgezal\t\t%ld\n",
2298                    (unsigned long)__this_cpu_read(mipsr2bremustats.bgezal));
2299         seq_printf(s, "beql\t\t%ld\n",
2300                    (unsigned long)__this_cpu_read(mipsr2bremustats.beql));
2301         seq_printf(s, "bnel\t\t%ld\n",
2302                    (unsigned long)__this_cpu_read(mipsr2bremustats.bnel));
2303         seq_printf(s, "blezl\t\t%ld\n",
2304                    (unsigned long)__this_cpu_read(mipsr2bremustats.blezl));
2305         seq_printf(s, "bgtzl\t\t%ld\n",
2306                    (unsigned long)__this_cpu_read(mipsr2bremustats.bgtzl));
2307 
2308         return 0;
2309 }
2310 
2311 static int mipsr2_stats_clear_show(struct seq_file *s, void *unused)
2312 {
2313         mipsr2_stats_show(s, unused);
2314 
2315         __this_cpu_write((mipsr2emustats).movs, 0);
2316         __this_cpu_write((mipsr2bdemustats).movs, 0);
2317         __this_cpu_write((mipsr2emustats).hilo, 0);
2318         __this_cpu_write((mipsr2bdemustats).hilo, 0);
2319         __this_cpu_write((mipsr2emustats).muls, 0);
2320         __this_cpu_write((mipsr2bdemustats).muls, 0);
2321         __this_cpu_write((mipsr2emustats).divs, 0);
2322         __this_cpu_write((mipsr2bdemustats).divs, 0);
2323         __this_cpu_write((mipsr2emustats).dsps, 0);
2324         __this_cpu_write((mipsr2bdemustats).dsps, 0);
2325         __this_cpu_write((mipsr2emustats).bops, 0);
2326         __this_cpu_write((mipsr2bdemustats).bops, 0);
2327         __this_cpu_write((mipsr2emustats).traps, 0);
2328         __this_cpu_write((mipsr2bdemustats).traps, 0);
2329         __this_cpu_write((mipsr2emustats).fpus, 0);
2330         __this_cpu_write((mipsr2bdemustats).fpus, 0);
2331         __this_cpu_write((mipsr2emustats).loads, 0);
2332         __this_cpu_write((mipsr2bdemustats).loads, 0);
2333         __this_cpu_write((mipsr2emustats).stores, 0);
2334         __this_cpu_write((mipsr2bdemustats).stores, 0);
2335         __this_cpu_write((mipsr2emustats).llsc, 0);
2336         __this_cpu_write((mipsr2bdemustats).llsc, 0);
2337         __this_cpu_write((mipsr2emustats).dsemul, 0);
2338         __this_cpu_write((mipsr2bdemustats).dsemul, 0);
2339         __this_cpu_write((mipsr2bremustats).jrs, 0);
2340         __this_cpu_write((mipsr2bremustats).bltzl, 0);
2341         __this_cpu_write((mipsr2bremustats).bgezl, 0);
2342         __this_cpu_write((mipsr2bremustats).bltzll, 0);
2343         __this_cpu_write((mipsr2bremustats).bgezll, 0);
2344         __this_cpu_write((mipsr2bremustats).bltzall, 0);
2345         __this_cpu_write((mipsr2bremustats).bgezall, 0);
2346         __this_cpu_write((mipsr2bremustats).bltzal, 0);
2347         __this_cpu_write((mipsr2bremustats).bgezal, 0);
2348         __this_cpu_write((mipsr2bremustats).beql, 0);
2349         __this_cpu_write((mipsr2bremustats).bnel, 0);
2350         __this_cpu_write((mipsr2bremustats).blezl, 0);
2351         __this_cpu_write((mipsr2bremustats).bgtzl, 0);
2352 
2353         return 0;
2354 }
2355 
2356 static int mipsr2_stats_open(struct inode *inode, struct file *file)
2357 {
2358         return single_open(file, mipsr2_stats_show, inode->i_private);
2359 }
2360 
2361 static int mipsr2_stats_clear_open(struct inode *inode, struct file *file)
2362 {
2363         return single_open(file, mipsr2_stats_clear_show, inode->i_private);
2364 }
2365 
2366 static const struct file_operations mipsr2_emul_fops = {
2367         .open                   = mipsr2_stats_open,
2368         .read                   = seq_read,
2369         .llseek                 = seq_lseek,
2370         .release                = single_release,
2371 };
2372 
2373 static const struct file_operations mipsr2_clear_fops = {
2374         .open                   = mipsr2_stats_clear_open,
2375         .read                   = seq_read,
2376         .llseek                 = seq_lseek,
2377         .release                = single_release,
2378 };
2379 
2380 
2381 static int __init mipsr2_init_debugfs(void)
2382 {
2383         struct dentry           *mipsr2_emul;
2384 
2385         if (!mips_debugfs_dir)
2386                 return -ENODEV;
2387 
2388         mipsr2_emul = debugfs_create_file("r2_emul_stats", S_IRUGO,
2389                                           mips_debugfs_dir, NULL,
2390                                           &mipsr2_emul_fops);
2391         if (!mipsr2_emul)
2392                 return -ENOMEM;
2393 
2394         mipsr2_emul = debugfs_create_file("r2_emul_stats_clear", S_IRUGO,
2395                                           mips_debugfs_dir, NULL,
2396                                           &mipsr2_clear_fops);
2397         if (!mipsr2_emul)
2398                 return -ENOMEM;
2399 
2400         return 0;
2401 }
2402 
2403 device_initcall(mipsr2_init_debugfs);
2404 
2405 #endif /* CONFIG_DEBUG_FS */
2406 

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